JP2001345447A - Thin-film transistor, liquid crystal display, semiconductor device, and their manufacturing methods - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a TFT, an LCD, a semiconductor device, and their manufacturing methods wherein the TFT contains low-concentration impurities with a high accuracy restrictedly in the shallow surface-layer portion of its channel. SOLUTION: The manufacturing method of a TFT has a process for forming semiconductor films 3a, 3b on a substrate 1 and has a process for implanting conductive impurities into the semiconductor films, by exposing the substrate to a plasma atmosphere 30 containing the conductive impurities for the semiconductor films in the state wherein at least a channel region of the semiconductor films is exposed to the plasma atmosphere.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT), a liquid crystal display (LCD: L
More specifically, the present invention relates to a semiconductor film and a gate insulating film by doping a predetermined region with a conductive impurity from a plasma atmosphere before forming a gate insulating film. TFT, LCD and semiconductor device formed by performing high-precision low-concentration doping without damaging the semiconductor device,
And their production methods.

[0002]

2. Description of the Related Art FIG.
This will be described with reference to FIGS. As shown in FIG. 27, after forming a base film of SiO ₂ 102 on a glass substrate 101, an amorphous silicon film is stacked on the base film 102. The amorphous silicon film is subjected to a process such as laser annealing to convert the amorphous silicon film into a polycrystalline silicon film. Thereafter, a channel pattern is formed on the resist by photolithography, and patterning is performed by dry etching using the resist as a mask to form a channel-shaped polycrystalline silicon film 103b, and the resist is removed (FIG. 27). Next, as shown in FIG. 28, a gate insulating film 104 is formed. Next, as shown in FIG. 29, a channel pattern 103c doped with a conductive impurity is formed in the channel region to control the threshold voltage Vth. At this time, ions are accelerated and implanted into the channel region located below the gate insulating film in order to dope a conductive impurity through the gate insulating film, so that some problems described later occur.

Following the above-described doping of the channel region, as shown in FIG. 30, the entire region of the TFT is covered with a resist mask 121, and a polycrystalline silicon pattern serving as a lower electrode of a capacitor portion is provided with a high-concentration conductive film. A lower impurity electrode 103d is formed by implanting a conductive impurity.

[0004] The subsequent manufacturing method is performed in accordance with a normal LCD manufacturing method. The gate electrode wiring and the upper electrode wiring of the capacitor are patterned on the gate insulating film.
Next, a resist pattern covering the p-type TFT of the drive circuit portion and covering the LDD regions of all the other n-type TFTs is implanted, and phosphorus (P) ions are implanted at a high concentration by ion implantation. Then, an n + impurity region is formed in the drain region and the terminal portion of the capacitor lower electrode. Next, excluding the resist 121, an n − impurity region, which is a low concentration impurity region for relaxing an electric field, is formed in an LDD (Lightly Doped Drain) region. Next, a resist pattern covering the n-type TFT and the capacitor portion is formed, and boron (B) ions, which are p-type impurity ions, are introduced into the same region at a high concentration, thereby forming the source and drain regions of the p-type TFT. I do.

[0005] The implantation of impurities is completed at this stage. Next, an interlayer insulating film is formed, and a contact hole for connecting the source / drain region to the source / drain electrode wiring is opened by dry etching. A conductive layer is formed in the contact hole and on the interlayer insulating film and patterned to form source and drain electrode wirings.
Next, a hydrogenation treatment is performed to improve electric characteristics of the channel region, such as improvement in mobility. Next, after applying a flattening film, a pixel contact hole is opened. Next, a pixel electrode is patterned by forming and patterning a transparent electrode film. As described above, the lower electrode including the TFTs in the drive circuit region and the pixel region is formed, and the liquid crystal is held between the lower electrode and the upper transparent electrode, thereby forming the LCD.

[0006]

In the above-described manufacturing method, in the channel doping step, impurities are implanted through the gate insulating film. Therefore, an ion, which is an impurity, is implanted by applying an acceleration voltage higher than a predetermined value. Therefore, the following problem occurs. (A) In a portion above the channel region, the gate insulating film is damaged and conductive impurities are partially contained. FIG. 31 is a diagram showing a range distribution of particles injected into a solid. In the case where impurities are implanted into the channel region with the gate insulating film, 50 ke is applied so that the concentration of the channel region becomes about 10 ¹⁷ / cm ^3.
Impurity ions are implanted at an acceleration voltage of about V. At this time, since the thickness of the gate insulating film is about 50 nm, about 5 × 10 ^{16 to} about 5 × 10 ¹⁷ impurities are contained in the gate insulating film. These impurities impair the withstand voltage of the gate insulating film and the withstand voltage of the capacitor dielectric of the pixel capacitor portion when used in an LCD. (B) The crystallinity of the channel region itself deteriorates due to the ion implantation. (C) There is a concentration variation peculiar to the implantation of the low-concentration conductive impurities.

As a result, the reliability of the TFT or LCD is reduced, and the mobility of charge carriers in the TFT or LCD is reduced. In addition, since the control at a low concentration is not sufficiently performed, the concentration of the conductive impurity varies, and as a result, there is a problem that precise control of the threshold voltage Vth cannot be performed.

Accordingly, the present invention provides a TFT, an LCD, a semiconductor device, and a method of manufacturing the same, which can perform low-concentration channel doping with high accuracy without damaging the crystallinity of a gate insulating film or a channel region. The purpose is to provide.

[0009]

According to the first aspect of the present invention, T
The method of manufacturing an FT includes a step of forming a semiconductor film on a substrate, and a step of forming a semiconductor film formed in the semiconductor film forming step in a plasma atmosphere containing conductive impurities with respect to the semiconductor film in a state where at least a channel region is exposed. A step of exposing the substrate to introduce conductive impurities into the semiconductor film (claim 1).

Although the impurity ions in the plasma atmosphere do not have a large momentum in a specific direction, each impurity ion has a momentum corresponding to the temperature. Therefore, doping is performed without damaging the crystallinity of the semiconductor film. Conventionally, impurity ions were accelerated and introduced into the channel region through the gate insulating film. However, in the present invention, impurity ions are directly introduced from the channel surface to the surface layer. As a result, the crystallinity of the gate insulating film is not hindered and impurities are not contained in the gate insulating film, and the reliability such as the withstand voltage of the gate insulating film is improved. When this TFT is used in, for example, an LCD, the gate insulating film is used as a dielectric film in a capacitance portion of a pixel region, and therefore, improvement in withstand voltage is very important. Further, since the momentum of each impurity ion in the plasma atmosphere is smaller than the momentum of ions accelerated by the ion implantation apparatus, damage to the channel region in the TFT is prevented. As a result, a decrease in the mobility of the charge carriers is prevented, and the original mobility can be secured. In addition, since the above-described doping by exposure to the plasma atmosphere can be performed with high precision at a low concentration only in the surface layer portion, the threshold voltage Vth can be controlled with high precision.

The above semiconductor film may be an amorphous silicon film or a polycrystalline silicon film crystallized by laser annealing or the like. Further, it may be a formed film or a patterned film in which the film is patterned. Further, the plasma atmosphere is preferably generated by mounting the substrate in a plasma generator such as a plasma CVD apparatus, but is not limited to this. The conductive impurity source included in the plasma atmosphere may be a source to which a source gas of the conductive impurity is supplied, or may be a conductive impurity source which is not. It is desirable that the plasma atmosphere be mainly made of a source gas such as an oxygen gas from the outside and used as a plasma atmosphere source. In addition, the semiconductor film may be formed directly on the substrate, or may be formed via a base film or another film.

In the method of manufacturing a TFT according to the first aspect, the semiconductor film is an amorphous silicon film,
After the step of introducing conductive impurities, a step of crystallizing the amorphous silicon film into a polycrystalline silicon film is provided.

When impurities are introduced from the plasma atmosphere,
The impurities are limited to a predetermined shallow depth from the surface. However, impurities are introduced at the stage of the amorphous silicon film,
For example, when amorphous silicon is partially melted by, for example, laser annealing for crystallization, impurities are distributed to a deeper position and have a lower concentration. Therefore,
When laser annealing is performed,
Low concentration doping can be accurately performed. However, in the case of polycrystal formation by lamp annealing, the effect of impurity introduction from the plasma atmosphere is maintained, and the surface is limited to a shallower portion than the conventional impurity implantation by ion implantation. In addition, even in the case of the polycrystallizing treatment by laser annealing, the effect of distributing high-concentration impurities to the surface layer of the silicon film is maintained depending on the laser irradiation conditions of laser annealing.

In the method of manufacturing a TFT according to the first aspect, the step of forming a semiconductor film includes a step of forming an amorphous silicon film and a step of crystallizing the amorphous silicon film to form a polycrystalline silicon film. (Claim 3).

According to this structure, it is possible to dope a low-concentration impurity with high precision only in the surface layer portion of polycrystalline silicon.

In the method of manufacturing a TFT according to the first aspect,
Ashing a resist containing a conductive impurity provided on a substrate to include the conductive impurity in a plasma atmosphere.

Usually, conductive impurities are often implanted into a semiconductor film using a resist as a mask. For example, in some cases, a conductive impurity is implanted into a lower electrode of a capacitor portion in a patterned polycrystalline silicon film. At this time, each polycrystalline silicon film forming the transistor does not contain a conductive impurity. First, a resist pattern with an opening at a location corresponding to the lower electrode of the capacitor portion is formed,
Implant conductive impurities. This conductive impurity, of course,
It is also implanted in the resist pattern and is contained in the resist. Thereafter, with the resist pattern attached, the substrate is loaded into a plasma generator, for example, a plasma CVD apparatus, and the resist is ashed to include the components in a plasma atmosphere. This plasma atmosphere naturally contains the conductive impurity ions. The polycrystalline silicon covered by the resist
Exposure to the above plasma atmosphere will introduce conductive impurities into the surface layer. Since the step of introducing the conductive impurities proceeds in parallel with the removal of the resist, not only the above-described property improvement can be obtained, but also the manufacturing cost can be reduced and the delivery time can be shortened by omitting the step.

In the method of manufacturing a TFT according to the first aspect,
Ashing is performed on the deposits containing the conductive impurities and attached to the inner wall of the plasma generator, so that the plasma atmosphere contains the conductive impurities.

In a plasma CVD apparatus or the like, after a conductive impurity is ashed to be in a plasma state, it often adheres to the inner wall as a deposit when the power is turned off. This deposit can be used as a suitable source of conductive impurities in the plasma atmosphere.

A method of manufacturing an LCD according to a first aspect of the present invention is a method of manufacturing a liquid crystal display device of an active matrix system, wherein the method of manufacturing a TFT according to any one of the TFTs of the first aspect is used. Then, a TFT is formed on the lower substrate located below the liquid crystal (claim 6).

According to this configuration, it is possible to obtain an LCD having a gate insulating film and a capacitor dielectric film having no problem in withstand voltage, and a channel region having no decrease in mobility of charge carriers. In addition, the LCD can control the threshold voltage Vth with high accuracy, and can obtain high-quality display with durability.

According to a first aspect of the present invention, in a method of manufacturing a semiconductor device, a semiconductor is exposed to a plasma atmosphere containing a conductive impurity for the semiconductor while at least a channel region on a surface of the semiconductor substrate is exposed. A step of introducing a conductive impurity into the surface of the semiconductor;

The doping of the semiconductor substrate at a low concentration can be performed accurately by mixing conductive impurities into the molten phase when pulling up the semiconductor crystal from a molten state such as the Czochralski method. However, the conductive impurities are distributed throughout the semiconductor substrate. For example, when performing low-concentration doping with high precision only in a shallow region of the surface layer portion of the channel region, the method of the present invention is used.

Since each impurity ion in the plasma atmosphere has a momentum in a random direction according to the temperature, it is doped without damaging the crystallinity of the semiconductor film. For this reason, conventionally, impurity ions were accelerated and introduced into the channel region through the gate insulating film.
In the present invention, impurity ions are directly introduced from the channel surface. As a result, the crystallinity of the gate insulating film is not hindered and impurities are not contained in the gate insulating film, and the reliability such as the withstand voltage of the gate insulating film is improved. Further, since the momentum of each impurity ion in the plasma atmosphere is smaller than the momentum of ions accelerated by the ion implantation apparatus, damage to the channel region in the semiconductor device is prevented. As a result, a decrease in the mobility of the charge carriers is prevented, and the original mobility can be secured. In addition, since the above-described doping by plasma atmosphere exposure can be performed with high accuracy even at a low concentration only in a shallow region of the surface layer, the threshold voltage Vth
Can be controlled with high accuracy.

In the method of manufacturing a semiconductor device according to the first aspect of the present invention, a resist containing a conductive impurity provided on a semiconductor substrate is ashed to include the conductive impurity in a plasma atmosphere. ).

For example, there is a case where a capacitance portion is formed in a semiconductor device. In this case, a resist pattern in which a portion corresponding to the lower electrode is first opened is used to inject conductive impurities into the lower electrode of the capacitor portion. At this time, the surface of the semiconductor substrate on which the transistor is formed does not contain conductive impurities. First, the above resist pattern is formed, and conductive impurities are implanted. This conductive impurity is naturally implanted into the resist pattern and is contained in the resist. Thereafter, with the resist pattern applied, the semiconductor surface is loaded into a plasma generator, for example, a plasma CVD apparatus, and the resist is ashed to be included in a plasma atmosphere. The plasma atmosphere naturally contains the conductive impurity ions. The semiconductor surface covered with the resist
Exposure to the above plasma atmosphere will introduce conductive impurities into the surface layer. Since the step of introducing the conductive impurities proceeds in parallel with the removal of the resist, not only the above-described property improvement can be obtained, but also the manufacturing cost can be reduced and the delivery time can be shortened by omitting the step.

In the method of manufacturing a semiconductor device according to the first aspect of the present invention, ashing is performed on an adhered substance containing conductive impurities and adhered to an inner wall of a plasma generator, so that the plasma atmosphere contains conductive impurities. (Claim 9).

In a plasma CVD apparatus or the like, after the conductive impurities are ashed to be in a plasma state, they often adhere to the inner wall when power is turned off. This deposit can be used as a suitable source of conductive impurities.

The TFT according to the first aspect of the present invention has a channel pattern of a semiconductor film, and a concentration of a conductive impurity in a gate insulating film below the gate electrode is 10 ¹⁶ / cm ³ or less. ).

By setting the concentration of the conductive impurity in the gate insulating film in the above portion to 10 ¹⁶ / cm ³ or less, the withstand voltage and the like of the gate insulating film can be improved and a highly reliable TFT can be obtained. The above impurity concentration is 5 × 10 ¹⁵ / c
m ³ or less, and preferably 5 × 10 ¹⁵ / cm ³ or less in order to improve the pressure resistance of the gate insulating film. According to the manufacturing method of the present invention, the impurity concentration is 5
It is sufficiently possible to set it to × 10 ¹⁵ / cm ³ or less.

In the TFT according to the first aspect, the concentration of the conductive impurity at a depth of 30 nm from the surface of the channel region of the semiconductor film is 5 × 10 ¹⁵ / cm ³ or less. .

The impurities introduced from the plasma atmosphere are:
In the case of polycrystallization by lamp annealing or laser annealing within a predetermined irradiation condition, the effect of impurity introduction from the plasma atmosphere is maintained, and the effect is limited to the surface layer portion of the channel region. For this reason, since the control by the gate voltage is well performed, a highly reliable transistor operation can be performed.

The LCD according to the first aspect of the present invention is an active matrix LCD, in which the concentration of conductive impurities in a gate insulating film below a gate electrode of a TFT provided in the LCD is 10 ¹⁶ / cm ^3. It is as follows (claim 12).

With this configuration, the LCD of the present invention can ensure high display quality with high durability. The impurity concentration is desirably 5 × 10 ¹⁵ / cm ³ or less in order to improve the breakdown voltage of the gate insulating film. According to the manufacturing method of the present invention, the impurity concentration is 5 × 10 ¹⁵
It is sufficiently possible to make it equal to or less than / cm ³ .

In the LCD of the first aspect, L
The concentration of the conductive impurity in the capacitance dielectric film of the capacitance portion provided in the pixel region of the lower substrate of the CD is 10 ¹⁶ / cm ³ or less (claim 13).

With the above configuration, the withstand voltage of the dielectric film in the capacity of the pixel region is improved, and the present LCD can maintain high durability and high quality display. The above impurity concentration is 5 to improve the withstand voltage of the gate insulating film.
It is more preferable that the concentration is not more than × 10 ¹⁵ / cm ^3, and it can be achieved with a margin by the above-mentioned manufacturing method.

In the LCD according to the first aspect, the concentration of the conductive impurity at a depth of 30 nm from the surface of the channel region below the gate electrode is 5 × 10 ¹⁵ / cm ^3.
It is as follows (claim 14).

The above configuration is realized in the case where a polycrystal is formed by lamp annealing or in the case of laser annealing within a predetermined condition range. With this configuration, the controllability of the threshold voltage Vth by the gate is improved, the channel control is facilitated, and high-speed display with high reliability can be performed.

In a semiconductor device according to a first aspect of the present invention, the concentration of conductive impurities in a gate insulating film below a gate electrode of a transistor formed on a surface of a semiconductor substrate is 10 ¹⁶ / c.
m ³ or less (claim 15).

With the above structure, the withstand voltage and the like of the gate insulating film in this semiconductor device are improved, and a highly reliable TFT is formed.
It can be.

In the semiconductor device according to the first aspect, the semiconductor device further has a depth of 30 from the surface of the channel region below the gate electrode.
The concentration of the conductive impurity at the position of nm is 5 × 10 ¹⁵
/ cm ³ or less (claim 16).

In the case where a polycrystal is formed by lamp annealing or in the case of laser annealing within a predetermined condition range,
The above configuration can be realized. With this configuration,
Since the conductive impurities are not distributed deeply into the channel region, the threshold voltage V
th controllability can be improved, and channel control can be facilitated.

[0043]

Next, embodiments of the present invention will be described with reference to the drawings.

Embodiment Mode 1 In this embodiment mode, at the stage of forming an amorphous silicon film, the surface is exposed to a plasma atmosphere to introduce conductive impurities. First, a base film 2 composed of, for example, a two-layer film of SiN and SiO ₂ is formed on a glass substrate 1, and then an amorphous silicon film 3a is formed by low-pressure CVD, as shown in FIG. Next, as shown in FIG. 2, the amorphous silicon film is exposed to, for example, plasma of an n-type conductive impurity formed by a plasma generator. This n-type conductive impurity can be externally introduced into the plasma generator as a gas. Also, this conductive impurity is
An attachment containing conductive impurities attached to the inner wall of the plasma generator may be used. If there is a step using a resist in the previous step, the resist may be ashed to a plasma state. This is because the resist used as a mask in the impurity implantation contains the impurity. In this embodiment mode, an impurity is introduced at the stage of amorphous silicon, and then crystallized while being melted or partially melted by laser annealing. For this reason, it is possible to distribute the impurity in a deeper range and to control the concentration to a lower concentration with high accuracy.

Thereafter, as shown in FIG. 3, the amorphous silicon 3 is subjected to laser annealing using an excimer laser.
is crystallized into polycrystalline silicon 3c. After this, FIG.
As shown in (1), the polycrystalline silicon 3c is patterned. In FIG. 4, reference numeral 51a denotes an n-type TF in the drive circuit area.
A portion where T is formed, and 51b is a portion where a p-type TFT is formed. Reference numeral 52 denotes a capacitance forming portion in the pixel region, and reference numeral 53 denotes a portion where two n-type TFTs are formed. Next, as shown in FIG. 5, a gate insulating film 4 is formed thereon. Next, as shown in FIG. 6, a resist pattern 21 is formed to cover the region of the TFT other than the lower electrode 3d of the capacitor portion. Lower electrode 3
forming d. At the time of FIG. 6, two n
The polycrystalline silicon films constituting the n-type TFT and the n-type and p-type TFT in the drive circuit region contain conductive impurities introduced by the above-described plasma atmosphere exposure. Next, the resist pattern 21 is removed to form a conductive film, and then, as shown in FIG. 7, patterning is performed on the gate electrode wiring 5 and the upper electrode wiring 6 of the capacitor. Next, a resist pattern 22 is formed to cover the p-type TFT of the drive circuit section and cover the LDD regions of all other n-type TFTs. Next, as shown in FIG. 8, phosphorus (P) ions are implanted at a high concentration by ion implantation to form n + -type impurity regions 3s in the source and drain regions of the n-type TFT and the terminal portions of the capacitor lower electrode. . Then, FIG.
As shown in FIG.
An n-impurity region 3m, which is a low-concentration impurity region for relaxing an electric field, is formed in a doped drain region. An n − impurity region 3 m is also formed in the source and drain regions of the p-type TFT. In a p-type TFT, however, as shown in FIG.
A resist pattern 23 covering the TFT and the capacitor is formed, and boron (B) ions, which are p-type impurity ions, are introduced into the same region at a high concentration. As a result, a p-type impurity region 3h more than offsetting the n-type impurity is formed, and the p-type TFT is formed.
Source and drain regions are formed.

The implantation of the impurity ends at the stage up to FIG. Then, after removing the resist pattern 23, as shown in FIG. 11, an interlayer insulating film 7 is formed, and a contact hole 18 for connecting the source and drain regions and the source and drain electrode wirings 8 and 9 is dry-etched. (FIG. 12). A conductive layer is formed in the contact hole and on the interlayer insulating film 7 and patterned to form source and drain electrodes 8 and 9 (FIG. 1).
3). Next, as shown in FIG. 14, a hydrogenation treatment is performed to improve electric characteristics of the channel region such as improvement of mobility. Next, as shown in FIG.
, A pixel contact hole 19 is opened.
Next, a transparent electrode film is formed and patterned, and the pixel electrode shown in FIG. 16 is patterned.

According to the above-described manufacturing method, the gate insulating film and the channel region below the gate electrode wiring are formed without the gate electrode in the steps other than the step of exposing the conductive impurities to the plasma shown in FIG. No ion irradiation is performed. Therefore, the channel region and the gate insulating film immediately above the channel region are not damaged. Further, low-concentration impurities can be introduced into the channel region limited to the surface layer portion with high accuracy. For this reason, Vth can be adjusted with high accuracy, mobility can be prevented from lowering, and a highly reliable liquid crystal display device can be provided.

The TF of the LCD manufactured by the above manufacturing method
At T, the impurity concentration in the gate insulating film below the gate electrode and the impurity concentration in the dielectric film in the capacitor portion are 10 ¹⁶ / c
m ³ or less. For this reason, it becomes possible to improve the pressure resistance of these insulating films. Further, in the channel region, doping can be limited within a surface layer depth of 15 nm. Therefore, the impurity concentration at a depth of 30 nm from the surface is 5 × 10 ¹⁵ / cm ³ or less, and the channel control of the gate can be strengthened.

(Embodiment 2) In this embodiment, first, a base film 2 is formed on a glass substrate 1, and then, FIG.
As shown in FIG. 7, an amorphous silicon film 3a is formed. Next, as shown in FIG. 18, the amorphous silicon film is converted into a polycrystalline silicon film 3b by laser annealing.
To In this state of the polycrystalline silicon, as shown in FIG. 19, the substrate is exposed to a plasma of a conductive impurity to form a low-concentration conductive impurity region 3c. Since this impurity is limited to the surface portion of the channel region, it is possible to improve the controllability of the threshold voltage Vth by the gate.

The subsequent manufacturing method follows the steps from FIG. 4 onward in the first embodiment. Therefore, the gate insulating film and the channel region below the gate electrode wiring are not irradiated with ions from above without the gate electrode in the steps other than the step of exposing the conductive impurities to plasma shown in FIG. Therefore, the crystallinity of the gate insulating film or the channel region is not damaged, and no impurity is contained in the gate insulating film or the capacitor insulating film. As a result, a highly reliable LCD can be provided.

(Embodiment 3) In this embodiment, an amorphous silicon film is formed on the base film 2 and then crystallized by laser annealing or the like to form a polycrystalline silicon film. Next, as shown in FIG. 20, the polycrystalline silicon film is patterned to form an island-shaped transistor pattern. In order to introduce impurities into the transistor pattern, the polycrystalline silicon pattern is exposed to a plasma atmosphere of n-type conductive impurities using a plasma generator into which n-type conductive impurities are introduced (FIG. 21). . Due to this exposure, n-type impurities are introduced with high precision only to the surface layer of polycrystalline silicon. As a result, a gate insulating film and a capacitor insulating film having excellent withstand voltage can be obtained, and a TFT having high mobility can be obtained. further,
Since a low-concentration impurity layer with high precision is formed only in the shallow surface layer, the controllability of the threshold voltage Vth can be increased.

(Fourth Embodiment) A manufacturing method according to a fourth embodiment will be described with reference to FIGS. The amorphous silicon film formed on the base film 2 is made into a polycrystalline silicon film by laser annealing or the like, and is then patterned to form an island-shaped pattern 3b as shown in FIG. Next, a resist pattern 24 covering the TFT region other than the capacitor portion is formed, and then, for example, an n-type impurity is introduced into the lower electrode portion of the capacitor portion (FIG. 23). Next, the resist is removed using oxygen plasma as a process for removing the resist. The ashing conditions at this time are as follows. (A) Pressure: 27 Pa (b) O ₂ flow rate: 300 sccm (standard cubic cm / m
in) (c) RF power: 1 kW (d) Time: 250 seconds (e) Mode: RIE (Reactive Ion Etching) At this time, as shown in FIG. Phosphorus (P) is supplied to the plasma atmosphere to introduce phosphorus into the polycrystalline silicon.

According to the above arrangement, the resist removing step and the impurity introducing step can be performed in one step.
As a result, it is possible to reduce the manufacturing cost and the delivery time.

(Fifth Embodiment) A fifth embodiment will be described with reference to FIGS. As shown in FIG. 25, the resist 25 containing phosphorus is processed in an oxygen plasma by an ashing device, thereby forming a thin film 32 of a compound containing phosphorus on the side wall of the plasma processing chamber. The patterned silicon substrate is carried into the processing chamber, and is exposed to oxygen plasma to introduce impurities.

According to the above configuration, a plasma atmosphere containing conductive impurities can be easily formed without providing a facility for introducing impurity gas.

Although the embodiments of the present invention have been described above, the embodiments of the present invention disclosed above are merely examples, and the scope of the present invention is not limited to these embodiments. Not limited. The scope of the present invention is shown by the description of the claims, and further includes all modifications within the meaning and scope equivalent to the description of the claims.

[0057]

According to the present invention, a conductive impurity can be doped into a channel region by exposing to a plasma atmosphere without using an ion doping apparatus or the like. For this reason, low-concentration doping can be performed with high accuracy, so that the control of the threshold voltage Vth can be performed with high accuracy. In addition, since the channel region is not irradiated with high-speed ions, high mobility can be secured.
Further, since impurity ions are not implanted through the gate insulating film, conductive impurities are not contained in the gate insulating film and crystallinity is not impaired, so that it is possible to obtain an LCD or semiconductor device having high reliability such as withstand voltage. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view at a stage when an amorphous silicon film is formed on a base film in Embodiment 1 of the present invention.

FIG. 2 is a cross-sectional view showing a state in which the substrate in FIG. 1 is exposed to a plasma atmosphere to introduce impurities.

FIG. 3 is a cross-sectional view of a stage in which the amorphous silicon film in the state of FIG. 2 is laser-annealed into a polycrystalline silicon film.

FIG. 4 is a cross-sectional view at the stage when the polycrystalline silicon film in the state of FIG. 3 is patterned into a channel shape.

FIG. 5 is a cross-sectional view at the stage when a gate insulating film is formed on the state of FIG. 4;

FIG. 6 is a cross-sectional view showing a state in which a region of a TFT is covered with a resist and high-concentration impurities are implanted into a lower capacitor electrode to form a lower capacitor electrode in the state of FIG. 5;

7 is a cross-sectional view at the stage where the resist is removed from the state of FIG. 6 and a gate electrode and a capacitor upper electrode are patterned on a gate insulating film.

FIG. 8 shows a state in which the entire region of the p-type TFT and the LDD portion of the n-type TFT are covered with a resist, n-type impurities are implanted at a high concentration, and source and drain regions are formed. It is sectional drawing.

FIG. 9 is a cross-sectional view showing a state in which the resist is removed from the state of FIG. 8 and an n-type impurity is implanted at a low concentration to form an LDD region.

10 is a cross-sectional view of the state of FIG. 9 in which an n-type TFT and a capacitor are covered with a resist, and a source and a drain of the p-type TFT are heavily implanted with p-type impurities.

11 is a cross-sectional view at the stage when an interlayer insulating film is formed on the state of FIG.

FIG. 12 is a cross-sectional view showing a state where a contact hole is opened in the state of FIG. 11;

13 is a cross-sectional view at the stage where the source and drain electrode films are formed and the wiring is patterned in the state of FIG. 12;

FIG. 14 is a cross-sectional view of a stage in which hydrogenation is being performed in a hydrogen atmosphere in the state of FIG. 13;

15 is a cross-sectional view at the stage where a planarizing film is formed in the state of FIG. 14 and a pixel contact hole is opened.

FIG. 16 is a cross-sectional view of a state where a transparent electrode filling a pixel contact hole is formed in the state of FIG.

FIG. 17 is a cross-sectional view at a stage where an amorphous silicon film is formed on a base film in the second embodiment of the present invention.

FIG. 18 is a cross-sectional view of a state where a polycrystalline silicon film is obtained by performing a laser annealing process on the state of FIG. 17;

19 is a cross-sectional view of a state where the polycrystalline silicon in the state of FIG. 18 is exposed to a plasma atmosphere.

FIG. 20 is a cross-sectional view at a stage where a polycrystalline silicon film is patterned in Embodiment 3 of the present invention.

FIG. 21 is a cross-sectional view at the stage where the device shown in FIG. 20 is exposed to a plasma atmosphere.

FIG. 22 is a sectional view of a stage where polycrystalline silicon is patterned in Embodiment 4 of the present invention.

FIG. 23 shows n-type and p-type T
FIG. 11 is a cross-sectional view at a stage where an area of the FT is covered with a resist and a capacitor lower electrode is heavily doped with impurities.

24. Ashing the resist from the state of FIG. 23 and setting the plasma atmosphere to an n-type TFT and a p-type TF
FIG. 5 is a cross-sectional view of a stage in which an impurity is introduced into a T channel shape.

FIG. 25 is a cross-sectional view of a stage in which an attachment for forming a plasma atmosphere is formed on the side wall of the plasma generator by ashing of a resist or the like in the fifth embodiment of the present invention.

FIG. 26 is a cross-sectional view of a state where power is applied to form a plasma atmosphere from side wall deposits and impurities are introduced into the TFT channel shape in the state of FIG. 25;

FIG. 27 is a cross-sectional view at a stage where polycrystalline silicon is patterned in a conventional LCD manufacturing method.

FIG. 28 is a cross-sectional view of a state where a gate insulating film is formed in the state of FIG. 27;

FIG. 29 is a cross-sectional view showing a state where impurity ions accelerated by an ion implantation apparatus are implanted in the state of FIG. 28;

30 shows an n-type TFT and a p-type TF in the state shown in FIG. 29.
FIG. 9 is a cross-sectional view of a stage in which T is covered with a resist and impurities are implanted at a high concentration into a capacitor lower electrode.

FIG. 31 is a diagram showing the existence distribution of particles implanted in a solid.

[Explanation of symbols]

1 substrate, 2 base film, 3a amorphous silicon film, 3b polycrystalline silicon film (does not contain impurities),
3c impurity-containing polycrystalline silicon film, 3d capacitor lower electrode (n + impurity region), 3s n + impurity region, 3m
LDD region, 3hp + impurity region, 4 gate insulating film (capacitive dielectric), 5 gate electrode, 6 capacitive upper electrode,
7 interlayer insulating film, 8 source electrode wiring, 9 drain electrode wiring, 11 transparent electrode, 18 contact hole, 1
9 Pixel contact holes, 21, 22, 23, 24
Resist, 30 plasma atmosphere, 31 hydrogen atmosphere,
32: Deposits on the side wall of the plasma generator, 51a n-type TFT of drive circuit, 51b p-type TFT of drive circuit, 52
Capacitance part in pixel area, 53 two TFT formation parts in pixel area.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 21/265 H01L 21/265 F 21/336 29/78 617S (72) Inventor Masanao Kobayashi Suwa-shi, Nagano 3-5, Yamato F-term in Seiko Epson Corporation (reference) 2H092 JA25 JA34 JB61 KA04 KA10 KA12 MA08 MA15 MA27 MA30 MA35 NA24 NA27 5C094 AA25 AA42 AA43 AA44 AA55 BA03 BA43 CA19 DA13 DB01 DB04 EB02 FB01 JA02 FB02 5F052 AA02 BB07 DA02 DB02 HA06 HA07 JA01 5F110 AA08 AA12 AA30 BB02 CC02 DD02 DD13 DD14 DD17 GG02 GG13 GG32 GG37 GG52 HJ01 HJ12 HM15 NN02 NN72 PP03 QQ11 QQ19 QQ21

Claims (16)

[Claims] A step of forming a semiconductor film on a substrate; and exposing at least a channel region of the semiconductor film formed in the semiconductor film forming step to a plasma atmosphere containing a conductive impurity for the semiconductor film. Exposing the substrate and introducing the conductive impurity into the semiconductor film. 2. The semiconductor device according to claim 1, wherein the semiconductor film is an amorphous silicon film, and after the step of introducing the conductive impurities, a step of crystallizing the amorphous silicon film into a polycrystalline silicon film is provided. Method for manufacturing thin film transistor. 3. The method according to claim 1, wherein the step of forming the semiconductor film includes a step of forming an amorphous silicon film and a step of crystallizing the amorphous silicon film into a polycrystalline silicon film. A method for manufacturing a thin film transistor. 4. The method for manufacturing a thin film transistor according to claim 1, wherein ashing is performed on a resist including the conductive impurity provided on the substrate to include the conductive impurity in a plasma atmosphere. . 5. The plasma atmosphere according to claim 1, wherein ashing is performed on a substance containing the conductive impurities and adhered to an inner wall of the plasma generator, so that the plasma atmosphere contains the conductive impurities. A method for manufacturing the thin film transistor according to the above. 6. A method of manufacturing an active matrix type liquid crystal display device, comprising using the method of manufacturing a thin film transistor according to claim 1 on a lower substrate located below a liquid crystal. Forming a liquid crystal display device. 7. The semiconductor is exposed to a plasma atmosphere containing a conductive impurity for the semiconductor while at least a channel region on the surface of the semiconductor substrate is exposed, thereby introducing the conductive impurity to the surface of the semiconductor. A method for manufacturing a semiconductor device, comprising the steps of: 8. The method of manufacturing a semiconductor device according to claim 7, wherein ashing is performed on a resist including the conductive impurity provided on the semiconductor substrate, so that the plasma atmosphere includes the conductive impurity. 9. The semiconductor according to claim 7, wherein the deposit containing the conductive impurities and adhering to the inner wall of the plasma generator is ashed so that the plasma atmosphere contains the conductive impurities. Device manufacturing method. 10. A thin film transistor having a channel pattern of a semiconductor film, wherein a concentration of a conductive impurity in a gate insulating film below the gate electrode is 10 ¹⁶ / cm ³ or less. 11. The thin film transistor according to claim 10, wherein the concentration of the conductive impurity at a position 30 nm deep from the surface of the channel region of the semiconductor film is 5 × 10 ¹⁵ / cm ³ or less. 12. An active matrix liquid crystal display device, wherein a concentration of a conductive impurity in a gate insulating film below a gate electrode of a thin film transistor provided in the liquid crystal display device is 10 ¹⁶ / cm ³ or less. Liquid crystal display. 13. The liquid crystal display device according to claim 12, wherein the concentration of the conductive impurity in the capacitance dielectric film of the capacitance portion provided in the pixel region of the lower substrate of the liquid crystal display device is 10 ¹⁶ / cm ³ or less. Liquid crystal display. 14. The semiconductor device according to claim 1, wherein the concentration of the conductive impurity at a depth of 30 nm from the surface of the channel region below the gate electrode is 5 × 10 ¹⁵ / cm ³ or less.
14. The liquid crystal display device according to 2 or 13. 15. A semiconductor device in which the concentration of a conductive impurity in a gate insulating film located below a gate electrode of a transistor formed on a surface of a semiconductor substrate is 10 ¹⁶ / cm ³ or less. 16. The semiconductor device according to claim 15, wherein the concentration of the conductive impurity at a depth of 30 nm from the surface of the channel region located below the gate insulating film is 5 × 10 ¹⁵ / cm ³ or less. Semiconductor device.