JPH03266435A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH03266435A JPH03266435A JP6566890A JP6566890A JPH03266435A JP H03266435 A JPH03266435 A JP H03266435A JP 6566890 A JP6566890 A JP 6566890A JP 6566890 A JP6566890 A JP 6566890A JP H03266435 A JPH03266435 A JP H03266435A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxidation
- element isolation
- resistant
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000002955 isolation Methods 0.000 claims abstract description 60
- 230000003647 oxidation Effects 0.000 claims abstract description 42
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 23
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 22
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 14
- 230000003247 decreasing effect Effects 0.000 abstract description 2
- 239000007788 liquid Substances 0.000 abstract 1
- 230000007423 decrease Effects 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 6
- 239000012528 membrane Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010306 acid treatment Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は半導体装置およびその製造方法に係り、特に高
集積度を実現できる素子分離膜を備えた半導体装置およ
びその製造方法に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, a semiconductor device equipped with an element isolation film that can achieve a high degree of integration and a method for manufacturing the same. Regarding.
（従来の技術）
従来、半導体集積回路装置において、素子間を分離する
素子分離膜としては基板表面に耐酸化性の膜としての窒
化膜を形成し、素子分離膜形成領域のみを除去してそこ
に厚い酸化膜を形成する選択酸化法により形成されたも
のが広く用いられている。代表的なものはＬＯＣＯ３法
であり、シリコン基板上に耐酸化性のシリコン窒化膜を
形成し、素子分離膜形成領域のみを除去して基板表面を
露出させた後に酸化雰囲気中で酸化を行うと、窒化膜の
ない部分のみに厚い酸化膜が形成されるものである。(Prior art) Conventionally, in semiconductor integrated circuit devices, a nitride film as an oxidation-resistant film is formed on the surface of a substrate as an element isolation film for separating elements, and only the region where the element isolation film is formed is removed. Those formed by a selective oxidation method that forms a thick oxide film are widely used. A typical method is the LOCO3 method, in which an oxidation-resistant silicon nitride film is formed on a silicon substrate, only the element isolation film formation region is removed to expose the substrate surface, and then oxidation is performed in an oxidizing atmosphere. , a thick oxide film is formed only in areas where there is no nitride film.
このような従来の素子分離膜は２酸化シリコンのみによ
り形成されているため、その後の工程で膜厚が減少して
しまい、そのために素子間の耐圧か減少し電流かリーク
するという問題がある。Since such a conventional element isolation film is formed only of silicon dioxide, the thickness of the film decreases in subsequent steps, resulting in a problem that the withstand voltage between elements decreases and current leaks.
第３図は従来の素子分離膜における膜厚減少の様子を示
す説明図である。FIG. 3 is an explanatory diagram showing how the thickness of a conventional element isolation film decreases.
半導体基板の表面に、耐酸化性のシリコン窒化膜を用い
て選択酸化を行うＬＯＣＯ５法などによって形成された
素子分離膜は、形成当初には参照番号２で示されたよう
な破線で表わされる形状となっている。ところが、この
素子分離膜の２酸化シリコンは後続の工程において特に
弗酸系の液相処理などにより侵され易く、実線で示され
た素子分離膜２′のように膜厚が減少してしまう。An element isolation film formed on the surface of a semiconductor substrate by the LOCO5 method, which performs selective oxidation using an oxidation-resistant silicon nitride film, initially has a shape indicated by a broken line as shown by reference number 2. It becomes. However, the silicon dioxide of this element isolation film is easily attacked by hydrofluoric acid-based liquid phase treatment in subsequent steps, and the film thickness is reduced as shown by the solid line in the element isolation film 2'.
この例では素子分離膜２′をマスクとしてイオン注入お
よび拡散が行われてＮ＋領域３が素子分離膜２の両側に
形成されているが、第４図（ａ）に示すように素子分離
膜２の上に配線４などが形成されることにより素子分離
膜の両側に形成されたＮ＋領域３とにより寄生トランジ
スタが形成されることがあるが、上述したような膜厚減
少が発生して第４図（ｂ）に示すような薄くなった素子
分離膜２′の状態となると、低電圧でこの寄生トランジ
スタがオンしてリーク電流が流れやすくなる。すなわち
、素子間の耐圧か低下して半導体装置としての特性を損
ねる結果となる。In this example, ion implantation and diffusion are performed using the element isolation film 2' as a mask, and N+ regions 3 are formed on both sides of the element isolation film 2. As shown in FIG. A parasitic transistor may be formed with the N+ regions 3 formed on both sides of the element isolation film due to the formation of the wiring 4 on top of the element isolation film. When the element isolation film 2' becomes thin as shown in FIG. 2B, this parasitic transistor turns on at a low voltage and leakage current tends to flow. In other words, the withstand voltage between the elements decreases, resulting in a loss of characteristics as a semiconductor device.
第４図（ａ）に示した寄生トランジスタでリークか発生
するゲート電圧ｖｔｈは一般にＶｔｈ＝Ａ−（Ｑｏ／Ｃ
ｏ）で表わされる（たたしＡ、ＱＯは定数）。Ｃｏは寄
生容量であって、素子分離膜の厚さが厚いほど小さくな
る。逆に、素子分離膜の厚さが減少するとｖｔｈは低下
することになる。The gate voltage vth that leaks or occurs in the parasitic transistor shown in FIG. 4(a) is generally Vth=A-(Qo/C
o) (Tachi A and QO are constants). Co is a parasitic capacitance, and the thicker the element isolation film is, the smaller it becomes. Conversely, when the thickness of the element isolation film decreases, vth decreases.
従来は８０００Ａの厚さで形成した酸化膜であっても、
第３図に示されたように５０００八にまで減少すること
がある。したがって、第４図（ａ）のように素子分離膜
の膜圧減少がない場合のｖｔｈと第４図（ｂ）のように
素子分離膜の膜圧減少があった場合のｖｔｈとを比較す
ると第４図（ｂ）の方がｖｔｈが低くなってしまう。Even if the oxide film was conventionally formed with a thickness of 8000A,
As shown in FIG. 3, it may be reduced to 50008. Therefore, if we compare vth when there is no decrease in the membrane pressure of the element isolation membrane as shown in Figure 4(a) and vth when there is a decrease in the membrane pressure of the element isolation membrane as shown in Figure 4(b), In FIG. 4(b), vth is lower.
このような問題を解決するために、素子分離膜の上に耐
酸化性の膜、例えばシリコン窒化膜を形成して膜厚の減
少を防止することが提案されている。In order to solve this problem, it has been proposed to form an oxidation-resistant film, such as a silicon nitride film, on the element isolation film to prevent the film thickness from decreasing.
第５図（ａ）はこのような例を示すもので、選択酸化に
よって厚く形成された素子分離膜２の上に再度シリコン
窒化膜５か形成されている。このシリコン窒化膜５は素
子分離膜２の上以外では不要であるから、除去する必要
かあり、このためレジスト６を用いて不要部分の除去か
行われる。しかし、このレジストの位置合わせは精度が
問題であり、第５図（ａ）に示すようにレジストの合わ
せずれが生じた場合には第５図（ｂ）に示すように一方
側ではシリコン窒化膜５の端部が素子分離膜の端部から
長さａたけ内側に位置し、反対側では外側に長さｂたけ
はみ出す。このような場合においてはみ出しが起きた部
分かトランジスタのソース・ドレイン領域となる場合に
は、トランジスタの能動領域の幅が狭まるなどの現象が
起きて特性の変化を招いてしまうという問題がある。こ
のため、位置合わせ余裕が必要となるが、十分な位置合
わせ余裕を確保することは寸法の増大を招き、高集積化
の障害となる。FIG. 5(a) shows such an example, in which a silicon nitride film 5 is again formed on the element isolation film 2 which has been thickly formed by selective oxidation. Since this silicon nitride film 5 is unnecessary except on the element isolation film 2, it is necessary to remove it. Therefore, a resist 6 is used to remove unnecessary parts. However, accuracy is a problem with this resist alignment, and if misalignment of the resist occurs as shown in FIG. 5(a), the silicon nitride layer on one side is The end of 5 is located inside by a length a from the end of the element isolation film, and protrudes outside by a length b on the opposite side. In such a case, if the protruding portion becomes the source/drain region of a transistor, there is a problem in that a phenomenon such as narrowing of the width of the active region of the transistor occurs, leading to a change in characteristics. For this reason, a positioning margin is required, but securing a sufficient positioning margin will lead to an increase in size, which will be an obstacle to high integration.
本発明はこのような問題を解決するためになされたもの
で、寸法の増大を招くことなく、しかも後続の工程で膜
厚の減少しない素子分離膜を備えた半導体装置およびそ
の製造方法を提供することを目的とする。The present invention has been made to solve these problems, and provides a semiconductor device equipped with an element isolation film that does not increase in size and whose thickness does not decrease in subsequent steps, and a method for manufacturing the same. The purpose is to
（課題を解決するための手段）
発明にかかる半導体装置によれば、素子分離膜により分
離された複数の素子を形成してなる半導体装置において
、前記素子分離膜がその上に自己整合で堆積された絶縁
性の耐酸化性膜を備えたことを特徴としている。(Means for Solving the Problems) According to a semiconductor device according to the invention, in a semiconductor device formed of a plurality of elements separated by an element isolation film, the element isolation film is deposited thereon in a self-aligned manner. It is characterized by having an insulating, oxidation-resistant film.
絶縁性の耐酸化性膜がシリコン窒化膜であるとよい。It is preferable that the insulating oxidation-resistant film is a silicon nitride film.
また、本発明にかかる半導体装置の製造方法によれば、
半導体基板上にバッファ膜を予定の素子分離膜が前記半
導体基板よりも突出する高さよりも厚く堆積させる工程
と、前記バッファ膜の上に第１の耐酸化性膜を堆積させ
る工程と、前記素子分離膜形成領域の前記バッファ膜お
よび第１の耐酸化性膜を除去して基板表面の露出する開
口を形成する工程と、酸化を行って素子分離膜となる厚
い酸化膜を前記開口部に形成させる工程と、全体に第２
の耐酸化性膜を堆積させ、さらに前記開口を埋める平坦
化材料を堆積させる工程と、前記酸化膜上のみに少なく
とも第２の耐酸化性膜を残存させるようにエッチバック
を行う工程と、残存した前記バッファ膜および前記平坦
化材料を除去する工程とを備えたことを特徴としている
。Further, according to the method for manufacturing a semiconductor device according to the present invention,
a step of depositing a buffer film on a semiconductor substrate to a thickness greater than a height at which a planned device isolation film protrudes beyond the semiconductor substrate; a step of depositing a first oxidation-resistant film on the buffer film; and a step of depositing a first oxidation-resistant film on the buffer film; a step of removing the buffer film and the first oxidation-resistant film in the isolation film formation region to form an opening exposing the surface of the substrate, and performing oxidation to form a thick oxide film that will become an element isolation film in the opening. The second step is to
a step of depositing a planarizing material to fill the opening; a step of etching back so that at least a second oxidation-resistant film remains only on the oxide film; and removing the buffer film and the planarization material.
ここで、第１および第２の耐酸化性膜がシリコン窒化膜
であり、前記バッファ膜がポリシリコン膜であり、前記
平坦化材料がレジストであるとよい。Here, it is preferable that the first and second oxidation-resistant films are silicon nitride films, the buffer film is a polysilicon film, and the planarization material is a resist.
（作 用）
素子分離膜上に自己整合で形成された耐酸化性膜は合わ
せずれがないため、合わせ余裕を必要とすることなく、
後工程における弗酸系のエツチング液を用いた処理等に
よる膜厚の減少から素子分離膜上を確実に保護する。(Function) The oxidation-resistant film formed on the element isolation film in a self-aligned manner has no misalignment, so there is no need for alignment margin.
This reliably protects the element isolation membrane from reduction in film thickness due to treatment using a hydrofluoric acid etching solution in a post-process.
予定の素子分離膜が基板表面から突出する高さ以上の厚
さのバッファ膜をあらかしめ形成しておき、この上に耐
酸化性膜を堆積させた後、選択的に素子分離膜を形成し
、この素子分離膜上にさらに第２の耐酸化性膜を堆積さ
せた後平坦化処理を行いエッチバックによって第２の耐
酸化性膜を残すようにすることにより、この第２の耐酸
化性膜は素子分離膜に対して自己整合されるので、確実
に素子分離膜の保護膜を形成することができる。A buffer film with a thickness greater than the height at which the intended device isolation film protrudes from the substrate surface is formed in advance, an oxidation-resistant film is deposited on top of this, and then the device isolation film is selectively formed. By depositing a second oxidation-resistant film on this element isolation film, performing a planarization process, and leaving the second oxidation-resistant film by etching back, this second oxidation-resistant film can be improved. Since the film is self-aligned to the element isolation film, it is possible to reliably form a protective film for the element isolation film.
（実施例）
以下、図面を参照しながら本発明の実施例につき詳細に
説明する。(Embodiments) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
第１図は本発明にかかる半導体装置における素子分離膜
部分を示す素子断面図である。Ｐ型半導体基板１１の表
面にＬＯＧＯ３法などの公知の方法で形成された素子分
離膜１２の表面には耐酸化性の膜であるシリコン窒化膜
１３が後述するように自己整合方式で形成されている。FIG. 1 is an element cross-sectional view showing an element isolation film portion in a semiconductor device according to the present invention. On the surface of the element isolation film 12 formed on the surface of the P-type semiconductor substrate 11 by a known method such as the LOGO3 method, a silicon nitride film 13, which is an oxidation-resistant film, is formed in a self-aligned manner as described later. There is.
この図に示された実施例においては素子分離膜１２の左
側にはソース・ドレイン領域をなすＮ＋拡散領域１４．
１５がゲート電極下のチャネル領域を挟んで対向してい
る。また、素子分離膜１２の右側にはＮ十拡散領域１７
が形成されている。In the embodiment shown in this figure, on the left side of the element isolation film 12 is an N+ diffusion region 14, which forms a source/drain region.
15 are opposed to each other across the channel region under the gate electrode. Further, on the right side of the element isolation film 12, an N+ diffusion region 17 is provided.
is formed.
第２図は第１図に示された素子分離膜を形成する工程を
示す工程別素子断面図である。まず、Ｐ型半導体基板２
１の表面に５００人の２シリコン酸化を行ない、酸化膜
２８を形成し、その上にポリシリコン膜２２をＣＶＤ法
などによりＴａ−５０００人の厚さで堆積させ、さらに
その上にシリコン窒化膜２３を３０００人の厚さで堆積
させる。写真食刻法を用いて素子分離膜形成領域のポリ
シリコン膜２２および酸化マスクとなるシリコン窒化膜
２３を除去して開口部２４を形成し、基板表面を露出さ
せる。そして酸化雰囲気で酸化を行なうと開口部の基板
表面は酸化され、８０００人の厚い酸化膜２５が形成さ
れる。したかって素子分離膜２５が基板表面から突出す
る高さＴｂ−４０００Ａである（第５図（ａ））ｏなお
、ポリシリコン膜２２は後述するエッチバックを行うた
めに必要な高さを確保するためおよび工程中に発生する
圧力を発散させるためのものである。FIG. 2 is a step-by-step device cross-sectional view showing the step of forming the device isolation film shown in FIG. First, P-type semiconductor substrate 2
2 silicon oxidation is performed on the surface of the silicon oxide film 28 to form an oxide film 28, a polysilicon film 22 is deposited on the surface of the silicon oxide film 22 to a thickness of Ta-5000 by CVD method, and a silicon nitride film is further deposited on top of it. 23 to a thickness of 3000. Using photolithography, the polysilicon film 22 in the element isolation film formation region and the silicon nitride film 23 serving as an oxidation mask are removed to form an opening 24 and expose the substrate surface. When oxidation is performed in an oxidizing atmosphere, the surface of the substrate at the opening is oxidized, and an 8,000 thick oxide film 25 is formed. Therefore, the height at which the element isolation film 25 protrudes from the substrate surface is Tb-4000A (FIG. 5(a)). Note that the polysilicon film 22 must have a height necessary for performing the etchback described later. This is for the purpose of dissipating the pressure generated during the process.
次に全体にシリコン窒化膜２６をＴｃ−５００人の厚さ
で堆積させる。したがって、Ｔａ≧Ｔｂ十Ｔｃの関係が
ある。さらに全体にレジスト２７を塗布する。このレジ
スト２７は段差を埋める平坦化作用を有するのでレジス
トの表面はほぼ平坦面となる（第５図（ｂ））。Next, a silicon nitride film 26 is deposited over the entire surface to a thickness of Tc-500. Therefore, there is a relationship of Ta≧Tb+Tc. Furthermore, a resist 27 is applied to the entire surface. This resist 27 has a flattening effect that fills in the difference in level, so that the surface of the resist becomes a substantially flat surface (FIG. 5(b)).
次にエッチバックを行い、素子分離膜の周囲のシリコン
窒化膜が除去されるまで表面から厚さをほぼ均等に減少
させていくと、Ｔａ≧Ｔｂ十ＴＣの関係があるために素
子分離膜２５上にはシリコン窒化膜の一部２６′と膜厚
の減少したレジスト２７′が積層され、その周囲には膜
厚の減少したポリシリコン２２′が残存した状態が得ら
れる（第２図（Ｃ））。Next, etchback is performed to reduce the thickness almost uniformly from the surface until the silicon nitride film around the element isolation film is removed. A part of the silicon nitride film 26' and a resist 27' with a reduced film thickness are laminated thereon, and a state is obtained in which a polysilicon 22' with a reduced film thickness remains around it (see Fig. 2 (C). )).
このあとドライエツチングにより、ポリシリコン２２′
を除去し、レジスト２７′を除去し、さらに弗酸処理を
行い、酸化膜２８を除去すると、シリコン窒化膜は弗酸
には溶けないため素子分離膜上中央にシリコン窒化膜２
６′がマスクを使用することなく確実に形成される。After this, polysilicon 22' is etched by dry etching.
When the resist 27' is removed, the oxide film 28 is removed by hydrofluoric acid treatment, and the silicon nitride film is not dissolved in hydrofluoric acid, a silicon nitride film 2 is formed in the center on the element isolation film.
6' is reliably formed without using a mask.
したがって、後続の工程における弗酸処理などでも素子
分離膜の膜圧はほとんど減少せず、寄生トランジスタに
おけるＶｔｈの低下などを引き起こすことはない。Therefore, even with hydrofluoric acid treatment in the subsequent process, the film thickness of the element isolation film hardly decreases, and a decrease in Vth in the parasitic transistor does not occur.
以上の実施例においては、耐酸化性膜としてシリコン窒
化膜を用いたが、絶縁性かつ耐酸化性、耐薬品処理性特
に耐弗酸性を有する膜であれば、他の材料でも使用する
ことかできる。また、バッファ膜としては上述の実施例
ではポリシリコンを用いたが、シリコン窒化膜などの耐
酸化性膜に対して十分な選択比を有する材料であれば、
他の材料でも使用することができる。さらに、実施例で
はエッチバックを行うのにレジストを使用しているが、
平坦化作用のある材料、例えば流動性や熱による溶融性
のある材料であれば使用することができる。In the above examples, a silicon nitride film was used as the oxidation-resistant film, but other materials may be used as long as they are insulating, oxidation-resistant, chemical treatment resistant, especially hydrofluoric acid resistant. can. Further, although polysilicon was used as the buffer film in the above embodiment, any material having a sufficient selectivity to an oxidation-resistant film such as a silicon nitride film may be used.
Other materials can also be used. Furthermore, although a resist is used for etchback in the example,
Any material that has a flattening effect, such as a material that is fluid or meltable by heat, can be used.
以上のように本発明にかかる半導体装置によれば、素子
分離膜上に自己整合により形成された耐酸化性膜を有し
ているので、後続の工程において膜圧減少が少なくなく
なり、膜圧減少による特性の変化などを発生しない。As described above, according to the semiconductor device of the present invention, since the oxidation-resistant film is formed on the element isolation film by self-alignment, the film thickness decreases less in subsequent steps, and the film thickness decreases. No change in characteristics occurs due to
また、本発明にかかる半導体装置の製造方法によれば、
マスクを使用することなく自己整合方式で素子分離膜上
の耐酸化性膜を確実に形成することかできる。Further, according to the method for manufacturing a semiconductor device according to the present invention,
It is possible to reliably form an oxidation-resistant film on an element isolation film by a self-alignment method without using a mask.
第１図は本発明にかかる半導体装置の素子分離膜の形状
を示す素子断面図、第２図は本発明にかかる半導体装置
の製造方法を示す工程別素子断面図、第３図は従来の素
子分離膜の膜厚減少の様子を示す素子断面図、第４図は
素子分離膜部分に形成される寄生トランジスタにおける
問題点を示す説明図、第５図は従来とられた膜厚減少対
策の説明図である。
１．１１．２１・・・半導体基板、２．２’、１２２５
・・・素子分離膜、１３．２３．２Ｂ’ 、２６゜２６
′・耐酸化性膜（シリコン窒化膜）、２２゜２２′・・
・バッファ膜（ポリシリコン膜）、２４・・・開口部。
馬１ 図
為３図
（○）
（ｂｌ
Ｐ）４図FIG. 1 is a cross-sectional view of a semiconductor device showing the shape of an isolation film of a semiconductor device according to the present invention, FIG. A cross-sectional view of the device showing how the isolation film thickness decreases, FIG. 4 is an explanatory diagram showing problems with parasitic transistors formed in the isolation film portion, and FIG. 5 is an explanation of conventional measures taken to reduce the film thickness. It is a diagram. 1.11.21...Semiconductor substrate, 2.2', 1225
...Element isolation film, 13.23.2B', 26°26
'・Oxidation-resistant film (silicon nitride film), 22°22'...
- Buffer film (polysilicon film), 24... opening. Horse 1 Figure 3 (○) (bl P) 4 Figure
Claims (1)
なる半導体装置において、前記素子分離膜がその上に自
己整合で堆積された絶縁性の耐酸化性膜を備えたことを
特徴とする半導体装置。 ２、絶縁性の耐酸化性膜がシリコン窒化膜であることを
特徴とする請求項１記載の半導体装置。 ３、半導体装置の製造方法において、 半導体基板上にバッファ膜を予定の素子分離膜が前記半
導体基板よりも突出する高さよりも厚く堆積させる工程
と、 前記バッファ膜の上に第１の耐酸化性膜を堆積させる工
程と、 前記素子分離膜形成領域の前記バッファ膜および第１の
耐酸化性膜を除去して基板表面の露出する開口を形成す
る工程と、 酸化を行って素子分離膜となる厚い酸化膜を前記開口部
に形成させる工程と、 全体に第２の耐酸化性膜を堆積させ、さらに前記開口を
埋める平坦化材料を堆積させる工程と、前記酸化膜上の
みに少なくとも第２の耐酸化性膜を残存させるようにエ
ッチバックを行う工程と、残存した前記バッファ膜およ
び前記平坦化材料を除去する工程とを備えたことを特徴
とする半導体装置の製造方法。 ４、前記第１および第２の耐酸化性膜がシリコン窒化膜
であり、前記バッファ膜がポリシリコン膜であり、前記
平坦化材料がレジストであることを特徴とする請求項３
記載の半導体装置の製造方法。[Scope of Claims] 1. A semiconductor device comprising a plurality of elements separated by an element isolation film, wherein the element isolation film includes an insulating oxidation-resistant film deposited thereon in a self-aligned manner. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein the insulating oxidation-resistant film is a silicon nitride film. 3. A method for manufacturing a semiconductor device, comprising: depositing a buffer film on a semiconductor substrate to a thickness greater than a height at which a planned element isolation film protrudes from the semiconductor substrate; and depositing a first oxidation-resistant film on the buffer film. a step of depositing a film; a step of removing the buffer film and the first oxidation-resistant film in the element isolation film formation region to form an opening exposing the substrate surface; and performing oxidation to become an element isolation film. forming a thick oxide film in the opening; depositing a second oxidation-resistant film over the entire surface and depositing a planarizing material to fill the opening; and depositing at least a second oxidation film only on the oxide film. 1. A method for manufacturing a semiconductor device, comprising the steps of etching back so as to leave an oxidation-resistant film remaining, and removing the remaining buffer film and planarization material. 4. Claim 3, wherein the first and second oxidation-resistant films are silicon nitride films, the buffer film is a polysilicon film, and the planarization material is a resist.
A method of manufacturing the semiconductor device described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6566890A JPH03266435A (en) | 1990-03-16 | 1990-03-16 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6566890A JPH03266435A (en) | 1990-03-16 | 1990-03-16 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03266435A true JPH03266435A (en) | 1991-11-27 |
Family
ID=13293609
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6566890A Pending JPH03266435A (en) | 1990-03-16 | 1990-03-16 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03266435A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08203886A (en) * | 1995-01-11 | 1996-08-09 | Lg Semicon Co Ltd | Method of isolating semiconductor element |
| US5567645A (en) * | 1993-04-24 | 1996-10-22 | Samsung Electronics Co., Ltd. | Device isolation method in integrated circuits |
| US5756390A (en) * | 1996-02-27 | 1998-05-26 | Micron Technology, Inc. | Modified LOCOS process for sub-half-micron technology |
| US6387777B1 (en) | 1998-09-02 | 2002-05-14 | Kelly T. Hurley | Variable temperature LOCOS process |
-
1990
- 1990-03-16 JP JP6566890A patent/JPH03266435A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5567645A (en) * | 1993-04-24 | 1996-10-22 | Samsung Electronics Co., Ltd. | Device isolation method in integrated circuits |
| JPH08203886A (en) * | 1995-01-11 | 1996-08-09 | Lg Semicon Co Ltd | Method of isolating semiconductor element |
| US5573974A (en) * | 1995-01-11 | 1996-11-12 | Lg Semicon Co., Ltd. | Method for isolating semiconductor elements |
| US5756390A (en) * | 1996-02-27 | 1998-05-26 | Micron Technology, Inc. | Modified LOCOS process for sub-half-micron technology |
| US6387777B1 (en) | 1998-09-02 | 2002-05-14 | Kelly T. Hurley | Variable temperature LOCOS process |
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