JPH11163281A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable mounting a highly integrated memory device and a high- performance logic device on one chip, by stacking a first insulating film only on a part of gate electrode of a transistor of the memory device, and depositing a second insulating film of type different from the first insulating film on the memory device and the logic device. SOLUTION: A P well and an N well 3 are formed on a silicon substrate 1 and then a device separating area 4 is formed. After that, a gate oxide film 5 is formed by thermal oxidation. Consecutively, polysilicon 6 is deposited. An oxide film 7 is formed on the polysilicon 6. SiN 8 as first insulating film is deposited on the oxide film 7. A mask is deposited on SiN 8. The polysilicon 6, the oxide film 7 and the SiN 8 film are etched to form a gate electrode. An SiO<2> film 19 as second insulating film which is different from the SiN film 8 of the gate electrode is deposited by CVD method. The SiO2 film 19 is etched and the resist is delaminated to form an Al wiring 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device in which a memory device such as a DRAM and a logic device are mixedly mounted on one chip.

[0002]

2. Description of the Related Art Conventionally, in a memory device manufacturing process, a SAC (Self-Alignment) is applied to a bit line contact or the like in order to reduce a cell area and a chip size.
ed-Contact) technology.

Hereinafter, a method using the SAC technique will be described with reference to FIG. In this method, a structure in which the upper surface and the side wall of the gate 101 are covered with the insulating film 102 such as a silicon nitride film is realized. After depositing an interlayer insulating film 103 of SiO ₂ or the like, a contact hole is formed by further etching the insulating film 103 under conditions that can maintain a selectivity with respect to the insulating film 102.

As a result, even if the contact hole is shifted toward the gate electrode due to misalignment in the lithography process, the insulating film 102 itself is not etched, so that a short circuit between the contact and the gate can be avoided.

On the other hand, for example, a DRAM (Dynamic RAM)
As shown in FIG. 4, the basic circuit of the memory cell includes a switching MOS transistor Tr and a memory capacitor C, and determines 1 or 0 based on whether or not the memory capacitor C has a charge. If the word line WL is set to a high voltage and the MOS transistor Tr is turned on, the electric charge stored in the memory capacitor C is detected on the bit line BL, and reading is performed. As described above, since the gate potential of the MOS transistor Tr serving as a transfer gate for controlling the reading and writing of charges is used after being boosted to a voltage higher than the power supply voltage, it is necessary to provide a thicker gate oxide film. .

[0006]

However, when the above-described SAC technology is used from the viewpoint of cell size reduction, the following will be described when manufacturing an LSI in which a memory and a logic device are mounted on one chip. Problems had arisen.

Generally, a logic device employs a technique called “salicide” in order to increase the speed of a transistor. In this salicide technique, an insulating film 1 such as a SiN film is formed only on a side wall of polysilicon 111 serving as a gate electrode.
12 is formed, and the polysilicon is exposed on the upper surface of the gate electrode. After that, a metal 113 such as Ti is deposited and then annealed to obtain a metal silicide (metastable) 114 as a source.
The insulating film 1 is selectively formed only on the drain and the gate electrode.
Excess metal on 12 is stripped by a chemical solution to form silicide (low resistance) 115, thereby reducing the resistance of the source / drain and gate to form a high performance transistor (see FIG. 5).

However, when the salicide technique is used, the SAC technique that requires an insulating film to be formed on the gate electrode in advance cannot be adopted. In such cases,
This is because it is difficult to form a metal silicide layer on the gate electrode in a self-aligned manner. Therefore, in this case, it becomes difficult to mount a high-performance logic circuit using a highly integrated memory and high-performance transistors on the same chip.

On the other hand, apart from the problem of the SAC technique, D
When a RAM and a high-performance logic device are mounted on one chip, the following problems have occurred. That is, in the DRAM, as described above, the gate oxide film is provided thick. Therefore, when manufacturing an LSI in which the DRAM and the logic device are mounted on the same chip in the process of manufacturing the DRAM, the thickness is larger than the gate oxide film normally used in the logic device. There is a problem that the performance is lower than that of a transistor created in a logic device manufacturing process.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to make it possible to simultaneously employ a SAC technique strongly demanded by a memory and a salicide technique strongly demanded by a logic. Another object of the present invention is to provide a method of manufacturing a semiconductor device in which a highly integrated memory device and a high-performance logic device are mixedly mounted on one chip without deteriorating both features. More specifically, DRAM
Was a problem when mixed with logic devices
The difference in the gate oxide film is also solved at the same time.

[0011]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which a memory device and a logic device are mounted on a single chip. Laminating a first insulating film only on at least a part of the gate electrode; and depositing a second insulating film different from the first insulating film on the memory device and the logic device. Features.

[0012] In the first embodiment, further,
The impurity concentration in the polysilicon of at least the gate electrode of the transfer gate of the memory device is made lower than the impurity concentration of the polysilicon in the gate electrode into which other same-type impurities are introduced, and the transfer gate is formed by the low concentration. By depletion, the effective thickness of the gate electrode of the transfer gate is made larger than that of other transistors.

Further, a second aspect is a method of manufacturing a semiconductor device in which a memory device and a logic device are mixedly mounted on one chip, a step of forming a gate oxide film, and forming a polysilicon as a gate electrode on the gate oxide film. Laminating, laminating SiN on the polysilicon, lithography and etching, forming a plurality of regions where the remaining film of SiN is different, and forming the transistors of the memory device and the logic device. Implanting arsenic at a predetermined dose into the entire region to be formed.

According to a third aspect, in a method of manufacturing a semiconductor device in which a memory device and a logic device are mixed on one chip, a step of forming a gate oxide film and a step of laminating polysilicon on the gate oxide film Laminating tungsten silicide on the polysilicon, forming a first region from which the tungsten silicide has been removed and a second region remaining through the lithography and etching steps, Implanting arsenic ions at a predetermined dose into the entire region where the transistor of the logic device is formed, and forming a plurality of insulating film regions having different thicknesses by changing the material of the gate electrode. It is characterized by.

According to the above-described first to fourth aspects, the following operations are provided. That is, according to the first aspect of the present invention,
By performing the salicide process after forming the insulating film only on the gate electrode of the transistor that is to be the transfer gate of the memory device, both SAC and salicide are achieved.

Further, according to the first aspect, when DRAM and logic are mixed among the memories, the impurity concentration of only the word line of the DRAM is reduced when doping the gate electrode, thereby depleting the gate electrode. By applying the oxidation phenomenon, the effective oxide film is increased only in the word line.

According to the second aspect, the insulating film is left on all the gate electrodes, but the film thickness is changed according to the region, so that the gates which are different in the same semiconductor device are effectively different. An insulating film is formed. According to the third aspect, by changing the material of the gate electrode, a plurality of effectively different gate insulating films are formed in different regions of the same semiconductor device.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS. 1 and 2,
A method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. First, after a P well 2 and an N well 3 are formed on a silicon substrate 1, a LOCOS (Local Oxidation Si
The element isolation region 4 is formed by the licon method. afterwards,
A 6 nm gate oxide film 5 is formed by thermal oxidation, and then a polysilicon 6 is deposited to a thickness of 300 nm. Thereafter, an oxide film 7 of 10 nm is formed on the polysilicon 6 by a thermal oxidation method, and SiN 8 is formed on the oxide film 7 by CVD (Chemical).
200 nm is deposited by a vapor deposition method. Then, through a known photolithography process, the SiN8
A mask 9 is deposited thereon, and the polysilicon 6, oxide film 7, and SiN 8 are etched by RIE (Reactive Ion Etching) (see FIG. 1A).

After forming the gate electrode in this manner, the LD
Medium concentration source / drain regions 10 and 11 for realizing a D transistor structure are formed. For this reason, in the present embodiment, As is applied at 50 keV for 7E only in the nMOS region.
A dose of 13cm ^-2, and ion-implanted at a dose of 5E13 cm ^-2 at 40keV a BF2 + only pMOS portion, 900 ° C. in the lamp annealing is set to be performed for 10 seconds activation annealing (Fig. 1 (b )reference).

Subsequently, by a photolithography process,
Only the gate electrode 16 of the transistor to be the transfer gate of the memory cell is covered with a resist,
The gate electrodes 17 and 18 of the normal transistor
N8 and the underlying oxide film 7 are formed by a known CDE (Chemical
Dry etching) and chemical etching. Thereafter, SiN is deposited to a thickness of 50 nm, and the whole is etched back by RIE, thereby forming a sidewall 12 of SiN at each gate electrode. At this time, the SiN film 8 remains on the gate electrode of the transfer gate transistor of the memory cell, and the entire gate electrode is covered with SiN (FIG. 1).
(C)).

Next, only nMOS is doped with phosphorus ions at 40 k.
A dose of 7E15 cm ^-2 is ion-implanted with eV, and pM
Only OS is implanted with BF2 ions at 40 keV and at a dose of 5E15 cm ^-2 , and the nMOS source / drain region 14a and gate electrode 14b and the pMOS source / drain region 13b and gate electrode 13a are respectively n +
Doping into p-type and 10% by lamp annealing
Activation is performed by annealing at 00 ° C. for 10 seconds. Then, T
i is sputtered for 30 nm, and 750 is formed by a lamp annealing method.
After annealing at 30 ° C. for 30 seconds to allow Ti and Si to react with each other, T
i is removed by a mixed solution of sulfuric acid and hydrogen peroxide solution. Subsequently, the source / drain 14a and the gate electrode 14
To lower the resistance of the Ti silicide formed on it,
Perform lamp annealing at 850 ° C. for 30 seconds. Thus, the entire transistor is formed (FIG. 2A).

Thereafter, if the memory section is, for example, a DRAM, a step of forming a stacked capacitor by a known method is performed, and then a full CMOS type SRA is formed.
In the case of an M cell, SiO ₂ 19 which immediately becomes an interlayer insulating film
Is deposited by a CVD method, and then a contact hole is formed by a lithography process using a resist pattern.
The SiO ₂ 19 is etched with take conditions of SiN and selection ratio, the resist is removed. Thereafter, an Al wiring 20 is formed to realize a semiconductor device in which a logic circuit formed of a highly integrated memory and a high-performance transistor is mounted on one chip (see FIG. 2B).

The S deposited on the gate electrode
Depending on the combination of the iN8 film thickness and the n + ion implantation conditions for doping the source / drain and the gate electrode (for example, SiN film thickness 15 nm, n + ion implantation,
As + ion implantation, 60 keV dose 7E15 cm ^-2
), The impurity concentration is reduced only in the gate electrode of the transfer gate transistor in which n + ions are implanted through SiN8, and the effective gate oxide film thickness can be increased by the gate depletion phenomenon.

Thus, in a DRAM in which only the oxide film of the transfer gate is applied with a high voltage, the physical oxide film thickness is 6 nm, which is a small value required for a high performance logic device, but only the transfer gate is 8 nm electrically. The gate oxide film thickness required for each of the high-performance logic transistor and the DRAM, such as working as a semiconductor device, can be mixedly mounted on one chip while being realized by a simple process.

Further, in the above-described embodiment, a method has been described in which only the gate electrode of the memory portion is made of polysilicon. However, even if this is a polycide structure having a two-layer structure of WSi / polysilicon, for example. Needless to say, a similar effect can be realized by a manufacturing method that can be easily analogized. That is, after exposing the gate electrodes other than the transfer gate in the memory section, removing the SiN 8 and the oxide film 7 thereon, the WSi on the polysilicon may be further removed.

As described above, a method of manufacturing a semiconductor device in which a plurality of effective gate insulating films can be set depending on whether or not an insulating film (in this case, an SiN film) is left on the gate electrode, and particularly a dynamic RAM and a logic circuit thereof LSI mixed with
Examples of application to

The effect of realizing different gate insulating films in different regions of the same semiconductor device is to leave the insulating films on all the gate electrodes, but to change the thickness according to the regions. Can also be obtained by
That is, after a 6-nm gate oxide film is formed, 250-nm polysilicon is deposited as a gate electrode,
After the lithography process and the etching process, the remaining film of
A region II of 50 nm and a region III of 0 nm are formed. Then, arsenic is applied for 50 k over the entire region for forming the nMOSFET.
Ion implantation is performed at a dose of eV, 5E15 cm ^-2 .
In this way, the effective oxide film region III close to 6 nm, the region I close to 8 nm, and 7 in between.
A region II close to nm can be formed.

The same effect can be obtained by changing the material of the gate electrode. That is, 6 nm
After forming a gate oxide film of
Deposited by the mLP-CVD method, and tungsten silicide is further deposited by a 200 nm sputtering method. afterwards,
Through lithography and etching steps, a region I where tungsten silicide is removed and a region II where the tungsten silicide is left are formed. Thereafter, arsenic ions are implanted into the entire region where the nMOSFET is to be formed at 50 keV and at a dose of 5E15 cm ⁻² . According to this, the region I of the effective oxide film close to 6 nm and the region II close to 8 nm can be electrically formed.

[0029]

As described in detail above, according to the present invention,
It is possible to simultaneously employ the SAC technology, which has a strong demand from the memory device, and the salicide technology, which has a strong demand from the logic device, so that highly integrated memory devices and high-performance logic devices can be used without impairing the characteristics of both.
It is possible to provide a method of manufacturing a semiconductor device which can be mounted on one chip.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a view illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention;

FIG. 3 is a diagram showing a configuration of a semiconductor device according to a conventional technique.

FIG. 4 is a diagram showing a basic configuration of a memory cell of a DRAM according to a conventional technique.

FIG. 5 is a view for explaining a general salicide process.

[Description of Signs] 1 silicon substrate 2 P well 3 N well 4 element isolation region 5 gate oxide film 6 polysilicon 7 oxide film 8 SiN 9 mask 10 source / drain region (nMOS) 11 source / drain region (pMOS) 12 side Wall 13a Source / drain region (nMOS) 13b Gate electrode 14a Gate electrode 14b Source / drain region (pMOS) 15 TiSiO ₂ 16 Gate electrode 17 Gate electrode 18 Gate electrode 19 SiO ₂ 20 Al wiring

Claims (5)

[Claims] 1. A memory device and a logic device,
In a method of manufacturing a semiconductor device mixedly mounted on a chip, a step of laminating a first insulating film on at least a part of a gate electrode of a transistor of the memory device; and a second insulating layer different in type from the first insulating film. Depositing a film on the memory device and the logic device;
A method for manufacturing a semiconductor device, comprising: 2. The transistor according to claim 1, wherein the first insulating film is SiN, the second insulating film is SiO ₂ , and the transistor in which the first insulating film is stacked on a gate electrode is a transfer gate of a memory device. The semiconductor device according to claim 1, wherein: 3. An impurity concentration in at least a polysilicon of a gate electrode of a transfer gate of the memory device is lower than an impurity concentration of polysilicon in a gate electrode into which another same-type impurity is introduced. 2. The method according to claim 1, wherein the transfer gate is depleted so that the effective thickness of the gate electrode of the transfer gate is larger than that of another transistor. 4. A memory device and a logic device,
A method of manufacturing a semiconductor device to be mounted on a chip, a step of forming a gate oxide film, a step of stacking polysilicon as a gate electrode on the gate oxide film, a step of stacking SiN on the polysilicon, and lithography. Through the process and the etching process, the above SiN
Forming a plurality of regions having different residual films, and implanting arsenic with a predetermined dose into the entire region where transistors of the memory device and the logic device are to be formed. Device manufacturing method. 5. A memory device and a logic device,
In a method of manufacturing a semiconductor device to be mounted on a chip, a step of forming a gate oxide film, a step of stacking polysilicon on the gate oxide film, a step of stacking tungsten silicide on the polysilicon, lithography and etching Forming a first region from which the tungsten silicide has been removed and a second region left by removing the tungsten silicide; and arsenic ions at a predetermined dose over the entire region where transistors of the memory device and the logic device are to be formed. Forming a plurality of insulating film regions having different thicknesses by changing the material of the gate electrode.