416135 Λ7 -^_____H7 五、發明説明（1 ) ' 〜 '~ 發明所屬之技術領域 本發明係關於非依電性半導體元件及其製造方法者， 詳言之’關於實現内設有快閃記憶體之複合晶片時，不管 電壓及溫度之變化如何，皆可形成具有穩定特性之電阻及 電容器的非依電性半導體元^件及其製造方法。 習知技術 最近’隨著半導體之製造技術及使用半導體之電子製 品的應用領域益行擴大，而將多種多樣之單一元件實現於 一個晶片内以進行各種機能之複合半導體晶片的必需性正 在增大》 如此，將記憶體晶片之機能及微控器或按照應用目的 而進行特定機能的控制機能，實現於一個半導體晶片内時 ’在半導體晶片之生產成本之節省及體積縮小之同時，可 謀使用此等之應用成品之製造成本之節減及性能之提高， 因而現在’對此之研究開發漸漸地一般化。 經濟部中央標隼局員工消費合作社印製 為了將此種複合性之機能實現於一個晶片内，在元件 之製造時，不只是對於存儲單元，電晶體，二極管等之有 源元件，且對於電阻及電容器之無源元件之製造技術也很 重要。 這是因為，在實現ADC(Analog to Digital Converter) ’比較器或運算放大器等之類比電路之實現時，雖要求非 常精密之電壓值及電流值之控制，但若與精密之電壓值及 電流值之供應直接關聯之電阻體及電容器，具有對於輸入 電壓或外部溫度敏感之特性的話，無法做出精密製品的設 4 n n U - n n n - , * n ^ln n n I T (請先閱讀背面之一iJ,-意事項再填轉本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 經濟部中央標準局員工消費合作社印製 Λ7 Η 7五、發明説明（2 ) ' 計之故。 因此，製造不管外部溫度及輸入電壓如何均具有穩定 特性之電阻及電容器之技術，被認為在複合半導體晶片之 實現上不可或缺的重要技術。 在這種理由下，在複合|晶片之非依電性存儲單元之製 造時通常未體現如電阻及電容器一般之單一元件。然而， 在未艘現如電阻及電容器一·'般之單一元件下製造複合晶片 時，快閃存儲單元之動作特性卻不如非那樣之情況，而產 生無法高速度動作之缺點。 為了改善該缺點，最近提案了一種將一使用有在半導 體直接電路頻繁地使用之高濃度雜質領域（例如n-或〆之活 性領域）的電阻體及一在MOS製造時使用之MIM構造（例如 ’堆疊型、構渠型及圓筒型等）之電容器，直接適用於内 設有快閃記憶體之複合半導體晶片製造之技術。（註： MlK^=metal /inter layer/metal) 發明欲解決之課題 然而’若像這樣將一在半導體直.接電路頻繁地使用之 電阻體及一電容器’直接適用於内設有快閃記憶體之複合 晶片時’電阻形成時之工程變數則變大而使存儲單元之電 阻值變成不均等，以致電阻體及電容器具有對於輸入電壓 及外部溫度變化敏感之特性，因此存在著精密之半導體製 品之設計變成$難，導致非依電性半導體元件之全體動作 特性降低等之‘點。 本發明之目的係在於提供—種非依電性半導體元件及 本紙張尺度4财關家辦( 2^^^--— - - -----Κ--· ά------IT-------冰 (請先閲請背面之u意事項再填寫本頁) 416135 Λ7 Η 7 五、發明説明（3) 其製造方法，以便在内設有快閃記憶體之複合晶片之實現 時，與非依電性存儲單元一同形成具有穩定之電阻值及靜 電電容之電阻及電容器，藉此使半導體元件之全體動作特 性提高。 用以解決課題之手段.丨 為了達成前述目的之本發明第一、第二實施例為一種 非依電性半導體元件，其包含有： 半導體基板，係定義有存儲單元形成部及周邊電路部 t 非依電性記憶電晶體，係形成在前述基板上之存儲單 元形成部，且具有透過隔離絕緣膜及隧道絕緣膜層合一用 來存儲電子之漂浮閘及一用來調節此漂浮閘之控制閘之構 造； 電阻線，係形成在前述基板上之周邊電路部規定部分 ’且具有與前述漂洋間相同之材質；及 電谷器，係形成在前述基板上之周邊電路部規定部分 以便與前述電阻線隔離一規定間隔，且透過介電膜層合一 與前述漂浮閘相同材質之第一電極端子及一與前述控制閘 相同材質之第二電極端子。 此時，前述介電膜，係由0N0構造之絕緣膜及氧化 膜材質之絕緣膜所構成。 又，為達成前述目的之第一實施例的非依電性半導體 元件之製造方法，包含有： 第一導電性臈及氧化防止膜形成工程’係在定義有存 本紙張尺度適用中國國家標準（CNS ) A4規格（210x 297公楚） I ； i iT-^ (請先閲讀背面之 k意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 6 --dums_b：__ 五、發明説明（4 ) 儲單元形成部及周邊電路部之半導體基板上，依次形成第 一導電性膜及氧化防止膜； 姓刻工程’係將氧化防止骐加以姑刻以便前述存儲單 元形成部之第一導電性膜表面露出一規定部分； 去除工程’係將前述氧化防止膜當做掩膜，藉由氧化 工程將隔離絕緣部形成於存儲單元形成部後去除前述氧化 防止膜； 介電膜形成工程’係在包含前述隔離絕緣膜之前述第 一導電性膜上，形成介電膜； 感光膜圖案形成工程，係在前述介電膜上之周邊電路 部形成用來界定電阻形成部及電容器形成部之感光膜圖索 * 介電膜食刻工程，係將前述感光膜圖案作為掩模蝕刻 介電膜； 感光膜圖案去除工程’係將前述感光膜圖案及前述隔 離絕緣膜作為掩模，餘刻前述第一導電性膜以同時形成一 漂浮閘’ 一在上侧部形成有前述介電膜之電阻線及一第一 電極端子，然後去除前述感光臈囷案； 經濟部中央標隼局員工消资合作社印製 (請先閲讀背面之注意事項再填寫本頁〕 j·Μ. 第二導電性膜形成工程，係在包含前述隔離絕緣膜之 兩邊緣部及前述漂浮閘之側壁的前述基板上之一規定部分 。前述電阻線之侧壁及前述第一電極端子之側壁，形成絕 緣膜，且在其結果物全面形成第二導電性膜； 感光膜圊案形成工程’係在前述第二導電性膜上之存 儲單元形成部及周邊電路部規定部分，形成用來界定電極 — __ 本紙張國國家標準（CNS > A4規格（210X297公潑)Γ-- Λ7 B7 416135 五、發明説明（5 ) 形成部及電容器形成部之感光膜圖案；及 感光膜圖案去除工程，係將前述感光膜圖案作為掩模 ，蝕刻前述第二導電性膜以同時形成控制閘及第二電極端 子後，去除前述感光膜圊案》 又’為達成前述目的$第二賁施例的非依電性半導體 元件之製造方法，包含有： 第一導電性膜及氧化防止膜形成工程，係在定義有存 儲單元形成部及周邊電路部之半導體基板上，依次形成第 一導電性膜及氧化防止膜； 触刻工程，係將氧化防止膜加以蝕刻以便前述存儲單 元形成部之第一導電性膜表面露出一規部分； 去除工程’係將前述氧化防止膜當做掩膜，藉由氧化 工程將隔離絕緣膜形成於存儲單元形成部後，去除前述氧 化防止膜； 感光膜圖案形成工程’係在前述第一導電性臈上之周 邊電路部形成用來界定電阻形成部及電容器形成部之感光 膜圖案； 感光膜圖案去除工程，係將前述感光骐圖案及前述隔 離絕緣膜當做掩模，蝕刻前述第一導電性膜以同時形率漂 浮閘，電阻線及第一電極端子後，去除前述感光膜圖案； 第一導電性膜形成工程，係在包含前述隔離絕緣膜之 兩邊緣部及前述漂浮閘之侧壁的前述基板上之一規定部分 前述電阻線之全表面及前述第一電極端子之全表面，形 成絕緣膜，在那些結果物全面形成第二導電性膜： (2!0X297公楚） I t— n I. - ---I ^ ti f — n I___丁 - U3. 言 (請先聞讀背面之注項再填寫本頁} 經濟部中央標準局負工消費合作社印製 Λ7 Η 7 _ 416135 ----—-_ 五、發明説明（6 ) 感光膜圊案形成工程’係在前述第二導電性膜上之存 儲單元形成部及周邊電路部規定部分，形成用來界定電極 形成部及電容器形成部之感光膜圖案；及 感光膜圊案去除工程，係將前述感光膜圖案作為掩模 ，名虫刻前述第二導電性膜以丨同時形成控制閘及第二電極端 子後，去除前述感光膜圖案。 當製造一具有如前述構造之非依電性半導體元件時， 由於減少電阻及電容器之形成時之工程變數，而可防止因 外部溫度及輸入電壓之變化而降低特性之情事。 發明之實施形態 以下，說明本發明之實施形態。 本發明’係將不管外部溫度及輸入電壓之變化如何均 具有穩定之電阻值及靜電電容之電阻及電容器，在複合晶 片内之非依電性存儲單元之製造時一同形成，藉此可達成 精密製品之設計的技術者。 此時，為驅動内設有非依電性記憶體之晶片而必需要 的電阻’係藉用來製作非依電性存儲.單元之漂浮閘的聚梦 酮來實現’而電容器則藉著將前述存儲單元之漂浮閑用聚 矽酮及控制閘用聚矽酮用做兩電極端子，並在其間放置由 另一途徑所形成之介電膜（例如ΟΝΟ構造之絕緣膜及氛化 膜材質之絕緣膜）來實現者。 就此，參照第1圓乃至第18圖來具體說明之。在此， 第1圖乃至第11圖係顯示依據本發明第一實施例之非依電 性半導體元件的製造方法之工程順序圖；第12圊乃至第18 本紙張尺度適用中固國家標準（CNS ) A4現格（210X297公栽） n -.- I J 1 11 (請先閱讀背面.之yi意事項再填寫本頁) 經濟部中央標隼局員工消費合作社印架 9 416135 ^ 一-‘. _ 五、發明説明（7 ) 圖係顯示本發明第二實施例之非依電性半導體元件之製造 方法的工程順序圖。前述圖中，用符號a表示之部分係表 示前述元件之非依電性存儲單元的形成部；用符號b表示 之部分係表示前述元件之電阻形成部；用符號(；表示之部 分係表示前述元件之電容器丨形成部。 首先’說明第一實施例’在此，為了方便而將前述工 程區分為十一階段來說明。 第一階段為；如第1圖所示，於半導體基板100上之規 定部分形成場氧化膜102以定義周邊電路部分（電阻形成部 (b)及電容器形成部（c))之後’僅在基板1〇〇上之存儲單元 選擇性地形成閘絕緣膜104’》 第二階段為：如第2圖所示’於前述閘絕緣膜1〇4及場 氧化膜102上依次形成聚石夕鋼材質之第一導電性膜及氮 化膜材質之氧化防止膜108。此時，前述第一導電性媒ι〇6 係形成1000〜2000A之厚度。 第二階段為.如第、圖所示’為了存儲單元形成部之 3 經濟部中央標準局員工消費合作社印製 氧化防止膜108表面露出一特定部而將之選擇蝕刻以形成 感光膜圖案】10之後，將之當做掩模乾蚀刻氧化防止膜丨08 。此時電阻形成部b及電容器形成部c之氧化防止膜1 〇8則 由於被感光膜圖案110所保護而未被蝕刻。 第四階段為：如第4圖所示’未除感光膜圖案uo，然 後將氧化防止膜108作為掩模施行氧化工程，其結果，僅 在未被氧化防止膜10 8所保護之部分選擇性地形成隔離絕 緣膜112 » 10 (請先閱讀背面之;i意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公楚）416135 Λ7-^ _____ H7 V. Description of the invention (1) '~' ~ Technical field to which the invention belongs The present invention relates to non-electrical semiconductor devices and methods for manufacturing the same, in particular, 'about the realization of a flash memory in the device In the case of a composite wafer, regardless of changes in voltage and temperature, a non-electrical-resistant semiconductor element having a stable characteristic of a resistor and a capacitor can be formed and a manufacturing method thereof. Recently, as the manufacturing technology of semiconductors and the application fields of electronic products using semiconductors have expanded, the need for compound semiconductor wafers that implement a wide variety of single components in one wafer to perform various functions is increasing. 》 In this way, the function of the memory chip and the micro-controller or the control function of the specific function according to the application purpose can be realized in a semiconductor wafer while saving the production cost of the semiconductor wafer and reducing the volume, and can be used. The reduction of manufacturing cost and the improvement of performance of these application finished products, so now the research and development of this are gradually generalized. Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs in order to realize such a composite function in one chip, when manufacturing components, not only for active components such as memory cells, transistors, diodes, etc., but also for resistors And the manufacturing technology of capacitor passive components is also important. This is because, when implementing analog circuits such as ADC (Analog to Digital Converter) 'comparators or operational amplifiers, although very precise control of voltage and current values is required, The resistors and capacitors directly related to the supply are sensitive to the input voltage or external temperature. It is impossible to make precision products. 4 nn U-nnn-, * n ^ ln nn IT (Please read iJ on the back first) (-) Please fill in this page and reprint this page) This paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Λ7 Η 7 Fifth, the invention description (2) For reasons. Therefore, the technology for manufacturing resistors and capacitors that have stable characteristics regardless of external temperature and input voltage is considered to be an important technology indispensable for the realization of composite semiconductor wafers. For this reason, non-electrical memory cells of composite | wafers are often not manufactured with single components like resistors and capacitors. However, when a composite wafer is manufactured under a single element such as a resistor and a capacitor, the operation characteristics of the flash memory cell are not as good as those in other cases, and a disadvantage that high-speed operation cannot be caused. In order to improve this disadvantage, a resistor body using a high-concentration impurity field frequently used in a semiconductor direct circuit (such as an active field of n- or europium) and a MIM structure (such as 'Stacked, channeled, cylindrical, etc.) capacitors are directly applicable to the technology for manufacturing composite semiconductor wafers with flash memory. (Note: MlK ^ = metal / inter layer / metal) The problem to be solved by the invention, however, 'If a resistor and a capacitor that are frequently used in a semiconductor directly connected circuit like this' are directly applicable to a flash memory. In the case of composite wafers, the engineering variables at the time of resistance formation become larger and the resistance values of the memory cells become unequal, so that resistors and capacitors are sensitive to input voltage and external temperature changes, so there are precision semiconductor products. The design becomes difficult, which leads to a reduction in the overall operating characteristics of the non-electronic semiconductor device. The purpose of the present invention is to provide a kind of non-electrically-conducting semiconductor device and the paper size home office (2 ^^^ ---------- Κ-- · ά ------ IT ------- Ice (please read the intentions on the back, and then fill out this page) 416135 Λ7 Η 7 V. Description of the invention (3) Its manufacturing method, so that it is equipped with flash memory. When the chip is realized, a resistance and a capacitor having a stable resistance value and an electrostatic capacitance are formed together with the non-electrostatic memory cell, thereby improving the overall operating characteristics of the semiconductor element. Means to solve the problem. In order to achieve the aforementioned purpose The first and second embodiments of the present invention are a non-independent semiconductor element, which includes: a semiconductor substrate, which defines a memory cell forming portion and a peripheral circuit portion. A non-independent memory transistor is formed in the foregoing. The storage unit forming part on the substrate has a structure for laminating a floating gate for storing electrons and a control gate for adjusting the floating gate through an isolation insulating film and a tunnel insulating film; a resistance line is formed on the aforementioned substrate On the peripheral circuit section prescribed part ' It has the same material as the aforementioned floating ocean; and an electric valley device, which is formed on a prescribed portion of the peripheral circuit portion on the aforementioned substrate so as to be isolated from the aforementioned resistance wire by a prescribed interval, and is laminated with a dielectric film to be the same material as the aforementioned floating gate The first electrode terminal and a second electrode terminal made of the same material as the control gate. At this time, the dielectric film is composed of an insulating film made of 0N0 and an insulating film made of an oxide film. In addition, in order to achieve the foregoing purpose The method for manufacturing a non-electrical semiconductor device according to the first embodiment includes the following steps: The first conductive plutonium and oxidation prevention film formation process is defined in the paper size of the paper to which the Chinese National Standard (CNS) A4 specification (210x 297 Gongchu) I; i iT- ^ (Please read the k-notes on the back before filling this page) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 6 --dums_b: __ V. Description of the invention (4) Storage unit formation The first conductive film and the oxidation prevention film are sequentially formed on the semiconductor substrate of the peripheral circuit portion and the peripheral circuit portion. A predetermined portion is exposed on the surface of the first conductive film of the forming portion; the removal process is to use the foregoing oxidation prevention film as a mask, and then remove the foregoing oxidation prevention film by forming an isolation insulating portion on the memory cell formation portion by the oxidation process; The film forming process is to form a dielectric film on the aforementioned first conductive film including the aforementioned isolation insulating film; the pattern forming process of the photosensitive film is to form a peripheral circuit portion on the aforementioned dielectric film to define a resistance forming portion and Photosensitive film drawing in capacitor formation section * Dielectric film engraving process uses the aforementioned photosensitive film pattern as a mask to etch the dielectric film; the photosensitive film pattern removal process uses the aforementioned photosensitive film pattern and the aforementioned isolation insulating film as a mask In the remainder, the first conductive film is formed to form a floating gate at the same time. A resistance line and a first electrode terminal of the dielectric film are formed on the upper side, and then the photosensitive case is removed; Printed by the Bureau's Consumers' Cooperative (please read the precautions on the back before filling this page) j · M. The second conductive film formation project is included in the above One of the two edges of the insulation film and a predetermined portion of the substrate on the side wall of the floating gate. An insulating film is formed on the side wall of the resistance line and the side wall of the first electrode terminal, and a second conductive film is formed on the entire surface of the result; the photosensitive film project formation process is based on the storage on the second conductive film. The unit forming part and the peripheral circuit part are defined to form the electrode — __ The national standard of this paper (CNS > A4 specification (210X297)) Γ-- Λ7 B7 416135 V. Description of the invention (5) Forming part and capacitor The photosensitive film pattern in the forming section; and the photosensitive film pattern removal process, using the photosensitive film pattern as a mask, etching the second conductive film to form a control gate and a second electrode terminal simultaneously, and removing the photosensitive film. In order to achieve the aforementioned object, the method for manufacturing a non-electrolytic semiconductor device according to the second embodiment includes: a first conductive film and an oxidation prevention film formation process, which are defined in a memory cell formation section and a peripheral circuit section; On the semiconductor substrate, a first conductive film and an oxidation prevention film are sequentially formed; in the contact engraving process, the oxidation prevention film is etched to form the aforementioned memory cell A part of the surface of the first conductive film is exposed; the removal process is to use the foregoing oxidation prevention film as a mask, and after the isolation insulating film is formed in the memory cell formation portion by the oxidation process, the foregoing oxidation prevention film is removed; The "patterning process" is to form a photosensitive film pattern for defining the resistance forming portion and the capacitor forming portion on the peripheral circuit part on the aforementioned first conductive sheet; the photosensitive film pattern removing process is to form the aforementioned photosensitive sheet pattern and the isolation insulating film As a mask, the first conductive film is etched to float gates, resistance lines, and first electrode terminals at the same time, and then the photosensitive film pattern is removed. The first conductive film formation process is based on An insulating film is formed on the entire surface of the aforementioned resistance line and the entire surface of the first electrode terminal on a predetermined portion of the substrate of the edge portion and the side wall of the floating gate, and a second conductive film is formed on those results in full: 2! 0X297 公 楚) I t— n I.---- I ^ ti f — n I___ 丁-U3. Words (please read the notes on the back before filling out this page} Economy Printed by the Ministry of Standards and Technology ’s Consumer Cooperatives Λ7 Η 7 _ 416135 ----——-_ V. Description of the invention (6) Photosensitive film formation project 'is the storage unit forming section on the aforementioned second conductive film And a prescribed portion of the peripheral circuit portion to form a photosensitive film pattern defining the electrode forming portion and the capacitor forming portion; and a photosensitive film removal process, which uses the aforementioned photosensitive film pattern as a mask, and inscribes the aforementioned second conductive film After the control gate and the second electrode terminal are formed at the same time, the aforementioned photosensitive film pattern is removed. When a non-electrical semiconductor element having the structure as described above is manufactured, the engineering variables at the time of forming the resistor and the capacitor are reduced, which can prevent the Deterioration of characteristics due to changes in external temperature and input voltage. Embodiments of the Invention Embodiments of the present invention will be described below. In the present invention, a resistor and a capacitor having a stable resistance value and an electrostatic capacitance regardless of changes in external temperature and input voltage are formed together during the manufacture of non-electrically-dependent memory cells in a composite wafer, thereby achieving precision Technician of product design. At this time, the resistor 'necessary' for driving a chip with non-independent memory is used to make non-independent memory. The unit ’s floating gate ’s polymone is used to achieve this, and the capacitor is made by The above-mentioned floating silicone for the storage unit and the silicone for controlling the gate are used as two-electrode terminals, and a dielectric film formed by another route (such as an insulating film of a ΝΟΟ structure and an atmosphere film material) is placed therebetween. Insulation film). In this regard, a detailed description will be made with reference to the first circle to FIG. 18. Here, FIG. 1 to FIG. 11 are engineering sequence diagrams showing a method for manufacturing a non-electrical semiconductor device according to the first embodiment of the present invention; the 12th to 18th paper standards are applicable to the China Solid State Standard (CNS) ) A4 (210X297 public planting) n -.- IJ 1 11 (Please read the meanings on the back. Please fill in this page) The Central Consumer Bureau of the Ministry of Economy Staff Consumer Cooperatives 9 9 416135 ^ a- '. _ V. Description of the Invention (7) The drawing is a process sequence diagram showing a method for manufacturing a non-electrical semiconductor device according to a second embodiment of the present invention. In the foregoing figure, a portion indicated by the symbol a indicates the formation portion of the non-electrical-dependent memory cell of the aforementioned element; a portion indicated by the symbol b indicates the resistance formation portion of the aforementioned element; a portion indicated by the symbol (; Capacitors for the components. First, the first embodiment will be described here. For convenience, the aforementioned process is divided into eleven stages. The first stage is as shown in FIG. 1 on the semiconductor substrate 100. The field oxide film 102 is formed in a prescribed portion to define peripheral circuit portions (the resistance forming portion (b) and the capacitor forming portion (c)), and the gate insulating film 104 is selectively formed only in the memory cell on the substrate 100. The second stage is: as shown in FIG. 2 'on the foregoing gate insulating film 104 and field oxide film 102, a first conductive film made of polysilicon steel and an oxidation prevention film 108 made of nitride film are formed in this order. At the time, the aforementioned first conductive medium ι〇6 is formed to a thickness of 1000 to 2000 A. In the second stage, as shown in the figure and the figure, 'for the storage unit formation section 3, the Ministry of Economic Affairs Central Standards Bureau employee consumer cooperative printed and oxidized. A specific portion of the stopper film 108 is exposed on the surface and is selectively etched to form a photosensitive film pattern.] 10 After that, use it as a mask to dry-etch the oxidation prevention film. 08. At this time, the oxidation prevention film of the resistance formation portion b and the capacitor formation portion c. 1 08 is not etched because it is protected by the photosensitive film pattern 110. The fourth stage is: as shown in FIG. 4 'the photosensitive film pattern is not removed, and then the oxidation prevention film 108 is used as a mask to perform the oxidation process, which As a result, the isolation insulating film 112 »10 was selectively formed only on the portion not protected by the oxidation prevention film 10 8 (Please read the back; i-notes before filling out this page) The paper size applies the Chinese National Standard (CNS) A4 specifications (2 丨 0X297)
經濟部中央標隼扃貝工消費合作社印製 五、發明説明（8 ) 第五階段為：如第5圊所示，去除氧化防止膜1〇8。 第六階段為：如第6圖所示，在包含隔離絕緣膜112之 第一導電性膜106全面，形成όνο構成之介電膜114，然 後僅在該介電骐114上之電阻形成部b及電容器形成部(；選 擇性地形成感光膜圖案l10f 第七階段為：如第7圖所示，將感光膜圖案u〇作為掩 模银刻介電膜Π4，接著將前述隔離絕緣膜U2及感光膜圖 案110作為掩模，在前述存儲單元形成部及其周圍之電路 部全領域，蝕刻處理第—導電性膜丨〇6之後，去除感光膜 圊案110°其結果，僅在存儲單元形成部a形成聚矽酮材質 之漂浮閘106a及隔離絕緣膜112，在電阻形成部形成聚矽 綱材質之電阻線106b，而在電容器形成部則形成聚矽酮材 質之第一電極端子l〇6c。 第八階段為··如第8圖所示，為了形成漂浮閘i〇6a與其 以後所形成的控制閘間之絕緣，及在電晶體之閘絕緣膜所使 用的氧化膜材質之絕緣膜，而施行氧化工程，其結果，存儲 單元形成部a ’係在包含隔離絕緣膜112之兩邊緣部及漂浮閘 106a之兩侧壁的閘絕緣膜1〇4上，形成一盡隧道氧化膜之任 務的厚度大約50〜200A之絕緣膜116 ;而電阻形成部及電容 器形成部c則在電極線l〇6b之兩侧壁及第一電極端子i〇6c之 兩側壁，分別形成厚度大約50〜200A之絕緣膜116。 第9階段為：如第9圖所示，在包含一形成有隧道絕緣 膜116及隔離絕緣膜112之漂浮閘，一在上部形成有介電膜 114之電極線1.06b及一第一電極端子l〇6c之基板全面，形 本紙張尺度適用中國國家標準（CNS ) A4規格（210X29?公釐） 11 (請先聞讀背面之这意事項再填寫本頁) •裝' 訂· 416135 Λ7 ^〜丨——1 -------------—- ____ 五、發明説明（9 ) 一' 成厚度1000〜2000A之聚矽鲷材質之第二導電性膜。之所 以如此形成第二導電性膜，是因為除了形成用做存储單元 之控制閘及電容器之第一電極端子106c以外，更形成其他 之第二電極端子之故。其次，在第二導電性膜上形成一用 來界定控制閘形成用部分及!第二電極端子形成用部分的感 光骐圖案110，將之作為掩模乾蝕刻第二導電性膜。在此 過程中，周迅電路部之電阻形成部b並未由感光膜圖案所 保護，因此第二導電性膜之全部被除去，使電阻線106b上 之介電膜114表面全部露出之反面，電容器形成部^只露出 未被感光膜圖案Π0所保護之部分的介電膜114表面。其結 果，在存儲單元形成部a形·成聚發嗣材質之控制閘n8a ; 在周邊電路部之電容器形成部c則形成聚矽酮材質之第二 電極端子118c。 即，由前述圖式可知，電阻線106b及電容器之第—電 極端子106c，係由跟漂浮閘106a相同之材質所形成；電容 器之第二電極端子118e則由跟控制閘118a相同之材質所形 成。 ， 經濟部中央標率局員工消費合作社印裝 -----------_--'裝------訂 (請先閱讀背面之诖意事項再填寫本頁) 第十階段為：如第10圊所示，去除感光膜圓案11 〇， 進而只在存儲單元電晶體之源極及汲極形成部選擇性地離 子植入高濃度之雜質，以在存儲單元形成部a之基板1〇〇内 形成源及汲領域120、122。 第十一階段為：如第11圖所示，在形成有那些結果物 之基板100全面，形成層間絕緣膜124’然後蝕刻層間絕緣 膜124及介電膜114以形成接觸孔，以便露出汲領域122之 本紙張尺度適用t關家標芈（CMS ) A4規格（210X297公龙} ：~^~~ 416135 A7 B? 經濟部中央標準局員工消費合作社印装 五、發明説明（10 ) 基板100表面規定部分以及電阻線106b、第一電極端子106c 、第二電極端子118c之表面規定部分。接著，於包含接觸 孔之層間絕緣膜124上形成A1及Cu合金材質之位元線126 ，而完成本工程。 其結果，由第11圖可Μ :在半導體基板上之存儲單元 形成部a，形成一透過隧道氧化膜（用符號116表示之部分） 層合用來存儲電子之漂浮閘1 〇6a及將之調節的控制閘118a 之非依電性記憶電晶體；在其板上之電阻形成部b，形成 跟漂浮閘106a相同材質之電阻線106b ;在基板1〇〇上之電 容器形成部c，形成一透過介電膜114層合跟漂浮閘相同材 質之第一電極端子l〇6c及跟控制閘118a同一材質之第二電 極端子118c以便介電膜114表面只露出一規定部分之電容 器；在形成有非依電性存儲單元，電極線106b及電容器之 基板100全面，形成具有接觸孔之層間絕緣膜124，以便露 出前述存儲單元之特定部分，前述電阻線106b之表面規定 部分，及前述第一、第二電極端子106c、118c;在包含接 觸孔之層間絕緣膜124上之規定部分.，則形成一形成有位 元線126以便與前述控制閘118a垂直交叉的非依電性半導 體元件》 其次，說明第二實施例。本實施例除了不將形成在電 容器之第一電極端子106c與第2電極端子118間之介電膜 114，透過另外之膜質（例如ΟΝΟ構造之絕緣膜）蒸鍍工程 來形成，而是將氧化工程（為形成隧道絕緣膜而實施）中所 製作之氧化膜材質之絕緣膜直接使用介電膜以外，基本性 (請先閏讀背面之诠意事項再填寫本頁) 、裝. ，1Τ -I冰_ 本紙張尺度適用中國國家標準（CNS > Α4規格（210Χ297公t ) ΤΊ 4^6135 A7 一一~~-~~—--__B? 一 五、發明説明（U ) 之工程則與第-實施例同樣地進行，因此與第一實施例不 同之部分為中心說明其製造方法。在此，為方便而將本實 施例之工程區分七階段來說明之。 第一階段為：如第12圖所示，在存儲單元形成部a形成開 絕緣膜204 ;週邊電路部（電，成部b及電容器形成部c)則在 形成有場氧化膜202之半導體基板2〇〇全面依次聚石夕網材質之 第-導電性膜206及氡化防止膜(未圖示）之後，在其上面形成 感光膜圖案（未圖示）以便存儲單元形成部之氧化防止膜表面露 出特定部分。將感光膜圖案作為掩模絲刻氧化防止膜，去 除感光膜圖案之後，施行氧化工程，藉此只在未由氧化防止 膜所保護之存儲單元形成部·選擇性地形成熱氧化膜材質之隔 離絕緣膜212 ,然後去除氧化防止膜。 第一階段為：如第13圖所示’只在第一導電性膜2〇6上之 電阻形成部b及電容器形成部£;，選擇性地形成感光膜圖案21〇。 經濟部中央標準局員工消费合作社印装 第三階段為：如第14圖所示，將隔離絕緣膜212及感光 膜圖案210作為掩模，在存儲單元形成部a及周邊電路部之全 領域蝕刻第—導電性臈206後，去除感光膜圖案210。其結果 ’在單存儲單元形成部a形成聚矽酮材質之漂浮閘2〇6a及隔 離絕緣膜212 ;在電阻形成部b形成聚矽酮材質之電阻線206b ;在電容器形成部形成聚矽嗣材質之第一電極端子206c。 第四階段為：如第15圖所示，為了形成漂浮閘206a及 此後形成之控制閘間之絕緣及在電晶體之閘絕緣膜所使用 之絕緣膜，而施行氧化工程。其結果，存儲單元形成部， 係在包含隔離絕緣膜212之兩邊緣部及漂浮閘206a之兩側 本紙浪尺度適用中国國家標準（CNS ) A4規格（2丨〇Χ 2ί»7公趋) -~ 經濟部中央標準局負工消費合作社印製 Λ7 H7 五、發明説明（U ) 壁的閘絕緣膜204上，形成在隧道絕緣膜所使用之氧化膜 材質之絕緣膜216(厚度約50〜200A);電阻形成部b及電容 器形成部c，則在電阻線206b及第一電極端子206c之全表 面，形成氧化膜材質之絕緣膜216(厚度大約50〜200 A)。 第五階段為：如第16罔所示’在包含一在上侧形成有 絕緣膜216及隔離絕緣膜212之漂浮閘206a及一在全表面形 成有絕緣膜216及電阻線206b，及第一電極端子206c之基 板200全面，形成聚發酮材質之厚度大約1〇〇〇〜2〇〇〇 A之 第二導電性膜。其之所以像這樣形成第二導電性膜，是因 為除了形成用做存儲單元之控制閘及電容器之第一電極端 子206c以外，更形成其他乏第二電極端子之故。其次，在 第二導電性膜上形成一用來界定控制閘形成用部分及第二 電極端子形成用部分之感光膜圖案210,然後將之作為掩 模乾蝕刻第二導電性膜。在此過程中，週邊電路部之電阻 形成部b並未由感光膜圖案所保護，因此使電阻線2〇615上 之絕緣膜216表面露出之反面，電容器形成部c只露出未被 感光膜圖案210所保護之部分的絕緣膜216表面。其結果， 在存儲單元形成部a形成聚矽酮材質之控制閘208a ;在周 邊電路部之電容器形成部c則形成聚矽嗣材質之第二電極 端子208c。 即，由前述圏式可知，電阻線206b及電容器之第一電 極端子206c，係由跟漂浮閘206a相同之材質所形成；電容 器之第二電極端子208c係由跟控制閘相同之材質所形成； 用做電容器之介電膜則由氧化膜材質之絕緣膜216所形成 本紙張尺度適财關家料（CNS)祕見格（21()>< 297公4 ) 15 ----^----!-1 1¾衣------ΐτ------^ (請先閱讀背面之注意事項再填寫本頁} 經濟部中央標隼局貝工消費合作社印裝 416135 Λ7 __ B1 · · __ ___ 里 _ 五、發明説明（13 ) 〇 第六階段為：如第17圊所示，去除感光膜圖案210, 進而只在存儲單元電晶體之源極及汲極形成部選擇性地離 子植入高濃度之雜質，以在存儲單元形成部a之基板200内 形成源及汲領域220、222。.丨 第七階段為：如第18圖所示，在形成有那些結果物之 基板200全面，形成層間絕緣膜224，然後乾蝕刻層間絕緣 膜224及絕緣膜216以形成接觸孔，以便露出一形成有汲領 域222之基板200表面規定部分以及電阻線206b，第一電極 端子206c、第二電極端子21 8c之表面規定部分。接著，於 包含接觸孔之層間絕緣膜224上形成A1或Cu合金材質之位 元線226 *而完成本工程。 當根據此種工程順序製造非依電性半導體元件時，在 電容器之製造時並不需要形成另外之介電膜，因此比第一 實施例之情況更可獲得工程單純化及成本節減之效果。. 又，此時，除了用做電容器之介電膜係由氧化膜所成 以外，餘則與第一實施例所提示之元.件及基本構造相同， 因此省略構造之說明。 若像這樣製造用以使非依電性存儲單元之周邊電路用 電阻及電容器時，較之習知技術之在實現内設有快閃記憶 體之複合晶片時將電阻體形成於高濃度之雜質領域（例如 n_或p+活性領域），並將電容器形成為MOS所一般使用過 來的MIN構造（例如堆疊型 '溝渠型、銷型及圓筒型）者， 更可減少這些製造時之工程變數，因此可防止因外部溫度及 本紙张尺度適用中關家標準（c叫A4規格（21〇><2们公势） "~Γ6~~ _ ^-I ------ΐτ------^ (請先Μ讀背面之ΪΪ意事項再填寫本頁) 416135 hi —------ Η ? 五 '發明説明（14 ) ~ ~~~ 一· 輸入電壓之變化而降低電阻及電容器之特性情事。其結果 ，可控制電阻及電容H之精密㈣值及電流值，從而可實 現精密製品之設計，也可提高元件之動作特性。 發明之效果 如上所說明，在形成蜱依電性存儲單元時，同時形成 為驅動該存儲單元而必要的電阻任務之「電極線路」及電 合任務之第一電極端子」、介電膜及第二電極端子，因 而具有以下之效果： ⑴為形成非依電性存儲單元而進行工程時減少工程變 數，藉此防止因外部溫度及輸入電壓之變化而降低電阻體 及電容器之特性（例如電阻值及靜電電容）之情事； ⑵因此，可控制電阻及電容器之精密電壓值及電流值 ’從而可實現高速度動作之高信賴性的半導體元件。 圖式之簡單說明 第1圖〜第11圖，係顯示依據本發明第一實施例之非 依電性半導體元件的製造方法之工程順序圖β 第12圖〜第18圖，係顯示依據本發明第二實施例之非 依電性半導體元件的製造方法之工程順序圖。Printed by the Central Ministry of Economic Affairs, Shellfisher Consumer Cooperatives V. Description of the invention (8) The fifth stage is as shown in Figure 5: removing the oxidation prevention film 108. The sixth stage is: as shown in FIG. 6, the first conductive film 106 including the insulating insulating film 112 is formed on the entire surface to form a dielectric film 114 composed of a dielectric film 114, and then only the resistance forming portion b on the dielectric film 114 is formed. And the capacitor forming portion (; the photosensitive film pattern l10f is selectively formed in the seventh stage: as shown in FIG. 7, the photosensitive film pattern u0 is used as a mask to etch the dielectric film Π4, and then the aforementioned isolation insulating film U2 and The photosensitive film pattern 110 is used as a mask, and the first conductive film is etched in the entire area of the aforementioned memory cell formation section and the surrounding circuit section, and the photosensitive film is removed by 110 °. As a result, only the memory cell is formed. The part a forms a polysilicon floating gate 106a and an isolation insulating film 112. A polysilicon resistance wire 106b is formed in the resistance forming part, and a capacitor forming part is formed with a first electrode terminal 106b made of polysilicone. The eighth stage is ... As shown in FIG. 8, in order to form the insulation between the floating gate i06a and the control gate formed later, and an insulating film made of an oxide film material for the gate insulating film of the transistor, Oxidative engineering As a result, the memory cell forming portion a ′ is formed on the gate insulating film 104 including the two edge portions of the insulating insulating film 112 and the two side walls of the floating gate 106a, and the thickness of the task of forming a tunnel oxide film is approximately 50 to 50. The insulation film 116 of 200A; and the resistance formation portion and the capacitor formation portion c are formed on the two sidewalls of the electrode line 106b and the two sidewalls of the first electrode terminal 106c respectively with an insulation film 116 having a thickness of about 50 to 200A. The ninth stage is: as shown in FIG. 9, a floating gate including a tunnel insulating film 116 and an isolation insulating film 112 is formed, an electrode line 1.06b having a dielectric film 114 formed on the upper part, and a first electrode terminal. The substrate of 〇6c is comprehensive, and the size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210X29? mm) 11 (Please read this matter on the back before filling in this page) • Binding 'Order · 416135 Λ7 ^ ~ 丨 ——1 ---------------- ____ V. Description of the invention (9)-A second conductive film made of polysilicon with a thickness of 1000 ~ 2000A. This is why The second conductive film is formed because in addition to the control gates and capacitors used as memory cells, In addition to the one electrode terminal 106c, other second electrode terminals are formed. Secondly, a photosensitive pattern 110 is formed on the second conductive film to define a control gate forming portion and a second electrode terminal forming portion. Use this as a mask to dry-etch the second conductive film. In this process, the resistance formation portion b of Zhou Xun's circuit section is not protected by the photosensitive film pattern, so all of the second conductive film is removed to make the resistance line On the opposite side of the surface of the dielectric film 114 exposed on 106b, the capacitor formation portion ^ exposes only the surface of the dielectric film 114 that is not protected by the photosensitive film pattern Π0. As a result, a control gate n8a made of a poly-hairlock material is formed in the memory cell formation portion, and a second electrode terminal 118c made of a silicone material is formed in the capacitor formation portion c of the peripheral circuit portion. That is, as can be seen from the foregoing drawings, the resistance line 106b and the first electrode terminal 106c of the capacitor are formed of the same material as the floating gate 106a; the second electrode terminal 118e of the capacitor is formed of the same material as the control gate 118a . , Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs -----------_-- 'installation ------ order (please read the intention on the back before filling this page) The ten stages are: as shown in the tenth stage, the photosensitive film circle 11 is removed, and then high-concentration impurities are selectively ion-implanted only at the source and drain forming portions of the memory cell transistor to form the memory cell. Source and drain regions 120 and 122 are formed in the substrate 100 of the part a. The eleventh stage is: as shown in FIG. 11, on the entire substrate 100 on which those products are formed, an interlayer insulating film 124 ′ is formed, and then the interlayer insulating film 124 and the dielectric film 114 are etched to form a contact hole to expose the drain region. The paper size of 122 is applicable to the standard of Guan Family Standard (CMS) A4 (210X297 male dragon): ~ ^ ~~ 416135 A7 B? Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (10) Part of the surface of the substrate 100 And the surface prescribed portions of the resistance line 106b, the first electrode terminal 106c, and the second electrode terminal 118c. Then, the bit line 126 of A1 and Cu alloy material is formed on the interlayer insulating film 124 including the contact hole to complete the project. As a result, as shown in FIG. 11, the memory cell formation part a on the semiconductor substrate forms a tunnel oxide film (the part indicated by the symbol 116). A floating gate 106a for storing electrons is laminated and adjusted. The non-independent memory transistor of the control gate 118a; the resistance formation part b on its board forms a resistance wire 106b of the same material as the floating gate 106a; the capacitor formation part c on the substrate 100 Forming a first electrode terminal 106c of the same material as the floating gate and a second electrode terminal 118c of the same material as the control gate 118a through the dielectric film 114 so that only a prescribed portion of the capacitor is exposed on the surface of the dielectric film 114; An interlayer insulating film 124 having a contact hole is formed on the entire substrate 100 on which the non-electrostatic memory cell, the electrode line 106b and the capacitor are formed, so as to expose a specific portion of the aforementioned memory cell, a prescribed portion of the surface of the aforementioned resistive line 106b, and the aforementioned The first and second electrode terminals 106c, 118c; on a predetermined portion of the interlayer insulating film 124 including a contact hole, a non-electrostatic semiconductor element having a bit line 126 formed so as to perpendicularly intersect the aforementioned control gate 118a is formed. 》 Next, the second embodiment will be described. In this embodiment, the dielectric film 114 formed between the first electrode terminal 106c and the second electrode terminal 118 of the capacitor is not vaporized through another film (for example, an insulating film with a ΝΟΟ structure). It is formed by a plating process, but the dielectric film of the oxide film material used in the oxidation process (implemented to form a tunnel insulating film) is directly made of dielectric. Beyond the film, basic (please read the explanation on the back before filling out this page), install., 1T -I ice _ This paper size applies to Chinese national standards (CNS > Α4 size (210 × 297 public t) ΤΊ 4 ^ 6135 A7 One-to-One ~~-~~ ---__ B? Fifth, the invention description (U) process is performed in the same way as the first embodiment, so the parts different from the first embodiment are mainly described in the manufacturing method. Here, for convenience, the process of this embodiment is divided into seven stages to explain. The first stage is: as shown in FIG. 12, an open insulating film 204 is formed in the memory cell forming section a; the peripheral circuit section (electrical, The part b and the capacitor formation part c), after the semiconductor substrate 2000 having the field oxide film 202 formed thereon, is sequentially formed of the first conductive film 206 of the polysilicon mesh and the anti-cure film (not shown). A photosensitive film pattern (not shown) is formed thereon so that the surface of the oxidation preventing film of the memory cell forming portion is exposed to a specific portion. The photosensitive film pattern is used as a mask to etch the oxidation prevention film. After removing the photosensitive film pattern, an oxidation process is performed to selectively form the isolation of the thermal oxidation film material only in the memory cell formation portion that is not protected by the oxidation prevention film. The insulating film 212 is then removed from the oxidation preventing film. The first stage is: as shown in FIG. 13 ′, only the resistance forming portion b and the capacitor forming portion on the first conductive film 206 are formed, and the photosensitive film pattern 21 is selectively formed. The third stage of the printing of the staff consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs is: as shown in FIG. 14, using the isolation insulating film 212 and the photosensitive film pattern 210 as masks, and etching the entire area of the memory cell formation section a and the peripheral circuit section. After the first conductive layer 206, the photosensitive film pattern 210 is removed. As a result, a floating gate 206a made of a silicone material and an isolation insulating film 212 were formed in the single memory cell formation portion a; a resistance line 206b made of a silicone material was formed in the resistance formation portion b; a polysilicon was formed in the capacitor formation portion. The first electrode terminal 206c is made of a material. The fourth stage is: as shown in FIG. 15, in order to form the floating gate 206a and the control gate formed thereafter and the insulating film used in the transistor gate insulating film, an oxidation process is performed. As a result, the memory cell forming portion is adapted to the Chinese National Standard (CNS) A4 specification (2 丨 〇Χ 2ί »7 common trend) at the two edges of the insulating insulating film 212 and the two sides of the floating gate 206a. ~ Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Λ7 H7 V. Description of the invention (U) The gate insulating film 204 on the wall is formed on the insulating film 216 (thickness of about 50 ~ 200A) of the oxide film material used in the tunnel insulating film ); The resistance forming portion b and the capacitor forming portion c, an insulating film 216 (thickness of about 50 to 200 A) made of an oxide film is formed on the entire surface of the resistance line 206b and the first electrode terminal 206c. The fifth stage is: as shown in 16), 'a floating gate 206a including an insulating film 216 and an isolation insulating film 212 formed on the upper side, and an insulating film 216 and a resistance line 206b formed on the entire surface, and the first The entire substrate 200 of the electrode terminal 206c is formed as a second conductive film having a thickness of about 100-2000A in a polyketone material. The reason why the second conductive film is formed in this manner is that in addition to forming the first electrode terminal 206c for the control gate and capacitor of the memory cell, other second electrode terminals are formed. Next, a photosensitive film pattern 210 is formed on the second conductive film to define a portion for forming a control gate and a portion for forming a second electrode terminal, and then it is used as a mask to dry-etch the second conductive film. In this process, the resistance forming portion b of the peripheral circuit portion is not protected by the photosensitive film pattern, so the opposite side of the surface of the insulating film 216 on the resistance line 2015 is exposed, and the capacitor forming portion c only exposes the non-photosensitive film pattern. The surface of the insulating film 216 of the portion protected by 210. As a result, a control gate 208a made of a silicone material is formed in the memory cell formation portion a; and a second electrode terminal 208c made of a polysilicon material is formed in the capacitor formation portion c of the peripheral circuit portion. That is, it can be known from the foregoing formula that the resistance wire 206b and the first electrode terminal 206c of the capacitor are formed of the same material as the floating gate 206a; the second electrode terminal 208c of the capacitor is formed of the same material as the control gate; The dielectric film used as a capacitor is formed by an insulating film 216 made of an oxide film. The paper size is suitable for household materials (CNS). (21 () > < 297 Gong 4) 15 ---- ^ ----!-1 1¾ clothing ------ ΐτ ------ ^ (Please read the precautions on the back before filling out this page} Printed by the Shell Industry Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 416135 Λ7 __ B1 · · __ ___ _ _ 5. Description of the invention (13) 〇 The sixth stage is as shown in Figure 17: removing the photosensitive film pattern 210, and then selecting only the source and drain forming portions of the memory cell transistor High-concentration impurities are ion-implanted to form source and drain regions 220 and 222 in the substrate 200 of the memory cell forming section a. The seventh stage is: as shown in FIG. 18, those results are formed The entire substrate 200 is formed to form an interlayer insulating film 224, and then the interlayer insulating film 224 and the insulating film 216 are dry-etched to form a contact In order to expose a predetermined portion of the surface of the substrate 200 on which the drain region 222 is formed, and a predetermined portion of the surface of the resistance line 206b, the first electrode terminal 206c, and the second electrode terminal 21 8c. Next, an interlayer insulating film 224 including a contact hole is formed A1 or Cu alloy bit line 226 * to complete this project. When manufacturing non-electrical semiconductor elements according to this process sequence, it is not necessary to form another dielectric film during capacitor manufacturing, so it is better than the first In the case of the embodiment, the effect of engineering simplification and cost reduction can be obtained. Also, at this time, except that the dielectric film used as the capacitor is made of an oxide film, the rest is the same as that suggested in the first embodiment. The components and the basic structure are the same, so the explanation of the structure is omitted. If the resistors and capacitors for peripheral circuits of non-electrical memory cells are manufactured in this way, compared with the conventional technology, the flash memory is provided in the implementation. For compound wafers, the resistor is formed in a high-concentration impurity region (such as n_ or p + active region), and the capacitor is formed into a MIN structure commonly used in MOS (such as Stacked 'ditch type, pin type, and cylindrical type' can further reduce the engineering variables during manufacturing, so it can prevent the application of the Zhongguan standard (c is called A4 specification (21〇 >) due to external temperature and the paper size. < 2 men's power) " ~ Γ6 ~~ _ ^ -I ------ ΐτ ------ ^ (please read the intention on the back before filling in this page) 416135 hi —- ----- Η? Five 'invention description (14) ~~~~ 1. Changes in input voltage reduce the characteristics of resistors and capacitors. As a result, the precise threshold value and current value of the resistor and capacitor H can be controlled, thereby realizing the design of precision products and improving the operating characteristics of the device. Effects of the Invention As described above, when a tick-dependent memory cell is formed, an "electrode circuit" and a first electrode terminal of the "coupling task", a dielectric film, and a first electrode terminal necessary for driving the memory cell are simultaneously formed. Two-electrode terminals have the following effects: 减少 Reduce engineering variables during engineering to form non-dependent memory cells, thereby preventing the characteristics of resistors and capacitors (such as resistance values from being reduced due to changes in external temperature and input voltage). And electrostatic capacitance); ⑵ Therefore, it is possible to control the precise voltage and current values of resistors and capacitors, thereby realizing high-reliability semiconductor devices with high speed. Brief Description of Drawings Figures 1 to 11 are engineering sequence diagrams showing a method for manufacturing a non-electrical semiconductor device according to the first embodiment of the present invention. Figures 12 to 18 are diagrams showing the method according to the present invention. Process sequence diagram of a method for manufacturing a non-electrical semiconductor device according to the second embodiment.
In ft ' n n n. -林^— I I I I —丁—— ___I _ A (請先閲讀背面之这意事項再填寫本頁) 經濟部中央標隼局員工消費合作社印製 Γ7 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X29>?公釐） 4^6135 Λ7 R? 五、發明説明（15) 元件標號對照 100.200.. .半導體基板 106a,206a...漂浮閘 106b，206b...電阻線 106c,206c...第一電極端子 114.. .介電膜 11 8a...控制閘 118c,218c...第二電極端子 124,224…層間絕緣膜 126,226…位元線 ----.I-----'裝-- 請先閱讀背面之ii意事項再填寫本頁) 訂 經濟部中央標準局貝工消費合作社印製 18 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公釐）In ft 'nn n.-林 ^ — IIII — 丁 —— ___I _ A (Please read the notice on the back before filling out this page) Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Γ7 This paper is applicable to China Standard (CNS) A4 specification (210X29 >? Mm) 4 ^ 6135 Λ7 R? V. Description of the invention (15) Component number comparison 100.200 ... Semiconductor substrates 106a, 206a ... Floating gates 106b, 206b ... Resistance lines 106c, 206c ... First electrode terminals 114 ... Dielectric film 11 8a ... Control gates 118c, 218c ... Second electrode terminals 124, 224 ... Interlayer insulation films 126, 226 ... Bit lines ---- .I ----- 'Installation-Please read the notice on the back of the page before filling out this page.) Ordered by the Central Standards Bureau of the Ministry of Economic Affairs and printed by the Shellfish Consumer Cooperatives. 18 This paper size applies to the Chinese National Standard (CNS) A4 specifications ( 2 丨 0X297 mm)