GB2143675A - High efficiency dynamic random access memory cell and process for fabricating it - Google Patents

Abstract

A random access memory cell is disclosed which includes spaced-apart N conductivity type source and drain regions 38(b), 38(a) and a first layer of polycrystalline silicon above and between them to provide a transfer gate 35(b). A diffused bit line 25 provides an electrical connection to the drain 38(a) of the transistor, and is overlaid by a relatively thick layer 27 of silicon dioxide to enable crossing the diffused bit line 25 with word lines 35. The first plate of the storage capacitor is a second layer 45 of polycrystalline silicon which is deposited over substantially all of the random access memory cell. The other plate of the capacitor is provided by a third layer 53 of polycrystalline silicon which is deposited over the entire memory cell array. The fabrication process is also disclosed and this includes forming periodic shorts between metal lines 62 and word lines 35 to reduce resistance. Capacitors in different cells have a common dielectric layer 50. <IMAGE>

Description

SPECIFICATION High efficiency dynamic random access memory cell and process for fabricating it Background of the invention Field of the invention This invention relates to semiconductor structures and processes, and in particular to an improved high efficiency cell for dynamic random access memories, and to processes for fabricating such cells.

Description of the prior art In the fabrication of large dynamic random access memories (herein RAM's) single transistor capacitive storage cells are widely used to provide economical random access read/write memory cells. Information is stored in such cells as an electric charge on a a small capacitor. In typical RAM's, the value of the capacitance is on the order of 50 femtofarads. A binary zero might be represented by zero charge and a binary one by a charge of several hundred femtocoulombs.

In such a RAM cell the transistor functions as an on/off switch to connect the capacitor to a bit line shared with other RAM cells. The transistor is also connected to word line, shared by many other RAM cells. When the word line is activated it turns on all of the transistors connected to it, but only one of these transistors is on a simultaneously activated bit line.

Thus, when the cell is selected for a read operation, the charge stored in the storage capacitor is shared between the capacitor and the capacitance of the dataline. Well known peripheral circuits are provided to read and write the RAM cells, as well as periodically refresh their contents.

One prior art dynamic RAM cell is described in "A 64 kbit MOS Dynamic RAM with Novel Memory Capacitor," IEEE Jo urnal of Solid-State Circuits, vol.

SC-15, No. 2, April 1980, at page 184. In that article a dynamic RAM cell for a 64 kbit RAM is described.

The RAM cell discussed there uses three separate layers of polycrystalline silicon to provide the storage node, ground plate, and word lines, as well as a metal line for the bit line. This random access memory cell, although suitable for 64,000 bit size memories, is difficult to implement in higher density memories for a number of reasons. First, higher density memories have typically been achieved by shrinking the cell size of individual cells in the dynamic RAM, yet maintaing a substantially constant overall die size. Thus the storage capacitor for an individual RAM cell has become progressively smaller, making detection of the change in voltage when the bit line for such a cell is sensed increasingly difficult.

Another disadvantage of many prior art dynamic random access memory cells is the undesirably large amount of wafer surface area required for their fabrication. Typically such cells have been designed in a manner which places the switch, typically a transistor, on the wafer surface adjacent a region used as a capacitor. In addition to consuming more of the surface of the wafer, such a design requires the use of fabrication processes in which transistors and capacitors are fabricated using a single process, which, therefore, is not optimal for either. Furthermore, such a structure requires vertical transitions from cell to cell to pass conducting lines over diffusions without forming undesired transistors.

Every increase in overall roughness of the surface of a cell, such as those which accompany the fabrication of vertical jumpers, creates difficulties in step coverage, alignment, edge effects, fringe fields, and other well known problems.

Furthermore, designing a random access memory cell in this manner requires that all regions of the transistor and all regions of the capacitor be defined, typically using photolithographic processes. As is well known, compensation for manufacturing tolerances during such processes requires substantial increases in the die surface area. An additional disadvantage of prior art random access memory cells is the limitation such cell designs impose upon making electrical connections to the word and bit lines. This disadvantage results from the fabrication of the word and bit lines above the surface of the wafer, but many layers below the upper surface of the semiconductor structure. This makes providing electrical connections to such lines difficult.

Another dynamic RAM cell known in the prior art is described in "A 5-V Only 1 6-kbit Stacked-Capacitor MOS RAM," published in IEEE Transactions of Electron Devices, Vol. ED-27, No. 8, August 1980, at page 1596. That publication describes a one transistor memory cell in which the storage capacitor is formed partially over the transfer gate of each RAM cell. It is difficult to apply the random access memory cell described in this publication to very large dynamic memory arrays for several reasons.

First, the cell occupies an undesirably large surface area on the wafer, among other reasons, because of the need to allow space to form an electrical connection through many overlying layers to one electrode of the transistor. The provision of space for an electrical connection greatly limits the permissible area of the storage capacitor, and requires that individual masking and etching steps be repeated numerous times to define the lower and upper plates of the capacitor, as well as the dielectric of the capacitor. The resulting structure has extremely rough topography, which results in well known difficulties of the insulating the edges of numerous layers, fringe effects, and the manufacture of vertical contacts.Because of the particular cell structure the word line for the cell cannot be shorted by overlying metal, and therefore the cell has a relatively high RC constant and operates at slower speed than desirable. Furthermore, because of the limitation imposed by the manner of forming connections to the word line, the storage capacitor cannot occupy as large an area as desirable, and is therefore unable to store the maximum amount of charge.

Summary of the invention This invention provides an improved dynamic RAM cell suitable for the fabrication of very high density dynamic RAM's, on the order of 256 kbits and larger. The invention provides a dynamic RAM cell in which the entire cell area is utilized as the storage capacitor. The cell eliminates the need for metal bit lines, enabling the fabrication of simpler, more reliable electrical connections between the source and storage capacitor. The invention also provides a dynamic RAM cell having flattertopography than prior art cells. In addition, it enables the fabrication of buried bit lines by forming such bit lines using a separate implant and protecting them with a relatively thicker layer of insulating material to enable the word lines to cross the bit lines without forming gates.

The dynamic random access memory cell of this invention provides numerous other advantages over the prior art cells chosen for random access memories. Because the capacitor is stacked entirely above the switch (transistor), the cell may be fabricated in substantially smaller wafer surface area than prior art cells. In addition, stacking the transistor and the capacitor allows the use of processes optimized for the fabrication of each, rather than compromised for the fabrication of both. Thus, a process optimal to the fabrication of desired types of transistors may be employed, followed by a process optimal for the fabrication of a desired capacitor.

The process and structure of this invention eliminate the need for vertical jumpers over diffusions to avoid forming transistors. By eliminating vertical jumpers the resulting topography of the cell is substantially smoother than prior art structures, enabling the fabrication of smaller cells with higher accuracy. In the preferred embodiment metal is not required for a contact between the bit lines and the transistor because the bit lines are formed with a first implantation or diffusion, and the source/drain regions are formed with a second implantation or diffusion. Lateral diffusion of the impurity used for each connects the two and creates a reliable contact.

The particular cell layout allows the cell capacitor to be approximately the same size as the overall cell, and maximizes the size of the capacitor for any given cell size. In addition, the structure eliminates well known difficulties of accurately and reliably insulating the edges of various layers, and avoids the well known difficulties in reliably patterning thin silicon dioxide or other dielectric materials. Because, in the preferred embodiment, the ground plate for an entire array of memory cells comprises a single sheet of electrically conductive material, which is patterned only to expose peripheral circuitry and bonding pads on the die, manufacturing tolerances are tighter, and the overall fabrication process simpler.The particular cell structure associated with the stacked arrangement of this invention allows metal to short either the bit or word lines without difficulty in forming vias through intervening layers.

Exotic metals such as tantalum, platinum, or metal silicides may also be readily employed without significant modifications to the process. Because the structure readily accommodates being crossed by overlying electrically conductive lines, the RAM cells of this invention may be employed in microprocessors, or other devices, in which it is frequently desirable to cross the memory array with other conducting lines.

In one embodiment of our invention a random access memory cell includes a semiconductor substrate; a data line region in the substrate for transferring data; switching means such as a transistor connected to the data line region and to a charge storage means, for electrically connecting the data line region to the charge storage means as desired; the charge storage means including a lower electrically conductive region disposed at least partially overthe switching means, a dielectric layer disposed over all the lower electrically conductive region disposed on the dielectric layer and over the data line region, the switching means and the lower electrically conductive region.

In another preferred embodiment of our invention a process for fabricating random access memory cells in a semiconductor substrate includes the steps of introducing first conductivity type impurity into the substrate on opposite sides of an electrically conductive transfer gate region and in selected regions to thereby form spaced apart source and drain regions adjacent the transfer gate and at least one bit line region in the selected regions, the bit line region being connected to the drain region; forming a first electrically conductive plate connected only to the source region and overlying all of the transfer gate and all of the source region; depositing a layer of insulating material over at least all of the first electrically conductive plate; and forming a second electrically condutive plate over at least all of the first electrically conductive plate.

Brief description of the drawings Figure 1 is a cross-sectional view of a semiconductor substrate with overlying silicon dioxide, and silicon nitride, illustrating an initial structure for one embodiment of the process of this invention.

Figure 2 is a subsequent cross-sectional view after formation of field oxide regions.

Figure 3 is a subsequent cross-sectional view after formation of a bit line.

Figure 4 is a subsequent cross-sectional view after introduction of p-conductivity type impurities to adjust the threshold voltage of the to be formed MOS transistor, and deposition of a layer of polycrystalline silicon to provide the word line and transfer gate.

Figure 5 is a subsequent cross-sectional view after patterning of the word line and transfer gate regions, and introduction of n-conductivity type impurities to provide the source and drain regions.

Figure 6 is a subsequent cross-sectional view after formation of a second layer of polycrystalline silicon, which provides the lower plate of the capacitor for each RAM cell.

Figure 7 is a subsequent cross-sectional view after formation of the third layer of polycrystalline silicon to provide the upper plate for the capacitors of all RAM cells in the memory array.

Figure 8 is a cross-sectional view of the completed semiconductor structure.

Figure 9 is a top view illustrating an array of RAM cells fabricated according to this invention.

Figure 10 is an electrical schematic of a single RAM cell illustrating the relationship between the structure depicted in Figures 1 through 9 and a circuit containing such RAM cells.

Detailed description of the preferred embodiments Figures 1 through 9 illustrate a process for fabricating the random access memory cell of this invention, together with the resulting structure. As shown in Figure 1, on a p-conductivity < 100 > semiconductor silicon substrate having a resistivity of 6-7 ohm-centimeters, a first relatively thin layer of silicon dioxide 12 is formed. Silicon dioxide 12 will be on the order of 700 Angstroms thick and is fabricated by heating substrate 10 in an oxygen and hydrogen ambient to a temperature of 9000 C for 30 minutes. On the upper surface of silicon dioxide 12, a layer of silicon nitride 14 approximately 1500 Angstroms thick is deposited, typically using chemical vapor deposition.A layer of photoresist 16 approximately 12,500 Angstroms thick is deposited across the upper surface of nitride 14 using well known techniques. Also using well known techniques, photoresist layer 16 is masked and patterned to create regions 16a and 16b. Photoresist layers 16a and 16b function to define the field oxide regions, that is, regions of relatively thick silicon dioxide used to electrically isolate individual devices, or groups of devices from other devices.

Those regions of silicon nitride 14 not protected by mask 16 are then removed using a plasma etching process with CF4 plasma. Boron or other Pconductivity type impurity is then implanted through the openings in masking layer 16 to form field implant regions 18a, 18b, and 18c as shown in Figure 2. The field implant regions 18 will have an impurity concentration on the order of 2.5 x 1013 atoms per cubic centimeter, and are formed by an ion implanation process in which the implant energy is 75 kev.

The resulting structure is then subjected to a relatively long thermal oxidation process, on the order of 6 1/3 hours at 9500 C to form regions of silicon dioxide 21 a, 21 b, and 21 c, all as shown in Figure 2.

During this process the silicon dioxide formed from the oxidation of the silicon substrate will lift the nitride layer 14 in the manner depicted in Figure 2.

The resulting silicon dioxide field regions 21 will be approximately 8,250 Angstroms thick.

Mask 16 is then removed, and a new mask 23 formed, also using photolithographictechniques.

New mask 23 as well as the underlying structure at this stage in the process are shown in Figure 2. In the preferred embodiment mask 23 is also formed with photoresist and is approximately 12,500 Angstroms thick. As will be apparent from subsequent process steps, mask 23 is used to define the locations of the bit line regions.

As next shown by Figure 3, and using the same plasma process described above in conjunction with the removal of nitride layer 14 in Figure 1, the exposed portions of nitride layer 14 in Figure 2 are removed. The underlying relative thin layer of silicon dioxide 12 is also removed, for example by wet etching.

Using ion implantation, arsenic or other suitable n-conductivity type dopant is introduced into substrate 10 throug h the opening in mask 23. In the preferred embodiment arsenic is introduced with an implant energy of 40 kev to produce an impurity concentration of 5 x 1015 atoms per cubic centimeter in the substrate. The resulting bit line region 25 is shown in cross section in Figure 3. In general the bit lines will connect to every transistor in the substrate, as is shown in Figure 9, and are usually formed orthogonally to the word lines. The semiconductor structure is then reoxidized at 9500 C for 60 minutes in steam to create a relatively thick layer of silicon dioxide 27 over the bit line region 25 and between field oxide regions 21b and 21a as shown in Figure 3.

This relatively thicker silicon dioxide 27 and arsenic implant allow deposition of electrically conductive material across the upper surface of bit line 25 without forming undesired gates or transistors. The buried bit lines further eliminate the need for vertical jumpers or other "bridges" over the bit lines. The appearance of the structure after formation of silicon dioxide 27 is shown in Figure 3.

Silicon nitride layer 14 and silicon dioxide layer 12 then are removed from the surface of the structure.

The structure is then heated to 9000 C for 98 minutes to form a layer of silicon dioxide 30 across the surface of the substrate between field oxide regions 21 and 21 c, which is about 300 Angstroms thick.

Silicon dioxide 30 is the gate oxide for an MOS transistor which will be formed in this region.

Selected p-conductivity type impurity such as boron is then introduced into the region between silicon dioxide 21 and 21 c. In the preferred embodiment a boron impurity concentration of 6 x 1011 atoms per cubic centimeter is achieved using an implant energy of 50 kev. These impurities form region 32, shown in Figure 4. The impurity concentration of region 32 will be chosen to achieve the desired threshold voltage of the to be formed MOS transistors which, with the capacitors, will form the random access memory cells.

A layer of polycrystalline silicon 35 is next formed across the surface of the wafer, as shown in Figure 4.

In the preferred embodiment polycrystalline silicon 35 is deposited using a known chemical vapor deposition process to a thickness of about 5500 Angstroms. The back of the wafer is then etched to remove the polysilicon from the back.

The polycrystalline silicon 35 is then doped by introducing N conductivity type impurity, for example, phosphorous, to lower its resistivity to about 20 ohms per square.

As also shown in Figure 4, a layer of photoresist 36 approximately 12,500 Angstroms thick is next deposited across the upper surface of the wafer and conventionally patterned to define the regions 36a, 36b, and 36c shown. The photoresist layer 36 is allowed to remain on polycrystalline silicon layer 35 wherever layer 35 is to remain. The exposed regions of layer 35 are then removed, typically using a plasma comprising C12 and SF6.

Masking layer 36 is removed from the structure, and a relatively thin layer of silicon dioxide (not shown) is formed by heating the substrate to 900C C for 36 minutes. This relatively thin layer of silicon dioxide covers the substrate in the regions of the substrate which will function as the source and drain of the MOS transistor, and is to protect the single crystal silicon. N-conductivity type impurity, preferably arsenic, is then implanted to form the source/ drain regions on each side of the transfer gate region 35b as shown in Figure 5. In the preferred embodiment the source/drain regions are formed by ion implantation at an energy of 50 kev to produce an impurity concentration of 5 x 1015 atoms per cubic centimeter.

Generally, the drain region for each transistor will be implanted into the surface of the wafer over a surface area in proximity to one of the bit line regions 25. Thus, during subsequent thermal fabrication processes, the impurities in the bit line and in the drain will diffuse laterally, as well as deeper into the wafer. By suitable choice of the planar position of the bit lines and drain regions, this lateral diffusion will cause the two regions to join together, thereby connecting the drain regions to the bit lines. As apparent from the preceding description, the bit lines and drain regions may be arbitrarily shaped.

Their shape in the preferred embodiment is most clearly seen in the top view of the structure shown in Figure 9.

An insulating layer is formed over the vapor deposited silicon dioxide and by heating the structure to 950 C for 13 minutes to create interpoly silicon dioxide layer 40, as also shown in Figure 5. In the preferred embodiment silicon dioxide 40 is 3000 Angstroms thick.

A layer of photoresist 42 is deposited across the upper surface of the entire structure,typicallyto a thickness of 12,500 Angstroms. Photoresist layer 42 is patterned and removed from region 43 where an electrical contact to the source region 38b is desired.

The appearance the structure at this stage of the process is shown by Figure 5.

Mask 42 is removed, and, as shown in Figure 6, a second layer of polycrystalline silicon 45 is deposited across the upper surface of the structure to a thickness of about 1700 Angstroms. Polycrystalline silicon 45 is then doped using arsenic implantation at 80 kevto a concentration of 8 x 1015 atoms per cubic centimeter to improve the electrical conductivity of the layer. A layer of photoresist 48 is deposited across the upper surface of the structure and patterned to define the lower electrode of the storage capacitor, for example, by removing it generally from above the bit line 25 and the drain region 38a, as shown in Figure 6. The second layer of polycrystalline silicon is then removed from these exposed regions, using the same plasma process as described above in conjunction with the first layer of po!ycrystalline silicon.The appearance of the structure at this stage in the process is depicted in Figure 6.

A top view of the structure illustrating the extent of the polycrystalline silicon regions is shown in Figure 9. Each region of electrically conductive polycrystalline silicon functions as the lower plate of a capacitor for the corresponding random access memory cell.

As may be apparent, the particular location of each plate with respect to the underlying structure is not significant, except that the plate be in electrical contact with a switch, that is, the source of a corresponding MOS device. To at least this extent the boundaries of an individual plate of the capacitor are arbitrary. For example, if desired, all the lower plates of the capacitors in the memory array might be rotated through an arbitrary angle from their location in Figure 9. The dimensions of the lower plate of each capacitor are determined by the minimum line width necessaryto assure that no plate contacts any of the adjoining plates.

After removal of mask 48, and using chemical vapor deposition, approximately 300 Angstroms of silicon nitride are deposited across the entire upper surface of the structure, to form layer 50 shown in Figure 7. The structure is then heated to reoxidize any of the second layer of polycrystalline silicon exposed as a result of flaws in the nitride 50. The reoxidation fills any such flaws with silicon dioxide preventing short circuits which would otherwise occur between the overlying layers and the second layer of polysilicon 45. Across the upper surface of silicon nitride 50 (and any silicon dioxide formed during the reoxidation step) a third layer of polycrystalline silicon 53, approximately 3300 Angstroms thick is deposited, also using chemical vapor deposition techniques.The third layer of polycrystalline silicon 53 is then doped with phosphorous to improve its conductivity, and a back etch again performed if desired. Another layer of photoresist is deposited across the upper surface of the structure and patterned, and polycrystalline silicon 53 and silicon nitride 50, respectively, are etched using a plasma containing Cl2 and SF6. In general the polycrystalline silicon 53 and silicon nitride 50 will be allowed to remain across the entire surface of the wafer, except where peripheral circuits for controlling the random access memory cell array are desired. Because these well known peripheral circuits are not shown in any of the figures, the polycrystalline silicon 53 and nitride 50 are shown in place across the entire upper surface of the structure depicted.

The fact that neither silicon nitride 50 nor polycrystalline silicon layer 53 need be patterned for individual cells provides a substantial advantage for the process and structure of this invention in contrast to the prior art. Numerous well known semiconductor fabrication problems which result from difficulties with step coverage, edge effects, the patterning thin dielectric materials, fringe fields, and other effects are all avoided. The use of the blanket insulating layer and blanket ground plate for the capacitor allows fabrication of the largest possible capacitors for a given cell size, and eliminates the need to provide masking and layout tolerances for the upper plate and insulating layer of each capacitor. The structure and process of this invention allow pattern- ing of the edge of the upper plate and thin dielectric only near the periphery of the entire random access memory array. This feature enables shrinking of the cell size of individual RAM cells, enabling the fabrication of higher density memories.

The fabrication of the capacitor plates above the transistor, or other switch, used to connect the capacitor to the data path also permits the optimization of the semiconductor process involved. In prior art random access memory cells a single process was used to fabricate transistors and capacitors, and optimization of the process for both functions was not readily available. Of particular advantage to the process of this invention is that it permits the use of an optimal transistor fabrication process with less concern for the effects of that process upon the fabrication of capacitors. In contrast to the prior art, in the preferred embodiment, the process of this invention fabricates capacitors after the fabrication of the transistors, enabling the use of a more optimal process for each.

As next shown in Figure 8, a layer of silicon dioxide 60 approximately 9,800 Angstroms thick is deposited across the upper surface of the wafer. This protective layer is densified by heating to 900 C for 20 minutes. Another mask, not shown in the figures, is formed across the upper surface of the wafer and patterned to expose those regions to which metal contact is desired, for example N+ conductivity regions, or polysilicon. In the preferred embodiment metal contact is desired to be made to the first layer of polycrystalline silicon at periodic intervals to reduce its resistance. Using a plasma containing CHF3, vapox 60 is etched, as well as in the underlying layers necessary to expose desired portions of the first layer of polycrystalline silicon 35, or N+ regions or the third layer of polysilicon, as needed in peripheral circuits.This mask is then removed, and a contact diffusion step performed to lower contact resistivity.

An alloy of aluminum with 1.5% silicon is then sputtered across the entire upper surface of the wafer to create layer 62, approximately 12,000 Angstroms thick. Layer 62 is then masked and etched, using well known photolithographic processes to define the desired regions of metal 62a, 62b, and 62c, all as shown in Figure 8. The metal layer is then alloyed by heating it to a temperature of 5000 C for 30 minutes. Of particular advantage to the process and structure of this invention is the ability afforded by the invention to short any desired underlying layer of polycrystalline silicon by repositioning the electrical contact to such layers. As evident from Figure 9, vias may be formed through overlying material to short either the bit lines, or the word lines as desired.The arrangement of prior art cells does not permit this flexibility.

Figure 8 also depicts the completed appearance of the random access memory cell of the preferred embodiment of the invention. As shown in Figure 8 the cell includes a transfer gate 35b, source and drain regions 38b and 38a, respectively, and a buried bit line 25 used to connect to the drains of a desired number of the RAM cells. A capacitor is provided by the combination of the second layer of polycrystalline silicon 45, and the closely spaced, but electrically separate third layer of polycrystalline silicon 53.

The metal 62 is used to short the first layer of polysilicon at desired intervals to reduce the overall resistance of the word lines.

Figure 9 is a top view of the structure shown in Figure 8, together with several surrounding random access memory cells fabricated in the same substrate. Figure 9 illustrates how the cell design depicted in cross-section in Figure 8 may be arranged to create a very high density random access memory. As shown in Figure 9, a series of bit lines 25 traverse the structure from side to side, with periodic stubs 25a extending from the bit lines 25 to contact the later formed drain regions 38a of pairs of transistors. A series of polycrystalline silicon word lines 35 traverse the structure from top to bottom, and, in the preferred embodiment, are each overlaid by a metal line 62. Periodic shorts between the metal lines 62 and the polysilicon lines 35 reduce the effective resistance of the overall structure.The number of these is determined by the desired first layer polysilicon word line delays. The shorts are formed by etching openings in the dielectric material overlying the third layer of polysilicon 53.

Wherever the gate oxide is sufficiently thin, and one of the polysilicon lines 35 crosses the substrate between source and drain regions 38a and 38b, a transfer gate 35b is formed. The second layer of polycrystalline silicon 45c is disposed over effectively all of the cell area. Six such plates of polycrystalline silicon 45 are shown in Figure 9. Disposed across the entire upper surface of the structure, and therefore not shown in Figure 9, are the thin layer of silicon nitride 50 and the third layer of polycrystalline silicon 53, which provide a common dielectric and ground plate for all storage capacitors on the die.

Figure 10 is an electrical schematic of the random access memory cell shown in cross-section in Figure 8 and in top view in Figure 9. Components of Figure 10 corresponding to those in the other figures are given corresponding reference numerals. Figure 10 illustrates that the word line comprises polycrystalline silicon layer 35b and metal 62; the bit line comprises implanted region 25; and the upper plate of the storage capacitor, together with the power supply line comprises the third layer of polycrystalline silicon 53. The switch to connect the capacitive storage to the bit line includes the polycrystalline silicon gate 35b, and the drain and source regions 38a and 38b, respectively, of an MOS transistor. The gate oxide 30 separates the first layer of polysilicon from the source and drain regions.The plate of the capacitor coupled to the source comprises the second layer of polycrystalline silicon 45c.

As explained, the first layer of polycrystalline silicon is used for the transfer gates, while the second and third layers are used to provide storage capacitors which are stacked above the switching devices. In the preferred embodiment, metal is not used directly in the random access memory cell, but contacts the word lines at periodic intervals over the entire array of memory cells. This enables the fabrication of a polycrystalline silicon word lines which have very short RC delay. Because in the preferred embodiment a separate implant is used to fabricate the bit lines, and is followed by formation of a thick layer of silicon dioxide, the polycrystalline word lines cross the bit lines without forming gates.

The storage area of the capacitor associated with each cell occupies substantially the entire cell area, providing improved performance compared to prior art structures. In addition, the structure and process of this invention provide substantially flatter topog raphy, which may be more readily and reliably traversed by overlying layers, thereby improving yields and lowering costs.

The foregoing has been a description of the preferred embodiment of the dynamic random access memory cell of this invention, together with a process for fabricating it. Although specific times, temperatures, thicknesses, conductivity types, and numerous other details have been provided to explain the manner of fabricating the structure and the resulting structure itself, these details are not to be interpreted as limiting the invention. For example, the terms source and drain have been used to refer to specific electrodes, and as well known, may be interchangeably applied depending upon biasing of the cell. Additionally, although the process of this invention has been explained in conjunction with the fabrication of silicon gate MOS devices, the process, and resulting random access memory cell may be readily adapted to the fabrication of metal gate MOS devices. In such embodiments the source/drain regions will not necessarily be self aligned to the metal gate, but may be fabricated using conventional MOS technology. The scope of the invention may be more completely ascertained from the appended

Claims (3)

claims. CLAIMS

1. A memory cell comprising: a semiconductor substrate; a data line region in the substrate for transferring data; switching means connected to the data line region and to a charge storage means, for electrically connecting the data line region to the charge storage means as desired; the charge storage means including: a lower electrically conductive region disposed at least partially over the switching means, a dielectric layer disposed over all the lower electrically conductive region, and an upper electrically conductive regin disposed on the dielectric layer and over the data line region, the switching means and the lower electrically conductive region.

2. A random access memory cell comprising: a semiconductor substrate; spaced-apart source and drain regions of first conductivity type in the substrate; an electrically conductive transfer gate region disposed between the source and the drain regions, and separated from the substrate, the source, and the drain regions by a layer of insulating material; an electrically conductive line connected to the transfer gate for supplying control signals thereto; a data transfer region of first conductivity type in the substrate extending to the drain region; a first electrically conductive plate disposed above portions of the electrically conductive line, all of the drain region, and all of the transfer gate region, the first plate being electrically connected only to the source region; and a second electrically conductive plate disposed over all of the above structure, and separated from the first electrically conductive plate by insulating material, the first and second electrically conductive plates providing capacitor means for storing charge.

3. A processforfabricating a random access memory cell on a semiconductor substrate comprising: introducing first conductivity type impurity into the substrate on opposite sides of an electrically conductive transfer gate region and in selected regions to thereby form spaced-apart source and drain regions adjacent the transfer gate and at least one bit line region in the selected region, the bit line region being connected to the drain region; forming a first electrically conductive plate connected only to the source region and overlying all of the transfer gate and all of the source region; depositing a layer of insulating material over at least all of the first electrically conductive plate; and forming a second electrically conductive plate over at least all of the first electrically conductive plate.