JP2003100887A - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the sameInfo
- Publication number
- JP2003100887A JP2003100887A JP2001294906A JP2001294906A JP2003100887A JP 2003100887 A JP2003100887 A JP 2003100887A JP 2001294906 A JP2001294906 A JP 2001294906A JP 2001294906 A JP2001294906 A JP 2001294906A JP 2003100887 A JP2003100887 A JP 2003100887A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- layer
- insulating film
- layer electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title description 2
- 238000002955 isolation Methods 0.000 claims abstract description 30
- 229910021332 silicide Inorganic materials 0.000 claims description 19
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 19
- 238000000926 separation method Methods 0.000 claims description 14
- 238000010030 laminating Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 239000012212 insulator Substances 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 124
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 24
- 239000011229 interlayer Substances 0.000 description 12
- 238000000034 method Methods 0.000 description 10
- 238000009413 insulation Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000007306 functionalization reaction Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置に関
し、特に積層する上層／下層電極構造およびそのコンタ
クト孔部の構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an upper / lower layer electrode structure to be laminated and a structure of a contact hole portion thereof.
【０００２】[0002]
【従来の技術】近年、半導体装置の多機能化に伴い、高
精度で高密度のメモリ回路、ロジック回路あるいはアナ
ログ回路を半導体チップに集積する混載デバイスが必要
とされてきている。そこで、例えばアナログ回路を構成
する容量素子の高精度化および高密度化が必須になる。
また、例えばＥＥＰＲＯＭあるいはフラッシュメモリの
ような不揮発性半導体記憶装置においては、昇圧回路の
搭載が必須であり、そのためのチャージポンプ回路には
比較的大きな面積の容量素子が必要になる。このような
容量素子では対向電極として積層する電極を形成し、そ
れぞれの電極をコンタクト孔を通して配線に接続するこ
とが必要になる。2. Description of the Related Art In recent years, with the multi-functionalization of semiconductor devices, there has been a demand for an embedded device in which a highly accurate and high density memory circuit, logic circuit or analog circuit is integrated on a semiconductor chip. Therefore, for example, it is indispensable to increase the precision and the density of the capacitive element that constitutes the analog circuit.
Further, for example, in a nonvolatile semiconductor memory device such as an EEPROM or a flash memory, it is essential to mount a booster circuit, and a charge pump circuit for that purpose requires a capacitive element having a relatively large area. In such a capacitive element, it is necessary to form an electrode to be laminated as a counter electrode and connect each electrode to a wiring through a contact hole.
【０００３】上述したフラッシュメモリの形成における
容量素子の形成方法として種々の技術が提案されてい
る。例えば、特開平１１−３０７７４５号公報、特開平
１０−００４１７９号公報等に記載されている。以下、
このような従来の技術について図４乃至図６に基づいて
説明する。判りやすくするために、これらの図におい
て、本発明と比較されることになる下層電極には斜線を
施している。Various techniques have been proposed as a method of forming a capacitive element in the above-described flash memory formation. For example, it is described in JP-A Nos. 11-307745 and 10-004179. Less than,
Such a conventional technique will be described with reference to FIGS. 4 to 6. For clarity, in these figures, the lower layer electrodes to be compared with the present invention are shaded.
【０００４】図４は、第１の従来例として示す容量素子
の平面図（図４（ａ））とその断面図（図４（ｂ））で
ある。ここで、図４（ｂ）は図４（ａ）に記すＸ１−Ｘ
２で切断した断面図となっている。FIG. 4 is a plan view (FIG. 4A) and a cross-sectional view (FIG. 4B) of a capacitive element shown as a first conventional example. Here, FIG. 4B is X1-X shown in FIG.
It is a sectional view taken along line 2.
【０００５】図４に示すように、シリコン基板１００上
に素子分離絶縁膜１０１が形成され、この素子分離絶縁
膜１０１上にパターニングした下層電極１０２が形成さ
れる。ここで、下層電極１０２は不純物を含有する多結
晶シリコンで構成される。そして、この下層電極１０２
表面には容量絶縁膜１０３が設けられ、上記の下層電極
１０２および容量絶縁膜１０３を被覆するようにパター
ニングした上層電極１０４が積層して設けられる。ここ
で、上層電極１０４も不純物を含有する多結晶シリコン
で構成される。As shown in FIG. 4, an element isolation insulating film 101 is formed on a silicon substrate 100, and a patterned lower layer electrode 102 is formed on the element isolation insulating film 101. Here, the lower electrode 102 is composed of polycrystalline silicon containing impurities. Then, this lower layer electrode 102
A capacitive insulating film 103 is provided on the surface, and the lower electrode 102 and the upper electrode 104 patterned so as to cover the capacitive insulating film 103 are stacked. Here, the upper electrode 104 is also made of polycrystalline silicon containing impurities.
【０００６】そして、全面に層間絶縁膜１０５が化学気
相成長（ＣＶＤ）法による堆積さらには化学機械研磨
（ＣＭＰ）による表面平坦化を通して形成される。更
に、上記層間絶縁膜１０５の所定の領域に下層電極用コ
ンタクト孔１０６が形成される。同時に、図４（ａ）お
よび図４（ｂ）に示しているように上層電極用コンタク
ト孔１０７，１０７ａが複数個設けられる。ここで、特
徴的なことは、図４に示すように、上層電極用コンタク
ト孔１０７，１０７ａは、下層電極１０２上に位置する
領域に設けられることである。Then, an inter-layer insulating film 105 is formed on the entire surface by deposition by chemical vapor deposition (CVD) and further by surface planarization by chemical mechanical polishing (CMP). Further, a contact hole 106 for lower layer electrode is formed in a predetermined region of the interlayer insulating film 105. At the same time, as shown in FIGS. 4A and 4B, a plurality of upper electrode contact holes 107, 107a are provided. Here, what is characteristic is that, as shown in FIG. 4, the upper-layer electrode contact holes 107 and 107 a are provided in a region located on the lower-layer electrode 102.
【０００７】以後は、図示しないが、上記下層電極用コ
ンタクト孔１０６および上層電極用コンタクト孔１０
７，１０７ａ内にプラグが充填され、それぞれの配線に
電気接続される。このようにして容量素子が形成され
る。Thereafter, although not shown, the contact hole 106 for the lower layer electrode and the contact hole 10 for the upper layer electrode are formed.
7, 107a are filled with plugs and electrically connected to the respective wirings. In this way, the capacitive element is formed.
【０００８】図５は、第２の従来例として示す容量素子
の平面図（図５（ａ））とその断面図（図５（ｂ））で
ある。ここで、図５（ｂ）は図５（ａ）に記すＹ１−Ｙ
２で切断した断面図となっている。第１の従来例との大
きな相違は、第１の従来例で説明した上層電極の表面が
シリサイド化され低抵抗化される点である。そこで、こ
のシリサイド化について説明するために、図６に浮遊ゲ
ート型ＭＯＳトランジスタと通常のＭＯＳトランジスタ
の模式的な断面構造を示している。FIG. 5 is a plan view (FIG. 5 (a)) and a cross-sectional view (FIG. 5 (b)) of a capacitive element shown as a second conventional example. Here, FIG. 5B is Y1-Y shown in FIG.
It is a sectional view taken along line 2. A major difference from the first conventional example is that the surface of the upper electrode described in the first conventional example is silicidized to reduce the resistance. Therefore, in order to explain this silicidation, FIG. 6 shows a schematic cross-sectional structure of a floating gate type MOS transistor and an ordinary MOS transistor.
【０００９】図５に示すように、第１の従来例と同様に
シリコン基板２００上に素子分離絶縁膜２０１が形成さ
れ、パターニングした下層電極２０２が形成される。こ
こで、下層電極２０２は不純物を含有する多結晶シリコ
ンで構成され、図に示すようにその一部にシリサイド層
２０２ａが形成される。この下層電極２０２表面には容
量絶縁膜２０３が設けられ、上記の下層電極２０２およ
び容量絶縁膜２０３を被覆するようにパターニングした
多結晶シリコン層２０４とシリサイド層２０５が形成さ
れ、上層電極２０６が積層して設けられる。ここで、上
層電極２０６のパターンの端部にはサイドウォール絶縁
膜２０７が設けられている。このサイドウォール絶縁膜
２０７はシリコン酸化膜で構成される。また、同時に、
図５（ｂ）に示すように、下層電極２０２の端部に形成
されている多結晶シリコン層２０４の段差部にもサイド
ウォール絶縁膜２０８が形成されてしまう。上記のシリ
サイド層およびサイドウォール絶縁膜の形成について
は、図６で詳細に説明する。As shown in FIG. 5, similarly to the first conventional example, an element isolation insulating film 201 is formed on a silicon substrate 200, and a patterned lower electrode 202 is formed. Here, the lower layer electrode 202 is composed of polycrystalline silicon containing impurities, and a silicide layer 202a is formed on a part thereof as shown in the figure. A capacitive insulating film 203 is provided on the surface of the lower electrode 202, a polycrystalline silicon layer 204 and a silicide layer 205 which are patterned so as to cover the lower electrode 202 and the capacitive insulating film 203 are formed, and an upper electrode 206 is laminated. Is provided. Here, the sidewall insulating film 207 is provided at the end of the pattern of the upper layer electrode 206. The sidewall insulating film 207 is composed of a silicon oxide film. At the same time,
As shown in FIG. 5B, the sidewall insulating film 208 is also formed on the step portion of the polycrystalline silicon layer 204 formed on the end portion of the lower layer electrode 202. The formation of the silicide layer and the sidewall insulating film will be described in detail with reference to FIG.
【００１０】そして、第１の従来例で説明したのと同様
に、全面に層間絶縁膜２０９が形成される。更に、上記
層間絶縁膜２０９の所定の領域に下層電極用コンタクト
孔２１０が形成される。同時に、図５（ａ）および図５
（ｂ）に示しているように上層電極用コンタクト孔２１
１，２１１ａが複数個設けられる。ここで、特徴的なこ
とは、図５に示すように、上層電極用コンタクト孔２１
１，２１１ａは、下層電極２０２パターン上からはずれ
た位置に設けられることである。Then, as described in the first conventional example, an interlayer insulating film 209 is formed on the entire surface. Further, a lower layer electrode contact hole 210 is formed in a predetermined region of the interlayer insulating film 209. At the same time, FIG. 5 (a) and FIG.
As shown in (b), the contact hole 21 for the upper layer electrode
A plurality of 1,211a are provided. Here, as a characteristic feature, as shown in FIG.
Reference numerals 1 and 211a mean that they are provided at positions deviated from the lower layer electrode 202 pattern.
【００１１】以後は、第１の従来例と同様で、上記下層
電極用コンタクト孔２１０および上層電極用コンタクト
孔２１１，２１１ａ内にプラグが充填され、それぞれの
配線に電気接続される。このようにして容量素子が形成
される。Thereafter, similar to the first conventional example, plugs are filled in the contact holes 210 for the lower layer electrodes and the contact holes 211, 211a for the upper layer electrodes, and are electrically connected to the respective wirings. In this way, the capacitive element is formed.
【００１２】次に、上記シリサイド化について説明す
る。図６に浮遊ゲート型ＭＯＳトランジスタと通常のＭ
ＯＳトランジスタの模式的な断面構造を示している。図
５に示した容量素子は図６に示す浮遊ゲート型ＭＯＳト
ランジスタとＭＯＳトランジスタと共に同時にシリコン
基板上に形成される。Next, the silicidation will be described. Figure 6 shows a floating gate type MOS transistor and an ordinary M
1 shows a schematic cross-sectional structure of an OS transistor. The capacitive element shown in FIG. 5 is simultaneously formed on the silicon substrate together with the floating gate type MOS transistor and the MOS transistor shown in FIG.
【００１３】すなわち、シリコン基板２００上に素子分
離絶縁膜２０１が形成され、浮遊ゲート型ＭＯＳトラン
ジスタでは、トンネル酸化膜を介して浮遊ゲート電極２
１２が形成される。そして、電極間絶縁膜を挟んで多結
晶シリコン層２１３が形成され、その上にシリサイド層
２１４が形成される。この多結晶シリコン層２１３とシ
リサイド層２１４で制御ゲート電極２１５を構成する。
そして、浮遊ゲート電極２１２、制御ゲート電極２１５
の側壁にサイドウォール絶縁膜２１６が形成される構造
になる。更に、浮遊ゲート型ＭＯＳトランジスタのソー
ス／ドレイン領域になる拡散層２１７が形成され、拡散
層２１７上部にシリサイド層２１８が形成される。That is, the element isolation insulating film 201 is formed on the silicon substrate 200, and in the floating gate type MOS transistor, the floating gate electrode 2 is formed through the tunnel oxide film.
12 is formed. Then, a polycrystalline silicon layer 213 is formed sandwiching the inter-electrode insulating film, and a silicide layer 214 is formed thereon. The polycrystalline silicon layer 213 and the silicide layer 214 form a control gate electrode 215.
Then, the floating gate electrode 212 and the control gate electrode 215
The side wall insulating film 216 is formed on the side wall of the. Further, a diffusion layer 217 to be the source / drain region of the floating gate type MOS transistor is formed, and a silicide layer 218 is formed on the diffusion layer 217.
【００１４】同様に、ＭＯＳトランジスタでは、ゲート
絶縁膜２１９上に多結晶シリコン層２２０、その上部の
シリサイド層２２１でもってゲート電極２２２が形成さ
れる。そして、ゲート電極２２２の側壁にサイドウォー
ル絶縁膜２２３が形成される構造になる。更に、ＭＯＳ
トランジスタのソース／ドレイン領域になる拡散層２２
４が形成され、拡散層２２４上部にシリサイド層２２５
が形成される。Similarly, in the MOS transistor, the gate electrode 222 is formed by the polycrystalline silicon layer 220 on the gate insulating film 219 and the silicide layer 221 on the polycrystalline silicon layer 220. Then, the sidewall insulating film 223 is formed on the sidewall of the gate electrode 222. Furthermore, MOS
Diffusion layer 22 serving as source / drain region of transistor
4 is formed, and the silicide layer 225 is formed on the diffusion layer 224.
Is formed.
【００１５】そして、全面を被覆する層間絶縁膜２０９
の所定の領域に浮遊ゲート型ＭＯＳトランジスタのコン
タクト孔２２６、ＭＯＳトランジスタのコンタクト孔２
２７が形成される。Then, an interlayer insulating film 209 covering the entire surface
In a predetermined area of the floating gate type MOS transistor contact hole 226, MOS transistor contact hole 2
27 is formed.
【００１６】図５に示した容量素子の下層電極２０２は
浮遊ゲート型ＭＯＳトランジスタの浮遊ゲート電極２１
２と同一の多結晶シリコン膜で形成されている。そし
て、上層電極２０６を構成する多結晶シリコン層２０４
は、浮遊ゲート型ＭＯＳトランジスタの多結晶シリコン
層２１３、ＭＯＳトランジスタの多結晶シリコン層２２
０と同一の多結晶シリコン膜で形成されている。そし
て、シリサイド層２０５あるいは２０２ａは、浮遊ゲー
ト型ＭＯＳトランジスタの２１４，２１８およびＭＯＳ
トランジスタのシリサイド層２２１，２２５を形成する
サリサイド技術でもって同時に設けられる。このサリサ
イド技術では、サイドウォール絶縁膜２１６，２２３の
形成が必須である。このために、図５で示した上層電極
２０６パターンの端部、あるいは段差部にサイドウォー
ル絶縁膜２０７，２０８が必然的に形成されることにな
る。また、図５に示した容量素子の下層電極用コンタク
ト孔２１０、上層電極用コンタクト孔２１１，２１１ａ
は、浮遊ゲート型ＭＯＳトランジスタのコンタクト孔２
２６およびＭＯＳトランジスタのコンタクト孔２２７と
同一のエッチング工程でもって形成されることになる。The lower electrode 202 of the capacitance element shown in FIG. 5 is the floating gate electrode 21 of the floating gate type MOS transistor.
It is formed of the same polycrystalline silicon film as 2. Then, the polycrystalline silicon layer 204 that constitutes the upper electrode 206
Is a polycrystalline silicon layer 213 of the floating gate type MOS transistor and a polycrystalline silicon layer 22 of the MOS transistor.
It is formed of the same polycrystalline silicon film as 0. The silicide layer 205 or 202a is formed of the floating gate type MOS transistors 214 and 218 and the MOS.
It is provided at the same time by the salicide technique for forming the silicide layers 221 and 225 of the transistor. In this salicide technique, formation of the sidewall insulating films 216 and 223 is essential. Therefore, the sidewall insulating films 207 and 208 are inevitably formed at the end portion or the step portion of the upper electrode 206 pattern shown in FIG. In addition, the lower-layer electrode contact hole 210 and the upper-layer electrode contact holes 211 and 211a of the capacitive element shown in FIG.
Is the contact hole 2 of the floating gate type MOS transistor.
26 and the contact hole 227 of the MOS transistor are formed by the same etching process.
【００１７】[0017]
【発明が解決しようとする課題】上述した従来の技術で
は、それぞれ以下のような大きな問題点を有する。図４
で説明した第１の従来例では、容量素子の製造工程にお
いて、上層電極１０４と下層電極１０２間の絶縁性が劣
化する。この理由として以下のことが考えられる。第１
の従来例では、上層電極用コンタクト孔１０７，１０７
ａは、下層電極１０２上に位置する領域に設けられてい
る。そして、これらのコンタクト孔を形成後には、充填
するプラグとの接触抵抗を低減するために希フッ酸溶液
で自然酸化膜を除去する。しかし、この工程において、
上記希フッ酸が上層電極１０４を構成する多結晶シリコ
ン膜の結晶粒界に浸透しその下の容量絶縁膜１０３を腐
食するようになる。このようにして、上層電極用コンタ
クト孔１０７，１０７ａ下の領域にある容量絶縁膜の絶
縁性が低下する。The above-mentioned conventional techniques have the following major problems. Figure 4
In the first conventional example described above, the insulation between the upper layer electrode 104 and the lower layer electrode 102 deteriorates in the manufacturing process of the capacitive element. The following are possible reasons for this. First
In the conventional example of No. 1, the contact holes 107, 107 for the upper layer electrode
a is provided in a region located on the lower layer electrode 102. After forming these contact holes, the natural oxide film is removed with a dilute hydrofluoric acid solution in order to reduce the contact resistance with the plug to be filled. However, in this process,
The dilute hydrofluoric acid penetrates into the crystal grain boundaries of the polycrystalline silicon film forming the upper electrode 104 and corrodes the capacitive insulating film 103 thereunder. In this way, the insulating properties of the capacitive insulating film in the regions below the upper electrode contact holes 107 and 107a are reduced.
【００１８】また、図５で説明した第２の従来例では、
第１の従来例とは異なり、上層電極用コンタクト孔２１
１，２１１ａは、下層電極２０２パターン上からはずれ
た位置に設けられる。このために、第１の従来例のよう
な問題点は生じない。しかし、この場合には、上層電極
２０６を構成するシリサイド層２０５の形成において、
一部でシリサイド層が形成できず、上層電極２０６の低
抵抗化が損なわれるようになる。この理由は以下のよう
である。図５（ｂ）に示すように、多結晶シリコン層２
０４において、下層電極２０２パターンの端部で生じる
段差部に必然的にサイドウォール絶縁膜２０８ができ
る。このために、上述したサリサイド化の工程におい
て、このサイドウォール絶縁膜２９８で覆われる領域に
シリサイド層が形成できないようになるからである。こ
のような低抵抗化が阻害されると、このような容量素子
を用いたチャージポンプ回路の性能が大幅に低下する。Further, in the second conventional example described with reference to FIG.
Unlike the first conventional example, the upper-layer electrode contact hole 21
1, 211a are provided at positions deviated from above the lower layer electrode 202 pattern. For this reason, the problem as in the first conventional example does not occur. However, in this case, in the formation of the silicide layer 205 forming the upper electrode 206,
A silicide layer cannot be formed in part, and the lowering of the resistance of the upper electrode 206 is impaired. The reason for this is as follows. As shown in FIG. 5B, the polycrystalline silicon layer 2
In 04, the side wall insulating film 208 is inevitably formed on the step portion generated at the end portion of the lower layer electrode 202 pattern. Therefore, in the above-described salicide process, the silicide layer cannot be formed in the region covered with the sidewall insulating film 298. If such a reduction in resistance is hindered, the performance of the charge pump circuit using such a capacitive element is significantly reduced.
【００１９】本発明の目的は、容量素子のように絶縁膜
を挟んで形成した下層電極と上層電極間の絶縁性および
信頼性を向上させることにある。また、本発明の他の目
的は、上記上層電極あるいは下層電極の低抵抗化を高い
制御性の下にできるようにすることである。An object of the present invention is to improve the insulating property and reliability between a lower layer electrode and an upper layer electrode formed by sandwiching an insulating film like a capacitive element. Another object of the present invention is to make it possible to reduce the resistance of the upper electrode or the lower electrode with high controllability.
【００２０】[0020]
【課題を解決するための手段】このために本発明の半導
体装置では、半導体基板上に第１の電極と第２の電極と
が絶縁層を挟んでこの順に積層して形成され、前記第２
の電極を上層の配線層に接続するためのコンタクト孔
が、前記第１の電極から切り離して形成された分離領域
の上部に位置して設けられている。ここで、前記絶縁層
を挟んで形成された前記第１の電極と第２の電極は容量
素子の対向電極であり、前記絶縁層は容量素子の容量絶
縁膜である。To this end, in a semiconductor device of the present invention, a first electrode and a second electrode are formed on a semiconductor substrate by laminating an insulating layer in this order, and the second electrode is formed.
A contact hole for connecting the above electrode to the upper wiring layer is provided at an upper portion of a separation region formed by being separated from the first electrode. Here, the first electrode and the second electrode formed with the insulating layer sandwiched therebetween are counter electrodes of a capacitive element, and the insulating layer is a capacitive insulating film of the capacitive element.
【００２１】そして、前記分離領域は前記第１の電極パ
ターンの端部に形成されている。あるいは、前記分離領
域は前記第１の電極パターンの中央部に形成されてい
る。The separation region is formed at the end of the first electrode pattern. Alternatively, the isolation region is formed in the central portion of the first electrode pattern.
【００２２】また、前記第２の電極あるいは第１の電極
の表面にはシリサイド層が形成されている。あるいは、
前記第１の電極と前記分離領域との分離幅は、前記第２
の電極の膜厚の２倍以下になるように設定されている。A silicide layer is formed on the surface of the second electrode or the first electrode. Alternatively,
The separation width between the first electrode and the separation region is equal to the second width.
It is set so as to be less than twice the film thickness of the electrode.
【００２３】本発明では、上層電極である第２の電極用
のコンタクト孔が分離領域上に位置するように形成され
るために、上記絶縁層の電気特性が劣化しても、下層電
極である第１の電極との間の絶縁性は全く劣化しない。
本発明のような上層電極／下層電極の構造であると、第
１の従来例で説明した容量素子のように絶縁膜を挟んで
形成した下層電極と上層電極間の絶縁性および信頼性は
大幅に向上するようになる。In the present invention, since the contact hole for the second electrode, which is the upper layer electrode, is formed so as to be located on the isolation region, even if the electrical characteristics of the insulating layer are deteriorated, the lower layer electrode is formed. The insulation with the first electrode does not deteriorate at all.
With the structure of the upper layer electrode / lower layer electrode as in the present invention, the insulation and reliability between the lower layer electrode and the upper layer electrode formed by sandwiching the insulating film like the capacitive element described in the first conventional example are significantly improved. Will be improved.
【００２４】また、本発明では、上層電極である第２の
電極用のコンタクト孔が分離領域の上部に形成されるて
いるために、第２の従来例で述べた段差部でシリサイド
化のない領域は全く影響しない。このために、第２の従
来例で説明したのと異なり、上層電極の低抵抗化は高い
制御性の下にできる。Further, in the present invention, since the contact hole for the second electrode which is the upper layer electrode is formed in the upper part of the isolation region, there is no silicidation at the step portion described in the second conventional example. The area has no effect. Therefore, unlike the second conventional example, the resistance of the upper layer electrode can be lowered with high controllability.
【００２５】[0025]
【発明の実施の形態】次に、本発明の第１の実施の形態
について図１に基づいて説明する。図１は、容量素子の
平面図（図１（ａ））とその断面図（図１（ｂ））であ
る。ここで、図１（ｂ）は図１（ａ）に記すＡ１−Ａ２
で切断した断面図となっている。なお、本発明を明確に
するために、図１において下層電極３には斜線を施す。BEST MODE FOR CARRYING OUT THE INVENTION Next, a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a plan view (FIG. 1A) and a cross-sectional view (FIG. 1B) of the capacitive element. Here, FIG. 1B is a line A1-A2 shown in FIG.
It is a cross-sectional view cut at. In order to clarify the present invention, the lower layer electrode 3 is shaded in FIG.
【００２６】図１に示すように、シリコン基板１上に素
子分離絶縁膜２が形成され、パターニングした第１の電
極となる下層電極３とその一部にシリサイド層４が形成
される。そして、本発明では、分離領域３ａが上記下層
電極３から切り離して形成される。ここで、下層電極３
と分離領域３ａは、濃度が１０１９〜１０２０原子／ｃ
ｍ３ のリン不純物を含有する多結晶シリコン膜をそれ
ぞれにパターニングして形成されるものである。ここ
で、上記多結晶シリコン膜の膜厚は２００ｎｍ程度であ
る。As shown in FIG. 1, an element isolation insulating film 2 is formed on a silicon substrate 1, and a patterned lower layer electrode 3 serving as a first electrode and a silicide layer 4 are formed on a part thereof. In the present invention, the isolation region 3a is formed separately from the lower layer electrode 3. Here, the lower layer electrode 3
And the separation region 3a has a concentration of 10 19 to 10 20 atoms / c.
It is formed by patterning a polycrystalline silicon film containing m 3 phosphorus impurities. Here, the film thickness of the polycrystalline silicon film is about 200 nm.
【００２７】そして、下層電極３、分離領域３ａ表面に
は容量絶縁膜５が設けられる。ここで、容量絶縁膜５は
積層するシリコン酸化膜／シリコン窒化膜／シリコン酸
化膜（以下、ＯＮＯ）膜で構成され、その膜厚はシリコ
ン酸化膜換算で１５ｎｍ程度である。A capacitive insulating film 5 is provided on the surfaces of the lower electrode 3 and the isolation region 3a. Here, the capacitive insulating film 5 is composed of a stacked silicon oxide film / silicon nitride film / silicon oxide film (hereinafter, ONO) film, and its film thickness is about 15 nm in terms of silicon oxide film.
【００２８】そして、上記の下層電極３、分離領域３ａ
および容量絶縁膜５を被覆するようにパターニングした
多結晶シリコン層６とシリサイド層７が形成され、第２
の電極である上層電極８が積層して設けられる。ここ
で、多結晶シリコン層６は、下層電極３と分離領域３ａ
間を完全に埋め込むようにＣＶＤ法で堆積される。そこ
で、下層電極３と分離領域３ａとの分離幅は、多結晶シ
リコン層６の膜厚の２倍以下になるように設定される。
そして、上層電極８のパターンの端部、および分離領域
３ａの端部に形成されている多結晶シリコン層６の段部
にはサイドウォール絶縁膜９が設けられている。このサ
イドウォール絶縁膜９はシリコン酸化膜で構成される。Then, the lower layer electrode 3 and the isolation region 3a are formed.
And a polycrystalline silicon layer 6 and a silicide layer 7 which are patterned so as to cover the capacitor insulating film 5 are formed.
The upper layer electrode 8 which is the electrode of is laminated and provided. Here, the polycrystalline silicon layer 6 includes the lower electrode 3 and the isolation region 3a.
It is deposited by the CVD method so that the space is completely filled. Therefore, the separation width between the lower layer electrode 3 and the separation region 3a is set to be twice the film thickness of the polycrystalline silicon layer 6 or less.
A sidewall insulating film 9 is provided on the end of the pattern of the upper layer electrode 8 and the step of the polycrystalline silicon layer 6 formed at the end of the isolation region 3a. The sidewall insulating film 9 is composed of a silicon oxide film.
【００２９】このようにして、全面に層間絶縁膜１０が
形成され、層間絶縁膜１０の所定の領域に下層電極用コ
ンタクト孔１１が形成される。同時に、図１（ａ）およ
び図１（ｂ）に示しているように上層電極用コンタクト
孔１２，１２ａが複数個設けられる。ここで、特徴的な
ことは、図１に示すように、上層電極用コンタクト孔１
２，１２ａは、分離領域３ａパターン上に位置するとこ
ろに設けられることである。In this way, the interlayer insulating film 10 is formed on the entire surface, and the lower layer electrode contact hole 11 is formed in a predetermined region of the interlayer insulating film 10. At the same time, as shown in FIGS. 1A and 1B, a plurality of upper electrode contact holes 12 and 12a are provided. Here, as a characteristic, as shown in FIG.
2, 12a are to be provided on the pattern on the separation region 3a.
【００３０】以後は、従来の技術で説明したように、上
記下層電極用コンタクト孔１１および上層電極用コンタ
クト孔１２，１２ａ内にプラグが充填され、それぞれの
配線に電気接続される。このようにして本発明の容量素
子が形成される。After that, as described in the prior art, the lower electrode contact hole 11 and the upper electrode contact holes 12 and 12a are filled with plugs and electrically connected to the respective wirings. In this way, the capacitive element of the present invention is formed.
【００３１】本発明のような上層電極／下層電極の構造
であると、第１の従来例で説明した容量素子のように絶
縁膜を挟んで形成した下層電極と上層電極間の絶縁性お
よび信頼性は大幅に向上するようになる。これは、本発
明では、上層電極用コンタクト孔１２，１２ａが分離領
域３ａ上に位置するように形成されるために、第１の従
来例で説明したようにその表面の容量絶縁膜５の絶縁性
が劣化しても、下層電極３と上層電極８との間の絶縁性
は全く劣化しないからである。With the structure of the upper layer electrode / lower layer electrode as in the present invention, the insulation and reliability between the lower layer electrode and the upper layer electrode formed by sandwiching the insulating film as in the capacitive element described in the first conventional example. Sex will be greatly improved. This is because, in the present invention, the contact holes 12 and 12a for the upper layer electrode are formed so as to be located on the isolation region 3a, so that the insulation of the capacitive insulating film 5 on the surface thereof is performed as described in the first conventional example. This is because the insulation between the lower layer electrode 3 and the upper layer electrode 8 does not deteriorate at all even if the property deteriorates.
【００３２】また、本発明の構造であると、第２の従来
例で説明した上層電極８の低抵抗化は高い制御性の下に
できるようになる。これは、本発明では、第２の従来例
と異なり、上層電極用コンタクト孔１２，１２ａが上部
に形成されるているために、上述した段差部のシリサイ
ド化がない領域は全く影響しなくなるからである。Further, with the structure of the present invention, the lowering of the resistance of the upper layer electrode 8 described in the second conventional example can be performed under high controllability. This is because in the present invention, unlike the second conventional example, since the contact holes 12 and 12a for the upper layer electrode are formed in the upper part, the above-mentioned region where the silicidation is not exerted has no influence. Is.
【００３３】次に、本発明の第２の実施の形態について
図２に基づいて説明する。図２は、容量素子の平面図
（図２（ａ））とその断面図（図２（ｂ））である。こ
こで、図２（ｂ）は図２（ａ）に記すＢ１−Ｂ２で切断
した断面図となっている。第２の実施の形態は、第１の
実施の形態とは、下層電極、上層電極および分離領域の
配置関係を異にする。そこで、以下ではその異なるとこ
ろを主に説明する。また、第１の実施の形態で説明した
構造と同様なものは同一符号で説明する。Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a plan view (FIG. 2A) and a cross-sectional view (FIG. 2B) of the capacitive element. Here, FIG. 2B is a sectional view taken along line B1-B2 shown in FIG. The second embodiment is different from the first embodiment in the arrangement relationship of the lower layer electrode, the upper layer electrode, and the separation region. Therefore, the difference will be mainly described below. The same components as those described in the first embodiment will be described with the same reference numerals.
【００３４】図２に示すように、層間絶縁膜２上に設け
る分離領域３ａは、下層電極３の中心の領域に形成され
る。そして、容量絶縁膜５を挟んでその上に積層する上
部電極８が設けられる。そして、下層電極３上の下層電
極用コンタクト孔１１，１１ａと上層電極８上の上層電
極用コンタクト孔１２とが層間絶縁膜１０に設けられ
る。ここでも、上層電極用コンタクト孔１２は分離領域
３ａ上に位置するところに形成されることになる。他の
構造は第１の実施の形態と同じである。As shown in FIG. 2, the isolation region 3 a provided on the interlayer insulating film 2 is formed in the central region of the lower layer electrode 3. Then, the upper electrode 8 is provided to sandwich the capacitive insulating film 5 and to be stacked thereon. Then, the lower layer electrode contact holes 11 and 11 a on the lower layer electrode 3 and the upper layer electrode contact hole 12 on the upper layer electrode 8 are provided in the interlayer insulating film 10. In this case as well, the upper-layer electrode contact hole 12 is formed at a position located on the isolation region 3a. The other structure is the same as that of the first embodiment.
【００３５】第２の実施の形態では、第１の実施の形態
で説明したのと全く同様の効果が生じる。そして、この
場合には、その配置関係の相違から、下層電極３の面積
が第１の実施の形態の場合より増加するために、容量素
子の密度が向上するようになる。In the second embodiment, exactly the same effect as described in the first embodiment is obtained. In this case, the area of the lower layer electrode 3 is larger than that in the first embodiment due to the difference in the arrangement relationship, so that the density of the capacitive element is improved.
【００３６】次に、本発明の第３の実施の形態について
図３に基づいて説明する。図３は、フラッシュＥＥＰＲ
ＯＭセルの端部領域の平面図（図３（ａ））とその断面
図（図３（ｂ））である。ここで、図３（ｂ）は図３
（ａ）に記すＣ１−Ｃ２で切断した断面図となってい
る。この実施の形態は、容量素子とは異なり、上層電極
がメモリセルのワード線であり下層電極がダミー電極と
なる場合である。Next, a third embodiment of the present invention will be described with reference to FIG. Figure 3 shows flash EEPR
3A and 3B are a plan view (FIG. 3A) and a cross-sectional view (FIG. 3B) of an end region of the OM cell. Here, FIG. 3B is the same as FIG.
It is a sectional view taken along line C1-C2 shown in (a). This embodiment is different from the capacitive element in that the upper layer electrode is the word line of the memory cell and the lower layer electrode is the dummy electrode.
【００３７】図３に示すように、シリコン基板２１表面
に素子分離絶縁膜２２が選択的に形成され、トンネル酸
化膜を介して素子活性領域２３上に浮遊ゲート型ＭＯＳ
トランジスタの浮遊ゲート電極２４が配列されている。
同様に、セル領域の端部には、トンネル酸化膜を介して
素子活性領域２３ａ上にダミー電極２５が配列されてい
る。また、素子分離絶縁膜２２上にはダミー領域２５か
ら切り離されて分離領域２５ａが形成される。そして、
浮遊ゲート電極２４、ダミー電極２５、分離領域２５ａ
表面には容量絶縁膜２６が設けられる。ここで、容量絶
縁膜２６はＯＮＯ膜で構成され、その膜厚はシリコン酸
化膜換算で１５ｎｍ程度である。As shown in FIG. 3, a device isolation insulating film 22 is selectively formed on the surface of a silicon substrate 21, and a floating gate type MOS is formed on a device active region 23 via a tunnel oxide film.
The floating gate electrodes 24 of the transistors are arranged.
Similarly, at the end of the cell region, the dummy electrode 25 is arranged on the element active region 23a via the tunnel oxide film. Further, the isolation region 25a is formed on the element isolation insulating film 22 by being separated from the dummy region 25. And
Floating gate electrode 24, dummy electrode 25, isolation region 25a
A capacitive insulating film 26 is provided on the surface. Here, the capacitive insulating film 26 is composed of an ONO film, and its film thickness is about 15 nm in terms of silicon oxide film.
【００３８】そして、上記の容量絶縁膜２６を被覆する
ようにパターニングした多結晶シリコン層２７とシリサ
イド層２８の積層したワード線２９が配設される。この
ようにして、全面に層間絶縁膜３０が形成され、層間絶
縁膜３０の所定の領域にワード線用コンタクト孔３１が
形成される。ここでも、図３に示すように、ワード線用
コンタクト孔３１は、分離領域２５ａパターン上に位置
するところに設けられる。この実施の形態においても、
上記第１の実施の形態で説明したのと同様の効果が生じ
る。Then, a word line 29 in which a polycrystalline silicon layer 27 and a silicide layer 28, which are patterned so as to cover the capacitance insulating film 26, are laminated, is provided. In this way, the interlayer insulating film 30 is formed on the entire surface, and the word line contact hole 31 is formed in a predetermined region of the interlayer insulating film 30. Also here, as shown in FIG. 3, the word line contact hole 31 is provided at a position located on the isolation region 25a pattern. Also in this embodiment,
The same effect as described in the first embodiment can be obtained.
【００３９】本発明は、上記の実施の形態に限定され
ず、本発明の技術思想の範囲内において、実施の形態が
適宜変更され得る。The present invention is not limited to the above embodiment, and the embodiment can be appropriately modified within the scope of the technical idea of the present invention.
【００４０】[0040]
【発明の効果】以上に説明したように、本発明の半導体
装置では、半導体基板上に下層電極と上層電極とが絶縁
層を挟んでこの順に積層して形成され、上層電極をその
上の配線層に接続するためのコンタクト孔が、上記下層
電極から切り離して形成された分離領域の上部に位置し
て設けられている。そして、上記分離領域は下層電極パ
ターンの端部に形成される。あるいは、上記分離領域は
下層電極パターンの中央部に形成される。ここで、上記
下層電極と上記分離領域との分離幅は、上層電極の膜厚
の２倍以下になるように設定される。As described above, in the semiconductor device of the present invention, the lower electrode and the upper electrode are formed in this order on the semiconductor substrate with the insulating layer sandwiched therebetween, and the upper electrode is formed on the wiring above the electrode. A contact hole for connecting to the layer is provided at an upper portion of an isolation region formed separately from the lower layer electrode. Then, the isolation region is formed at the end of the lower electrode pattern. Alternatively, the isolation region is formed at the center of the lower layer electrode pattern. Here, the separation width between the lower layer electrode and the separation region is set to be twice the film thickness of the upper layer electrode or less.
【００４１】本発明のような上層電極／下層電極の構造
であると、容量素子のように絶縁膜を挟んで形成した下
層電極と上層電極間の絶縁性および信頼性は大幅に向上
するようになる。また、本発明では、上層電極である第
２の電極用のコンタクト孔が分離領域の上部に形成され
ているために、段差部のサイドウオール絶縁膜により生
じるシリサイド化のない領域は全く影響しなくなる。そ
して、従来の技術で説明したのと異なり、上層電極の低
抵抗化は高い制御性の下にできる。With the structure of the upper layer electrode / lower layer electrode as in the present invention, the insulating property and reliability between the lower layer electrode and the upper layer electrode formed by sandwiching an insulating film like a capacitive element are significantly improved. Become. Further, in the present invention, since the contact hole for the second electrode, which is the upper layer electrode, is formed in the upper portion of the isolation region, the region without silicidation caused by the sidewall insulating film at the step portion has no influence. . Further, unlike the description of the conventional technique, the resistance of the upper layer electrode can be lowered with high controllability.
【図１】本発明の第１の実施の形態を説明するための容
量素子の平面図と断面図である。1A and 1B are a plan view and a cross-sectional view of a capacitive element for explaining a first embodiment of the present invention.
【図２】本発明の第２の実施の形態を説明するための別
の容量素子の平面図と断面図である。FIG. 2 is a plan view and a cross-sectional view of another capacitive element for explaining the second embodiment of the present invention.
【図３】本発明の第３の実施の形態の説明するためのフ
ラッシュＥＥＰＲＯＭセル部の平面図と断面図である。3A and 3B are a plan view and a cross-sectional view of a flash EEPROM cell portion for explaining a third embodiment of the present invention.
【図４】第１の従来例の技術を説明するための容量素子
の平面図と断面図である。4A and 4B are a plan view and a cross-sectional view of a capacitive element for explaining a technique of a first conventional example.
【図５】第２の従来例の技術を説明するための容量素子
の平面図と断面図である。5A and 5B are a plan view and a cross-sectional view of a capacitive element for explaining a technique of a second conventional example.
【図６】第２の従来例の技術を説明するための浮遊ゲー
ト型ＭＯＳトランジスタとＭＯＳトランジスタの断面図
である。FIG. 6 is a sectional view of a floating gate type MOS transistor and a MOS transistor for explaining a technique of a second conventional example.
１，２１ シリコン基板 ２，２２ 素子分離絶縁膜 ３ 下層電極 ３ａ，２５ａ 分離領域 ４，７，２８ シリサイド層 ５，２６ 容量絶縁膜 ６，２７ 多結晶シリコン層 ８ 上層電極 ９ サイドウォール絶縁膜 １０，３０ 層間絶縁膜 １１，１１ａ 下層電極用コンタクト孔 １２，１２ａ 上層電極用コンタクト孔 ２３，２３ａ 素子活性領域 ２４ 浮遊ゲート電極 ２５ ダミー電極 ２９ ワード線 ３１ ワード線用コンタクト孔 1,21 Silicon substrate 2,22 Element isolation insulating film 3 Lower layer electrode 3a, 25a separation area 4,7,28 Silicide layer 5,26 Capacitive insulation film 6,27 Polycrystalline silicon layer 8 Upper layer electrode 9 Sidewall insulation film 10,30 Interlayer insulation film 11, 11a Contact hole for lower layer electrode 12, 12a Contact hole for upper layer electrode 23, 23a Device active region 24 Floating gate electrode 25 dummy electrode 29 word lines 31 Word line contact hole
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 29/788 29/792 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI theme code (reference) H01L 29/788 29/792
Claims (6)
とが絶縁層を挟んでこの順に積層して形成され、前記第
２の電極を上層の配線層に接続するためのコンタクト孔
が、前記第１の電極から切り離して形成された分離領域
の上部に位置して設けられていることを特徴とする半導
体装置。1. A contact hole for connecting a first electrode and a second electrode to an upper wiring layer by laminating a first electrode and a second electrode in this order on both sides of an insulating layer. Is provided at a position above an isolation region formed separately from the first electrode.
の電極と第２の電極は容量素子の対向電極であり、前記
絶縁層は容量素子の容量絶縁膜であることを特徴とする
請求項１記載の半導体装置。2. The first portion formed with the insulating layer sandwiched therebetween.
2. The semiconductor device according to claim 1, wherein the electrode and the second electrode are counter electrodes of a capacitive element, and the insulating layer is a capacitive insulating film of the capacitive element.
の端部に形成されていることを特徴とする請求項１また
は請求項２記載の半導体装置。3. The semiconductor device according to claim 1, wherein the isolation region is formed at an end of the first electrode pattern.
の中央部に形成されていることを特徴とする請求項１ま
たは請求項２記載の半導体装置。4. The semiconductor device according to claim 1, wherein the isolation region is formed in a central portion of the first electrode pattern.
面にはシリサイド層が形成されていることを特徴とする
請求項１から請求項４のうち１つの請求項に記載の半導
体装置。5. The semiconductor device according to claim 1, wherein a silicide layer is formed on the surface of the second electrode or the first electrode.
幅は、前記第２の電極の膜厚の２倍以下になるように設
定されていることを特徴とする請求項１から請求項５の
うち１つの請求項に記載の半導体装置。6. The separation width between the first electrode and the separation region is set to be not more than twice the film thickness of the second electrode. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001294906A JP2003100887A (en) | 2001-09-26 | 2001-09-26 | Semiconductor device and method of manufacturing the same |
| US10/254,399 US6583492B2 (en) | 2001-09-26 | 2002-09-25 | Capacitor element having a contact hole structure in an electrode structure |
| KR10-2002-0058055A KR100447823B1 (en) | 2001-09-26 | 2002-09-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001294906A JP2003100887A (en) | 2001-09-26 | 2001-09-26 | Semiconductor device and method of manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003100887A true JP2003100887A (en) | 2003-04-04 |
Family
ID=19116423
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001294906A Pending JP2003100887A (en) | 2001-09-26 | 2001-09-26 | Semiconductor device and method of manufacturing the same |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6583492B2 (en) |
| JP (1) | JP2003100887A (en) |
| KR (1) | KR100447823B1 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7445989B2 (en) | 2004-10-29 | 2008-11-04 | Fujitsu Limited | Semiconductor device and method of manufacturing the same |
| JP2009094204A (en) * | 2007-10-05 | 2009-04-30 | Renesas Technology Corp | Semiconductor device and method of manufacturing the same |
| JP2010177688A (en) * | 2010-03-29 | 2010-08-12 | Renesas Electronics Corp | Semiconductor device |
| JP2010192922A (en) * | 2010-04-19 | 2010-09-02 | Fujitsu Semiconductor Ltd | Method for manufacturing semiconductor device |
| US8084800B2 (en) | 2007-10-15 | 2011-12-27 | Renesas Electronics Corporation | Semiconductor device and a method of manufacturing the same |
| JP2017108168A (en) * | 2011-06-01 | 2017-06-15 | 株式会社半導体エネルギー研究所 | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3947135B2 (en) * | 2003-05-30 | 2007-07-18 | 株式会社東芝 | Nonvolatile semiconductor memory device |
| KR200452337Y1 (en) * | 2010-08-09 | 2011-02-17 | 이재붕 | A type safety fence |
| TWI721026B (en) * | 2015-10-30 | 2021-03-11 | 日商半導體能源研究所股份有限公司 | Method for forming capacitor, semiconductor device, module, and electronic device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE470415B (en) * | 1992-07-06 | 1994-02-14 | Ericsson Telefon Ab L M | High capacitor capacitor in an integrated function block or integrated circuit, method of producing the capacitor and using the capacitor as an integrated decoupling capacitor |
| JP3719618B2 (en) | 1996-06-17 | 2005-11-24 | 松下電器産業株式会社 | Semiconductor device and manufacturing method thereof |
| US6177716B1 (en) * | 1997-01-02 | 2001-01-23 | Texas Instruments Incorporated | Low loss capacitor structure |
| KR100302188B1 (en) | 1998-04-21 | 2001-11-22 | 윤종용 | Method for fabricating non-volatile semiconductor device |
| JP3276351B2 (en) * | 1999-12-13 | 2002-04-22 | 松下電器産業株式会社 | Method for manufacturing semiconductor device |
| JP2001284526A (en) * | 2000-03-28 | 2001-10-12 | Nec Yamagata Ltd | Mim capacitor for semiconductor integrated circuit |
-
2001
- 2001-09-26 JP JP2001294906A patent/JP2003100887A/en active Pending
-
2002
- 2002-09-25 KR KR10-2002-0058055A patent/KR100447823B1/en not_active IP Right Cessation
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8169017B2 (en) | 2004-10-29 | 2012-05-01 | Fujitsu Semiconductor Limited | Semiconductor device and method of manufacturing the same |
| US7445989B2 (en) | 2004-10-29 | 2008-11-04 | Fujitsu Limited | Semiconductor device and method of manufacturing the same |
| JP2009094204A (en) * | 2007-10-05 | 2009-04-30 | Renesas Technology Corp | Semiconductor device and method of manufacturing the same |
| US9461105B2 (en) | 2007-10-15 | 2016-10-04 | Renesas Electronics Corporation | Semiconductor device and a method of manufacturing the same |
| US8084800B2 (en) | 2007-10-15 | 2011-12-27 | Renesas Electronics Corporation | Semiconductor device and a method of manufacturing the same |
| US8258561B2 (en) | 2007-10-15 | 2012-09-04 | Renesas Electronics Corporation | Semiconductor device and a method of manufacturing the same |
| US8431978B2 (en) | 2007-10-15 | 2013-04-30 | Renesas Electronics Corporation | Semiconductor device and a method of manufacturing the same |
| US8975678B2 (en) | 2007-10-15 | 2015-03-10 | Renesas Electronics Corporation | Semiconductor device and a method of manufacturing the same |
| US9755012B2 (en) | 2007-10-15 | 2017-09-05 | Renesas Electronics Corporation | Semiconductor device and a method of manufacturing the same |
| JP2010177688A (en) * | 2010-03-29 | 2010-08-12 | Renesas Electronics Corp | Semiconductor device |
| JP2010192922A (en) * | 2010-04-19 | 2010-09-02 | Fujitsu Semiconductor Ltd | Method for manufacturing semiconductor device |
| JP2017108168A (en) * | 2011-06-01 | 2017-06-15 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| US10504920B2 (en) | 2011-06-01 | 2019-12-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| US6583492B2 (en) | 2003-06-24 |
| KR100447823B1 (en) | 2004-09-08 |
| US20030057466A1 (en) | 2003-03-27 |
| KR20030027721A (en) | 2003-04-07 |
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