JPH0147012B2 - - Google Patents
Info
- Publication number
- JPH0147012B2 JPH0147012B2 JP54137749A JP13774979A JPH0147012B2 JP H0147012 B2 JPH0147012 B2 JP H0147012B2 JP 54137749 A JP54137749 A JP 54137749A JP 13774979 A JP13774979 A JP 13774979A JP H0147012 B2 JPH0147012 B2 JP H0147012B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon
- melting point
- point metal
- vapor deposition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 61
- 229910052710 silicon Inorganic materials 0.000 claims description 61
- 239000010703 silicon Substances 0.000 claims description 61
- 239000000758 substrate Substances 0.000 claims description 23
- 238000002844 melting Methods 0.000 claims description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 230000008018 melting Effects 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 13
- 229910021332 silicide Inorganic materials 0.000 claims description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 13
- 238000007740 vapor deposition Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 229910016006 MoSi Inorganic materials 0.000 description 17
- 238000001704 evaporation Methods 0.000 description 9
- 230000008020 evaporation Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- -1 arsenic ions Chemical class 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
Description
【発明の詳細な説明】
この発明は、高融点金属の硅化物膜を主体とす
る電極配線を有する半導体装置の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device having electrode wiring mainly made of a silicide film of a high melting point metal.
従来より、半導体装置の電極配線にはAl膜や
多結晶シリコン膜が広く用いられている。Al膜
は比抵抗が小さく、シリコン基板とのコンタクト
も良好であるため最も多用されているが、融点が
低いために高温処理工程が全て終了した後でなけ
れば用いられないという制約がある。従つて
MOSデバイスを自己整合法で作る場合や多層配
線構造の集積回路を作る場合には多結晶シリコン
膜が用いられる。ところが、多結晶シリコン膜
は、不純物を高濃度にドープしたとしてもAl膜
に比べると比抵抗がはるかに高く、高速動作化に
は不向きであるという難点がある。 Conventionally, Al films and polycrystalline silicon films have been widely used for electrode wiring of semiconductor devices. Al film is the most commonly used because it has a low resistivity and good contact with the silicon substrate, but its low melting point means that it can only be used after all high-temperature treatment steps have been completed. accordingly
Polycrystalline silicon films are used when making MOS devices using the self-alignment method or when making integrated circuits with multilayer wiring structures. However, even when doped with impurities at a high concentration, polycrystalline silicon films have a much higher resistivity than Al films, making them unsuitable for high-speed operation.
そこで最近は、電極配線としてMoSi2膜のよう
な高融点金属の硅化膜を用いる方法が注目されて
いる。MoSi2膜は高温処理に耐え得るから、
MOSデバイスの自己整合法にも適用でき、多層
配線構造を得るにも都合がよく、また比抵抗が多
結晶シリコン膜に比べて十分低い、といつた特徴
を備えている。 Therefore, recently, a method of using a high-melting point metal silicide film such as MoSi 2 film as the electrode wiring has been attracting attention. Because MoSi 2 film can withstand high temperature treatment,
It can also be applied to self-alignment methods for MOS devices, is convenient for obtaining multilayer wiring structures, and has characteristics such as a sufficiently low resistivity compared to polycrystalline silicon films.
しかしながら、MoSi2膜からなる電極配線は、
特に高温処理を経た後においては、シリコン基板
とのオーミツクコンタクトや密着性の点でAl膜
や多結晶シリコン膜に劣るという欠点がある。一
般に半導体基板と電極配線のオーミツクコンタク
ト不良は、半導体基板を大気中に放置することに
よりその表面に自然に形成される酸化膜が原因と
なることが多い。例えばシリコン基板を大気中に
たかだか数分放置することによりその表面には20
〜30Åのシリコン酸化膜が形成され、この酸化膜
がMoSi2膜からなる電極配線を形成した場合に良
好なオーミツクコンタクトによつて必要なシリコ
ンとMoSi2との反応を妨げることになる。 However, the electrode wiring made of MoSi 2 film is
Particularly after high-temperature treatment, it has the disadvantage of being inferior to Al films and polycrystalline silicon films in terms of ohmic contact and adhesion with silicon substrates. Generally, poor ohmic contact between a semiconductor substrate and electrode wiring is often caused by an oxide film that naturally forms on the surface of the semiconductor substrate when it is left in the atmosphere. For example, if a silicon substrate is left in the atmosphere for a few minutes at most, the surface of the silicon substrate will be 20%
A silicon oxide film with a thickness of ~30 Å is formed, and this oxide film prevents the necessary reaction between silicon and MoSi 2 by providing good ohmic contact when forming an electrode wiring made of a MoSi 2 film.
この発明は上記した点に鑑み、シリコン基板ま
たはその上に絶縁膜を介して設けられた多結晶シ
リコン膜に対して良好なオーミツクコンタクトを
し、かつ密着性にも優れた高融点金属の硅化物膜
を主体とする電極配線を形成することを可能とし
た半導体装置の製造方法を提供するものである。 In view of the above-mentioned points, the present invention has been developed by using a high-melting point metal silicide that has good ohmic contact with a silicon substrate or a polycrystalline silicon film provided thereon via an insulating film, and has excellent adhesion. The present invention provides a method for manufacturing a semiconductor device that makes it possible to form electrode wiring mainly made of a material film.
この発明においては、シリコン基板またはその
上に絶縁膜を介して設けられた多結晶シリコン膜
にコンタクトする電極配線を、シリコン膜と高融
点金属の硅化物膜をシリコン膜表面を大気にさら
すことなくこの順に連続的に被着し、得られた積
層膜を選択エツチングして形成することを骨子と
する。 In this invention, the electrode wiring that contacts the silicon substrate or the polycrystalline silicon film provided on the silicon substrate via the insulating film can be connected to the silicon film and the high melting point metal silicide film without exposing the silicon film surface to the atmosphere. The main idea is to deposit the layers successively in this order and then selectively etching the resulting laminated film.
具体的には例えば、一つの蒸着装置にシリコン
と高融点金属の蒸着源を別々に設けておき、コン
タクトホールが形成されたシリコン基板をこの蒸
着装置に装着し、まずシリコンの蒸着を所定時間
行い、その後シリコンの蒸着を続行しながら同時
に高融点金属の蒸着を行うことにより、シリコン
膜と高融点金属の硅化物膜の積層膜を形成する。
このようにすれば、シリコン基板と高融点金属の
硅化物膜との間にシリコン膜が介在することにな
る。従つて、シリコン基板表面に20〜30Åのシリ
コン酸化膜があつたとしても、これはシリコン基
板とシリコン膜の同種半導体間に挟まれているた
め、熱処理によつてシリコン膜の結晶粒塊に容易
に取り込まれる結果、良好なオーミツクコンタク
トがとれる。勿論シリコン膜と高融点金属の硅化
物膜との間には、連続蒸着を行うから全く酸化膜
が介在することはない。 Specifically, for example, a single evaporation device is provided with separate evaporation sources for silicon and a high-melting point metal, a silicon substrate with a contact hole formed therein is mounted on this evaporation device, and silicon is first evaporated for a predetermined period of time. Then, while continuing the silicon vapor deposition, a high melting point metal is simultaneously vapor deposited to form a laminated film of a silicon film and a high melting point metal silicide film.
In this way, a silicon film is interposed between the silicon substrate and the high melting point metal silicide film. Therefore, even if there is a silicon oxide film of 20 to 30 Å on the surface of the silicon substrate, since it is sandwiched between the silicon substrate and the silicon film, which are the same type of semiconductor, it is easily converted into crystal grain agglomerates of the silicon film by heat treatment. As a result, good ohmic contact can be made. Of course, there is no oxide film between the silicon film and the high melting point metal silicide film since continuous vapor deposition is performed.
以下この発明をMOS集積回路に適用した実施
例につき図面を参照して説明する。第１図はＤ型
負荷MOSトランジスタQ1とＥ型ドライバMOSト
ランジスタQ2を組合せたＥ／DMOSインバータ
の等価回路であり、第２図ａ〜ｆはその負荷
MOSトランジスタQ1の部分の製造工程図であ
る。まずＰ型シリコン基板１に厚いフイールド酸
化膜２を形成し、これを選択エツチングして素子
形成領域に薄いゲート酸化膜３を形成する(a)。次
にイオン注入により所定のしきい値が得られるよ
うにゲート酸化膜３下の不純物濃度を制御した
後、ゲート酸化膜３のソース形成領域の一部をエ
ツチング除去し、ヒ素をイオン注入してN2ガス
中で1000℃、30分の熱処理を行つてn+型層４を
形成する(b)。この後、真空蒸着法によりシリコン
膜５とMoSi2膜６を連続的に被着する(c)。このと
き、シリコン膜５とMoSi2膜６の間に酸化膜等の
バリアが形成されないように、シリコン膜５の表
面を大気にさらすことなくその上にMoSi2膜６を
被着することが重要である。これは例えば、一つ
の蒸着装置にシリコンとMoの蒸着源を別々に設
けたものを用い、まずシリコンを蒸着速度10Å／
秒程度で約100秒蒸着した後、シリコンの蒸着を
続けながらMoを蒸着速度3.9Å／秒程度で約300
秒蒸着を行うことで可能である。これにより約
1000Åのシリコン膜５と約3000ÅのMoSi2膜６の
積層膜が得られ、これをN2ガス中で約1000℃、
30分の熱処理をして層抵抗を約２Ω／ロにする。
その後、この積層膜を選択エツチングして、ゲー
ト電極とこれから連続的に素子領域の外を通つて
n+型層４にダイレクトコンタクトする電極配線
を一体的に形成する(d)。この状態の平面パターン
は模式的に示すと第３図の如くなる。この積層膜
のエツチングにはCF4−O2を用いたガスプラズマ
エツチング法やリアクテイブイオンエツチング法
が望ましいが、弗酸と硝酸の混合液を用いてもよ
い。この後、電極パターンをマスクとしてゲート
酸化膜３をエツチングし、ヒ素イオン注入を行つ
てn+型のドレイン７、ソース８を形成する(e)。
先に電極配線をコンタクトさせるために設けた
n+型層４はソース８と一体化し、ソースの一部
となる。その後、CDV法により全面にシリコン
酸化膜９を被着し、N2ガス中で1000℃、30分の
熱処理をしてドレイン７、ソース８の活性化を行
い、コンタクトホールをあけて、ドレイン７を電
源端に導くAl配線１０をはじめとする配線を施
して完成する(f)。 Embodiments in which the present invention is applied to a MOS integrated circuit will be described below with reference to the drawings. Figure 1 is an equivalent circuit of an E/DMOS inverter that combines a D-type load MOS transistor Q 1 and an E-type driver MOS transistor Q 2 , and Figure 2 a to f show its load.
FIG. 3 is a manufacturing process diagram of a portion of MOS transistor Q1 . First, a thick field oxide film 2 is formed on a P-type silicon substrate 1, and this is selectively etched to form a thin gate oxide film 3 in the element formation region (a). Next, after controlling the impurity concentration under the gate oxide film 3 to obtain a predetermined threshold value by ion implantation, a part of the source formation region of the gate oxide film 3 is removed by etching, and arsenic ions are implanted. A heat treatment is performed at 1000° C. for 30 minutes in N 2 gas to form an n + type layer 4 (b). Thereafter, a silicon film 5 and a MoSi 2 film 6 are successively deposited by vacuum evaporation (c). At this time, it is important to deposit the MoSi 2 film 6 on the surface of the silicon film 5 without exposing it to the atmosphere so that a barrier such as an oxide film is not formed between the silicon film 5 and the MoSi 2 film 6. It is. For example, this can be done by using a single evaporator with separate silicon and Mo evaporation sources, and first depositing silicon at a rate of 10 Å/1.
After evaporating for approximately 100 seconds, while continuing to deposit silicon, Mo was deposited at a rate of approximately 3.9 Å/sec for approximately 300 Å/sec.
This is possible by performing second evaporation. This results in approx.
A laminated film of a silicon film 5 of 1000 Å and a MoSi 2 film 6 of about 3000 Å was obtained, which was heated at about 1000°C in N 2 gas.
Heat treatment for 30 minutes to reduce the layer resistance to approximately 2Ω/ro.
After that, this laminated film is selectively etched so that the gate electrode and the gate electrode are continuously etched through the outside of the device area.
Electrode wiring in direct contact with the n + type layer 4 is integrally formed (d). The planar pattern in this state is schematically shown in FIG. For etching this laminated film, a gas plasma etching method using CF 4 --O 2 or a reactive ion etching method is preferable, but a mixed solution of hydrofluoric acid and nitric acid may also be used. Thereafter, the gate oxide film 3 is etched using the electrode pattern as a mask, and arsenic ions are implanted to form an n + type drain 7 and source 8 (e).
It was provided first to make contact with the electrode wiring.
The n + type layer 4 is integrated with the source 8 and becomes part of the source. After that, a silicon oxide film 9 is deposited on the entire surface by the CDV method, and heat treatment is performed at 1000°C for 30 minutes in N 2 gas to activate the drain 7 and source 8. A contact hole is made and the drain 7 Complete wiring including Al wiring 10 leading to the power supply terminal (f).
この実施例によれば、ソース領域のn+型層４
に直接コンタクトするゲート電極配線をシリコン
膜５とMoSi2膜６の連続蒸着法により形成してお
り、シリコン膜５とMoSi2膜６の間には酸化膜等
のバリアが介在することはなく、またシリコン膜
５とn+型層４の間には自然に形成される薄い酸
化膜が介在したとしてもこれは後の熱工程で簡単
に消失する結果、ゲート電極配線とn+型層４と
の間には良好なオーミツクコンタクトとなり、ま
たゲート電極配線の密着性も優れたものとなる。 According to this embodiment, the n + type layer 4 of the source region
The gate electrode wiring that is in direct contact with the silicon film 5 and the MoSi 2 film 6 is formed by a continuous vapor deposition method, and there is no barrier such as an oxide film between the silicon film 5 and the MoSi 2 film 6. Furthermore, even if a naturally formed thin oxide film is interposed between the silicon film 5 and the n + type layer 4, this will easily disappear during the subsequent thermal process, so that the gate electrode wiring and the n + type layer 4 Good ohmic contact is made between the two, and the adhesion of the gate electrode wiring is also excellent.
上記実施例は、シリコン基板に直接コンタクト
する電極配線を形成するものであつたが、基板上
に絶縁膜を介して設けられた多結晶シリコン膜に
コンタクトする電極配線を形成する場合にもこの
発明は有用である。その実施例を第４図ａ−ｇに
より次に説明する。なお、先の実施例と対応する
部分には同一符号を付して詳細な説明は省く。ま
ず、第４図ａの構造を得、同図ｂのようにゲート
酸化膜３の一部をエツチング除去するところまで
は先の実施例と同じである。この後、ヒ素をドー
プした多結晶シリコン膜１１を全面に被着し、熱
処理をしてヒ素を基板１中に拡散させてn+型層
４を形成する(c)。この後は先の実施例と同様、シ
リコン膜５とMoSi2膜６を連続蒸着法により形成
し(d)、得られた多結晶シリコン膜１１とシリコン
膜５とMoSi2膜６からなる積層膜をパターニング
してゲート電極配線を形成し(e)、ゲート酸化膜３
を除去してソース７、ドレイン８を形成し(f)、
CVD法によるシリコン酸化膜９でおおつてコン
タクトホールをあけてAl配線１０を施して完成
する(g)。 In the above embodiment, the electrode wiring is formed in direct contact with a silicon substrate, but the present invention can also be applied when forming an electrode wiring in contact with a polycrystalline silicon film provided on a substrate via an insulating film. is useful. An embodiment thereof will now be described with reference to FIGS. 4a-g. Note that the same reference numerals are given to parts corresponding to those in the previous embodiment, and detailed description thereof will be omitted. First, the structure shown in FIG. 4a is obtained, and the steps up to the point where a part of the gate oxide film 3 is etched away as shown in FIG. 4b are the same as in the previous embodiment. Thereafter, a polycrystalline silicon film 11 doped with arsenic is deposited on the entire surface, and heat treatment is performed to diffuse arsenic into the substrate 1 to form an n + type layer 4 (c). After this, as in the previous example, a silicon film 5 and a MoSi 2 film 6 are formed by continuous vapor deposition (d), and the resulting laminated film consisting of the polycrystalline silicon film 11, the silicon film 5, and the MoSi 2 film 6 is formed. is patterned to form gate electrode wiring (e), and gate oxide film 3 is formed.
is removed to form a source 7 and a drain 8 (f),
It is completed by covering with a silicon oxide film 9 by CVD method, making a contact hole and applying Al wiring 10 (g).
この実施例によつても、先の実施例と同様の理
由でシリコン膜５とMoSi2膜６の積層膜が多結晶
シリコン膜１１に対して良好なオーミツクコンタ
クトと密着性を示し、また多結晶シリコン膜１１
も基板１に対して良好なオーミツクコンタクトと
密着性を示し、かつ多結晶シリコン膜１１とシリ
コン膜５も同じシリコンどうしなので良好なコン
タクトが得られる結果、優れた特性の電極配線が
形成される。この実施例では、多結晶シリコン膜
１１とシリコン膜５とMoSi2膜６の三層構造を一
体的にパターニングして電極配線としたが、シリ
コン膜５とMoSi2膜６からなる積層膜による電極
配線パターンをその下の多結晶シリコン膜１１の
パターンと異ならせてもよい。具体的には、多結
晶シリコン膜１１により第１層電極配線を形成
し、これに対しシリコン膜５とMoSi2膜６の積層
膜からなる第２層電極配線をコンタクトさせる場
合にも、この発明は有用である。 In this embodiment as well, the laminated film of the silicon film 5 and the MoSi 2 film 6 exhibits good ohmic contact and adhesion to the polycrystalline silicon film 11 for the same reason as in the previous embodiment. Crystalline silicon film 11
The polycrystalline silicon film 11 and the silicon film 5 also exhibit good ohmic contact and adhesion to the substrate 1, and since the polycrystalline silicon film 11 and the silicon film 5 are made of the same silicon, good contact is obtained, and as a result, electrode wiring with excellent characteristics is formed. . In this embodiment, the three-layer structure of the polycrystalline silicon film 11, the silicon film 5, and the MoSi 2 film 6 was integrally patterned to form the electrode wiring. The wiring pattern may be different from the pattern of the polycrystalline silicon film 11 underneath. Specifically, the present invention can also be applied when a first layer electrode wiring is formed of a polycrystalline silicon film 11 and a second layer electrode wiring made of a laminated film of a silicon film 5 and a MoSi 2 film 6 is brought into contact therewith. is useful.
また、以上の実施例では、シリコンとMoを
別々の蒸着源として備えた蒸着装置による連続蒸
着法を説明したが、スパツタ法によつても同様の
積層膜が得られるし、或いはSiH4とMoCl3等を
用いたCVD法によつて同様の積層膜を形成する
こともできる。 Furthermore, in the above embodiments, a continuous evaporation method using a evaporation apparatus equipped with silicon and Mo as separate evaporation sources was explained, but a similar laminated film can also be obtained by sputtering, or SiH 4 and MoCl A similar laminated film can also be formed by a CVD method using No. 3 or the like.
また、シリコン膜には必要に応じて不純物をド
ープしてもよい。 Further, the silicon film may be doped with impurities as necessary.
更に高融点金属としてはMoの他、Ｗ、Ti、
Ta、Nb、Pt等を用いることも可能である。 In addition to Mo, high melting point metals include W, Ti,
It is also possible to use Ta, Nb, Pt, etc.
以上説明したように、この発明によれば、シリ
コン膜と高融点金属の硅化物膜をシリコン膜表面
が大気にさらされないように連続的に被着するこ
とによつて、オーミツクコンタクト性、密着性に
優れた電極配線を形成することができる。またこ
の発明の方法により得られる電極配線は高融点金
属の硅化物膜を主体とするため多結晶シリコン膜
を用いたものに比べて比抵抗が約１桁小さくな
り、回路の高速動作にとつて好ましい。しかも電
極配線の下層にはシリコン膜があり、MOSトラ
ンジスタのゲート電極として用いる場合には従来
の多結晶シリコンゲートの場合とほゞ同じしきい
値が得られるため、回路設計が容易であるという
利点も有する。 As explained above, according to the present invention, by continuously depositing a silicon film and a high-melting point metal silicide film so that the surface of the silicon film is not exposed to the atmosphere, ohmic contact and adhesion can be achieved. Electrode wiring with excellent properties can be formed. Furthermore, since the electrode wiring obtained by the method of the present invention is mainly made of a silicide film of a high-melting point metal, the resistivity is approximately one order of magnitude lower than that using a polycrystalline silicon film, making it suitable for high-speed operation of circuits. preferable. Furthermore, since there is a silicon film in the lower layer of the electrode wiring, when used as a gate electrode of a MOS transistor, the threshold value is almost the same as that of a conventional polycrystalline silicon gate, so circuit design is easy. It also has
第１図はＥ／Ｄ MOSインバータの等価回路
図、第２図ａ〜ｆは第１図の負荷MOSトランジ
スタ部分にこの発明を適用した実施例の製造工程
断面図、第３図は第２図ｄの模式的平面パター
ン、第４図ａ〜ｇは別の実施例の製造工程断面図
である。
１…Ｐ型シリコン基板、２…フイールド酸化
膜、３…ゲート酸化膜、４…n+型層、５…シリ
コン膜、６…MoSi2膜、７…n+型ドレイン、８…
n+型ソース、９…シリコン酸化膜、１０…Al配
線、１１…多結晶シリコン膜。
Figure 1 is an equivalent circuit diagram of an E/D MOS inverter, Figures 2 a to f are cross-sectional views of the manufacturing process of an embodiment in which the present invention is applied to the load MOS transistor portion of Figure 1, and Figure 3 is a diagram of Figure 2. d is a schematic planar pattern, and FIGS. 4a to 4g are sectional views showing the manufacturing process of another embodiment. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Field oxide film, 3... Gate oxide film, 4... N + type layer, 5... Silicon film, 6... MoSi 2 film, 7... N + type drain, 8...
n + type source, 9... silicon oxide film, 10... Al wiring, 11... polycrystalline silicon film.
Claims (1)
する半導体装置を製造するに際し、前記電極配線
を、シリコン膜を被着した後その表面を大気にさ
らすことなく高融点金属の硅化物膜を連続的に被
着し、得られた積層膜の熱処理を行なうことによ
り形成し、この熱処理で前記シリコン基板と前記
積層膜との間の自然酸化膜を消失させることを特
徴とする半導体装置の製造方法。 ２ シリコン膜と高融点金属の硅化物膜を連続的
に被着する工程は、一つの蒸着装置にシリコンと
高融点金属の蒸着源を別々に設け、シリコンの蒸
着を所定時間行なつた後、これを続行しながら同
時に高融点金属の蒸着を行うものである特許請求
の範囲第１項記載の半導体装置の製造方法。 ３ シリコン基板に多結晶シリコン膜を介してコ
ンタクトする電極配線を有する半導体装置を製造
するに際し、前記電極配線を、シリコン膜を被着
した後その表面を大気にさらすことなく高融点金
属の硅化物膜を連続的に被着し、得られた積層膜
の熱処理を行なうことにより形成し、この熱処理
で前記多結晶シリコン膜と前記積層膜との間の自
然酸化膜を消失させることを特徴とする半導体装
置の製造方法。 ４ シリコン膜と高融点金属の硅化物膜を連続的
に被着する工程は、一つの蒸着装置にシリコンと
高融点金属の蒸着源を別々に設け、シリコンの蒸
着を所定時間行なつた後、これを続行しながら同
時に高融点金属の蒸着を行うものである特許請求
の範囲第３項記載の半導体装置の製造方法。[Claims] 1. When manufacturing a semiconductor device having an electrode wiring in contact with a silicon substrate, the electrode wiring is coated with a silicon film and then coated with a high melting point metal silicide film without exposing its surface to the atmosphere. of the semiconductor device, characterized in that the semiconductor device is formed by continuously depositing the silicon substrate and heat-treating the obtained laminated film, and the heat treatment eliminates a natural oxide film between the silicon substrate and the laminated film. Production method. 2. The step of continuously depositing a silicon film and a silicide film of a high melting point metal is to provide separate vapor deposition sources for silicon and a high melting point metal in one vapor deposition apparatus, and after performing silicon vapor deposition for a predetermined time, 2. The method of manufacturing a semiconductor device according to claim 1, wherein the vapor deposition of a high melting point metal is simultaneously performed while this is continued. 3. When manufacturing a semiconductor device having an electrode wiring in contact with a silicon substrate via a polycrystalline silicon film, the electrode wiring is coated with a high-melting point metal silicide without exposing the surface to the atmosphere after depositing a silicon film. It is characterized in that it is formed by successively depositing films and subjecting the obtained laminated film to heat treatment, and that the natural oxide film between the polycrystalline silicon film and the laminated film is eliminated by this heat treatment. A method for manufacturing a semiconductor device. 4. The step of continuously depositing a silicon film and a silicide film of a high melting point metal is to provide separate vapor deposition sources for silicon and a high melting point metal in one vapor deposition apparatus, and after performing silicon vapor deposition for a predetermined time, 4. The method of manufacturing a semiconductor device according to claim 3, wherein the vapor deposition of a high melting point metal is simultaneously performed while this is continued.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13774979A JPS5662339A (en) | 1979-10-26 | 1979-10-26 | Production of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13774979A JPS5662339A (en) | 1979-10-26 | 1979-10-26 | Production of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5662339A JPS5662339A (en) | 1981-05-28 |
| JPH0147012B2 true JPH0147012B2 (en) | 1989-10-12 |
Family
ID=15205925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13774979A Granted JPS5662339A (en) | 1979-10-26 | 1979-10-26 | Production of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5662339A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4617071A (en) * | 1981-10-27 | 1986-10-14 | Fairchild Semiconductor Corporation | Method of fabricating electrically connected regions of opposite conductivity type in a semiconductor structure |
| JPS59220919A (en) * | 1983-05-31 | 1984-12-12 | Toshiba Corp | Manufacture of semiconductor device |
| JPS6057974A (en) * | 1983-09-09 | 1985-04-03 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS63207179A (en) * | 1987-02-24 | 1988-08-26 | Seikosha Co Ltd | Manufacture of semiconductor device |
| JPH0226021A (en) * | 1988-07-14 | 1990-01-29 | Matsushita Electron Corp | Formation of multilayer interconnection |
| JPH02292866A (en) * | 1989-05-02 | 1990-12-04 | Nec Corp | Manufacture of mis type semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4944797A (en) * | 1972-06-19 | 1974-04-27 | ||
| JPS5413283A (en) * | 1977-06-30 | 1979-01-31 | Ibm | Method of forming metal silicide layer on substrate |
-
1979
- 1979-10-26 JP JP13774979A patent/JPS5662339A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4944797A (en) * | 1972-06-19 | 1974-04-27 | ||
| JPS5413283A (en) * | 1977-06-30 | 1979-01-31 | Ibm | Method of forming metal silicide layer on substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5662339A (en) | 1981-05-28 |
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