JPH0154853B2 - - Google Patents
Info
- Publication number
- JPH0154853B2 JPH0154853B2 JP57017362A JP1736282A JPH0154853B2 JP H0154853 B2 JPH0154853 B2 JP H0154853B2 JP 57017362 A JP57017362 A JP 57017362A JP 1736282 A JP1736282 A JP 1736282A JP H0154853 B2 JPH0154853 B2 JP H0154853B2
- Authority
- JP
- Japan
- Prior art keywords
- melting point
- silicon
- high melting
- film
- point metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910052751 metal Inorganic materials 0.000 claims description 31
- 239000002184 metal Substances 0.000 claims description 31
- 238000002844 melting Methods 0.000 claims description 30
- 230000008018 melting Effects 0.000 claims description 29
- 229910052710 silicon Inorganic materials 0.000 claims description 26
- 239000010703 silicon Substances 0.000 claims description 26
- 229910021332 silicide Inorganic materials 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 22
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 21
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 230000001590 oxidative effect Effects 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 3
- 238000002156 mixing Methods 0.000 claims description 3
- 239000010408 film Substances 0.000 description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 23
- 239000010409 thin film Substances 0.000 description 18
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 15
- 229910052750 molybdenum Inorganic materials 0.000 description 15
- 239000011733 molybdenum Substances 0.000 description 15
- 239000010410 layer Substances 0.000 description 11
- 239000000758 substrate Substances 0.000 description 11
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 10
- 239000003990 capacitor Substances 0.000 description 10
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 238000005468 ion implantation Methods 0.000 description 8
- 238000007796 conventional method Methods 0.000 description 7
- 229910052785 arsenic Inorganic materials 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910016006 MoSi Inorganic materials 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- -1 arsenic ions Chemical class 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】
本発明は高融点金属シリサイドを電極や配線に
使用して半導体装置の製造方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device using refractory metal silicide for electrodes and wiring.
集積回路装置における集積度、動作速度、消費
電力等の向上のため配線等の寸法が益々微細化さ
れつつある。その様な微細化された集積回路装置
における配線や電極形成用材料として、モリブデ
ン、タングステン、タンタル等のいわゆる高融点
金属のシリサイドが有望と見なされている。その
理由は、これら高融点金属シリサイドは、従来の
MOS型集積回路のゲート電極等に用いられてき
た多結晶シリコンに比し、比抵抗が約1/10と低
く、かつ耐熱性が高いことや熱酸化により表面に
安定な酸化膜を形成できるからである。 BACKGROUND OF THE INVENTION In order to improve the degree of integration, operating speed, power consumption, etc. of integrated circuit devices, the dimensions of wiring, etc. are becoming increasingly finer. Silicides of so-called high melting point metals such as molybdenum, tungsten, and tantalum are considered to be promising materials for forming wiring and electrodes in such miniaturized integrated circuit devices. The reason is that these high melting point metal silicides are
Compared to polycrystalline silicon, which has been used for gate electrodes in MOS integrated circuits, it has a low resistivity of approximately 1/10, has high heat resistance, and can form a stable oxide film on the surface through thermal oxidation. It is.
従来高融点金属シリサイドを形成する方法の１
つとして、高融点金属膜をシリコンの基板上また
は薄膜上に堆積した後、熱処理により高融点金属
とシリコンとを反応させてシリサイド膜を形成す
る方法が知られている。この様な方法で形成した
高融点金属シリサイドを酸素等の酸化性雰囲気中
で高温熱処理すると、高融点金属シリサイドの表
面に酸化シリコン膜を形成できることが知られて
いる。しかし、この様な従来の方法で形成した高
融点金属シリサイドの酸化膜の絶縁耐圧は、シリ
コンそのものを熱酸化して形成した酸化シリコン
膜より相当に低く、従つて集積回路装置における
誘電体膜や層間絶縁膜としての応用に対して必ず
しも充分満足できるものではなかつた。 1 of conventional methods for forming high melting point metal silicide
One known method is to deposit a high melting point metal film on a silicon substrate or thin film, and then react the high melting point metal with silicon through heat treatment to form a silicide film. It is known that when a high melting point metal silicide formed by such a method is subjected to high temperature heat treatment in an oxidizing atmosphere such as oxygen, a silicon oxide film can be formed on the surface of the high melting point metal silicide. However, the dielectric strength of the high melting point metal silicide oxide film formed by such conventional methods is considerably lower than that of the silicon oxide film formed by thermally oxidizing silicon itself, and therefore it is difficult to use as a dielectric film in integrated circuit devices. It was not always completely satisfactory for application as an interlayer insulating film.
本発明は、上記従来の方法における問題点を大
幅に改良した新規な半導体装置の製造方法を提供
するものである。本発明による半導体装置の製造
方法は、シリコン上に高融点金属膜を堆積し、該
高融点金属膜の上からイオン注入を行なうことに
より該高融点金属膜と前記シリコンとの界面を混
合し、次いで非酸化性雰囲気中で加熱して前記高
融点金属と前記シリコンを反応せしめて高融点金
属シリサイド膜を形成した後、未反応の高融点金
属を除去し、次いで酸化性雰囲気中で熱酸化する
ことにより該高融点金属シリサイド表面に酸化膜
を形成することを特徴とするものである。 The present invention provides a novel method for manufacturing a semiconductor device that significantly improves the problems of the conventional methods described above. A method for manufacturing a semiconductor device according to the present invention includes depositing a high melting point metal film on silicon, mixing the interface between the high melting point metal film and the silicon by performing ion implantation from above the high melting point metal film, Next, after heating in a non-oxidizing atmosphere to cause the high melting point metal and the silicon to react to form a high melting point metal silicide film, unreacted high melting point metal is removed, and then thermal oxidation is performed in an oxidizing atmosphere. Accordingly, an oxide film is formed on the surface of the high melting point metal silicide.
本発明による方法によつて形成した高融点金属
シリサイドの酸化膜では従来の方法によつて形成
したものより大幅な絶縁耐圧の向上が得られる
が、これは、本発明による方法によつて形成され
た高融点金属シリサイドの表面が極めて平滑であ
るということと、さらにその様な平滑な高融点金
属シリサイドを酸化性雰囲気中で熱処理した場合
に形成される酸化膜の厚さも極めて均一でさらに
酸化膜と高融点金属シリサイドとの界面も平坦で
あるという発明者らが見出した事実によるものと
考えられる。 The refractory metal silicide oxide film formed by the method of the present invention has a much higher dielectric strength than that formed by the conventional method; The surface of the high melting point metal silicide is extremely smooth, and the thickness of the oxide film that is formed when such a smooth high melting point metal silicide is heat treated in an oxidizing atmosphere is also extremely uniform. This is thought to be due to the fact discovered by the inventors that the interface between the metal silicide and the high melting point metal silicide is also flat.
以下、本発明による方法の実施例を図を用いて
詳細に説明する。第１図ａ〜ｆの各図は本発明に
よる方法を半導体装置中に組込まれる薄膜蓄電器
の製作へ応用した場合の第１の実施例における主
要製造工程での薄膜蓄電器部の断面の模式図を示
したもののである。ｐ型シリコン基板１１の表面
に熱酸化によつて酸化シリコン膜１２を形成した
後、周知のホトエツチング技術を用いて開口１３
を設ける（ａ図）。次にスパツタ法を用いてモリ
ブデン膜１４を350Åの厚さに堆積した後、加速
電圧160keVの砒素イオン１５を５×1015cm-2だ
けイオン注入する（ｂ図）。その際開口１３以外
の領域では、モリブデン膜１４を貫通した砒素イ
オンは厚い酸化膜１２によりマスクされるのでシ
リコン基板１１中にまで達することはない。開口
部１３においては、大部分の砒素イオンはモリブ
ン膜１４を貫通してシリコン基板１１中に注入さ
れるとともに、モリブデン膜１４とシリコン基板
１１との界面はイオン衝撃によつて混合される。
次に600℃の水素雰囲気中でアニールすると開口
部１３のモリブデンは完全にモリブデンシリサイ
ドMoSi216に変換される（ｃ図）。なお、上述の
イオン注入の際にイオン注入電流が大きくイオン
注入速度が充分大きい場合には、イオン注入によ
つて生じる基板の温度上昇が400℃程度以上にも
なり、その際イオン注入による界面の混合効果と
前記温度上昇が相乗的に作用してイオン注入時に
シリサイド形成が自動的に行われてしまう。この
様な場合には上記600℃でのシリサイド形成のた
めの熱処理を省略してもさしつかえない。次に過
酸化水素水中に試料を浸漬することにより未反応
のモリブデン、即ち、酸化シリコン膜１２上のモ
リブデン膜を選択的にエツチング除去できる。更
に、硅素注入層１７を電気的に活性化させるため
1000℃の窒素ガス中で熱処理することによりモリ
ブデンシリサイドMoSi2層１６の下に高濃度に砒
素をドープしたn+層１７が形成される（ｄ図）。
次に950℃の酸素ガス中で熱処理することにより
モリブデンシリサイド層１６の上に酸化シリコン
膜１８を300Åの厚さに形成した（ｅ図）。次に周
知の真空蒸着法及びホトエツチング法を用いてア
ルミニウムからなる対向電極１９を形成すること
により薄膜蓄電器を作製した（ｆ図）。この様に
して作製した薄膜蓄電器の電極１６と１９との間
の絶縁耐圧の平均値は12Vでかつその標準偏差は
1.5Vであつた。一方従来のの方法、すなわち、
モリブデン薄膜を被着する前に予め開口部に硅素
をイオン注入しておいてからモリブデン薄膜を被
着した後にシリサイド化した場合には、それらの
値はそれぞれ4.5V及び3Vであり、本発明による
方法で作製したものに比して著しく劣つていた。 Hereinafter, embodiments of the method according to the present invention will be explained in detail using the drawings. Each of the figures in FIGS. 1a to 1f is a schematic cross-sectional view of a thin film capacitor part in the main manufacturing process in the first embodiment when the method according to the present invention is applied to the production of a thin film capacitor to be incorporated into a semiconductor device. This is what is shown. After forming a silicon oxide film 12 on the surface of a p-type silicon substrate 11 by thermal oxidation, an opening 13 is formed using a well-known photoetching technique.
(Figure a). Next, a molybdenum film 14 is deposited to a thickness of 350 Å using a sputtering method, and then arsenic ions 15 of 5×10 15 cm -2 are implanted at an acceleration voltage of 160 keV (Figure b). At this time, in areas other than the opening 13, the arsenic ions that have penetrated the molybdenum film 14 are masked by the thick oxide film 12, so that they do not reach into the silicon substrate 11. In the opening 13, most of the arsenic ions penetrate the molybdenum film 14 and are implanted into the silicon substrate 11, and the interface between the molybdenum film 14 and the silicon substrate 11 is mixed by ion bombardment.
Next, by annealing in a hydrogen atmosphere at 600° C., the molybdenum in the opening 13 is completely converted to molybdenum silicide MoSi 2 16 (Figure c). Note that during the above-mentioned ion implantation, if the ion implantation current is large and the ion implantation speed is sufficiently high, the temperature rise of the substrate caused by the ion implantation will be about 400°C or more, and the The mixing effect and the temperature increase act synergistically to automatically form silicide during ion implantation. In such a case, the heat treatment for forming silicide at 600° C. may be omitted. Next, by immersing the sample in hydrogen peroxide water, unreacted molybdenum, that is, the molybdenum film on the silicon oxide film 12 can be selectively etched away. Furthermore, in order to electrically activate the silicon implanted layer 17,
By heat treatment in nitrogen gas at 1000° C., an n + layer 17 doped with arsenic at a high concentration is formed under the molybdenum silicide MoSi 2 layer 16 (Figure d).
Next, a silicon oxide film 18 with a thickness of 300 Å was formed on the molybdenum silicide layer 16 by heat treatment in oxygen gas at 950° C. (Fig. e). Next, a thin film capacitor was manufactured by forming a counter electrode 19 made of aluminum using the well-known vacuum evaporation method and photoetching method (Figure f). The average value of the dielectric strength between electrodes 16 and 19 of the thin film capacitor produced in this way was 12V, and its standard deviation was
It was 1.5V. On the other hand, the conventional method, i.e.
If silicon is ion-implanted into the opening before depositing the molybdenum thin film and then silicided after depositing the molybdenum thin film, these values are 4.5V and 3V, respectively, and according to the present invention, the values are 4.5V and 3V, respectively. It was significantly inferior to that produced by the method.
次に第２の実施例について説明する。この実施
例においては高融点金属と反応させてシリサイド
を形成するためのシリコンとして絶縁膜上に形成
した単結晶シリコン薄膜を用いた。第２図ａ〜ｆ
は本発明の第２の実施例を説明するための図で、
第１の実施例と同様に薄膜蓄電器を組込んだ半導
体装置の主要製造工程における該薄膜蓄電器部の
断面の模式図である。シリコン単結晶基板２１上
に形成された酸化シリコン膜２２に開口２３を設
けた（ａ図）後、多結晶シリコン膜２４を化学蒸
着法によつて堆積する。（ｂ図）。次に周知のレー
ザアニール法、すなわち連続発振レーザ光の走査
により該多結晶シリコン膜２４を単結晶化する。
この際開口部２３の単結晶シリコン基板を種にし
て、単結晶を開口部２３から横方向に成長させる
いわゆるlateral seeding法を用いた。次に周知
の選択酸化技術を用いて酸化シリコン膜２５で囲
まれたシリコン単結晶薄膜からなる島状の領域２
４′を形成する（ｃ図）。これ以後は、第１の実施
例の場合と同様の工程により第２図ｄに示した様
なn+層２７上に形成されたモリブデンシリサイ
ド層２６を酸化して形成した薄い酸化膜２８を絶
縁層とし、アルニウムを上部電極２９とした薄膜
蓄電器を作製した。 Next, a second embodiment will be described. In this example, a single crystal silicon thin film formed on an insulating film was used as the silicon for reacting with a high melting point metal to form silicide. Figure 2 a-f
is a diagram for explaining the second embodiment of the present invention,
FIG. 3 is a schematic cross-sectional view of a thin film capacitor section in the main manufacturing process of a semiconductor device incorporating a thin film capacitor, similar to the first embodiment. After an opening 23 is provided in a silicon oxide film 22 formed on a silicon single crystal substrate 21 (FIG. 1A), a polycrystalline silicon film 24 is deposited by chemical vapor deposition. (Figure b). Next, the polycrystalline silicon film 24 is made into a single crystal by a well-known laser annealing method, that is, by scanning with a continuous wave laser beam.
At this time, a so-called lateral seeding method was used in which the single crystal silicon substrate in the opening 23 was used as a seed and the single crystal was grown laterally from the opening 23. Next, an island-like region 2 made of a silicon single crystal thin film surrounded by a silicon oxide film 25 is formed using a well-known selective oxidation technique.
4' (Figure c). After this, a thin oxide film 28 formed by oxidizing the molybdenum silicide layer 26 formed on the n + layer 27 as shown in FIG. A thin film capacitor was fabricated using aluminum as a layer and an upper electrode 29 made of aluminum.
この様に本発明による方法を用いて作製した薄
膜蓄電器においては、従来の方法、すなわち、予
めシリコン単結晶領域に砒素のドーピングを行つ
ておいてからモリブデン薄膜を堆積した後、モリ
ブデンとn+層との反応によつてモリブデンシリ
サイドを形成し、該モリブデンシリサイド膜を熱
酸化するという工程で作製した場合に比して、第
１の実施例の場合とほぼ同程度の耐圧の向上が得
られた。 As described above, in the thin film capacitor manufactured using the method according to the present invention, the conventional method is used, that is, a silicon single crystal region is doped with arsenic in advance, a molybdenum thin film is deposited, and then a molybdenum and n + layer is deposited. Compared to the case where molybdenum silicide is formed by a reaction with the molybdenum silicide film and the molybdenum silicide film is thermally oxidized, an improvement in breakdown voltage to the same extent as in the case of the first example was obtained. .
第３の実施例は、シリコン薄膜として多結晶シ
リコンを用いた場合である。第２の実施例におい
て多結晶膜（第２図ｂにおける２４）の単結晶化
工程を省略した場合、すなわち、第２図ｃにおけ
る島状領域２４′が多結晶シリコン膜である場合
にも本発明による方法を用いて形成した薄膜蓄電
器は従来の方法によつて形成したものに比して著
しい耐圧の向上が得られた。 The third embodiment is a case where polycrystalline silicon is used as the silicon thin film. The present invention also applies when the single crystallization step of the polycrystalline film (24 in FIG. 2b) is omitted in the second embodiment, that is, when the island region 24' in FIG. 2c is a polycrystalline silicon film. Thin film capacitors formed using the method of the invention have significantly improved breakdown voltage compared to those formed using conventional methods.
上述の実施例においては、高融点金属を堆積す
るシリコンとしてはいずれも比抵抗が数Ω・cmの
基板、または、ドーピングを行つていないシリコ
ン薄膜を用いたが、高濃度にドーピングしたシリ
コン基板またはシリコン薄膜に対しても本発明に
よる方法は有効に適用できた。また、イオン注入
におけるイオンの種類も族や族のドーパント
イオンの他、目的によりシリコン、アルゴンある
いは金属イオン等種々のイオンを用いることがで
きる。更に、モリブデン以外の高融点金属（タン
グステン、タンタル、チタン、ニオブ、ハフニウ
ム）に対しても本発明による方法が有効に適用で
きた。 In the above embodiments, a substrate with a resistivity of several Ω·cm or an undoped silicon thin film was used as the silicon on which the high melting point metal was deposited, but a highly doped silicon substrate was used. The method according to the present invention was also effectively applied to silicon thin films. Furthermore, in addition to group and group dopant ions, various ions such as silicon, argon, or metal ions can be used for ion implantation depending on the purpose. Furthermore, the method according to the present invention could be effectively applied to high melting point metals (tungsten, tantalum, titanium, niobium, hafnium) other than molybdenum.
また上述の実施例ではイオン注入後にモリブデ
ンを完全にモリブデンシリサイドMoSi2に変換す
るための工程として、水素雰囲気中のアニールを
用いたが、何もこれに限る必要はなく、窒素雰囲
気中、不活性雰囲気中、真空中のアニール等を用
いてもよい。 Furthermore, in the above embodiment, annealing in a hydrogen atmosphere was used as a process to completely convert molybdenum into molybdenum silicide MoSi 2 after ion implantation, but there is no need to limit it to this. Annealing in an atmosphere or in a vacuum may be used.
上述の如く本発明による方法を用いて形成した
高融点金属シリサイドの酸化膜は優れた絶縁耐圧
を有し、集積回路装置の配線間の絶縁層、ダイナ
ミツク型ランダムアクセスメモリ装置を構成する
蓄電器の誘電体、更には本発明の方法によつて形
成した酸化膜上に単結晶シリコン膜を形成してな
る高融点金属シリサイドをゲート電極とし、該シ
リサイドの酸化膜をゲート絶縁膜としたMOS型
トランジスタ、等の作製に有効に応用することが
できる。 As described above, the high melting point metal silicide oxide film formed using the method according to the present invention has excellent dielectric strength and is suitable for use as an insulating layer between interconnects in integrated circuit devices, and as a dielectric layer in capacitors constituting dynamic random access memory devices. a MOS type transistor in which a high-melting point metal silicide formed by forming a single crystal silicon film on an oxide film formed by the method of the present invention is used as a gate electrode, and an oxide film of the silicide is used as a gate insulating film; It can be effectively applied to the production of etc.
第１図及び第２図は本発明による方法の実施例
における主要工程での断面の模式図。図中の番号
はそれぞれ以下のものを示している。
１１，２１……シリコン基板、１２，２２……
酸化シリコン膜、１３，２３……シリコン酸化膜
の開口、１４……モリブデン膜、１５……砒素イ
オンビーム、１６，２６……モリブデンシリサイ
ド、１７，２７……n+層、１８，２８……モリ
ブデンシリサイドの酸化膜、１９，２９……アル
ミニウム電極。
1 and 2 are schematic cross-sectional views of main steps in an embodiment of the method according to the present invention. The numbers in the figure indicate the following, respectively. 11, 21... Silicon substrate, 12, 22...
Silicon oxide film, 13, 23... opening in silicon oxide film, 14... molybdenum film, 15... arsenic ion beam, 16, 26... molybdenum silicide, 17, 27... n + layer, 18, 28... Molybdenum silicide oxide film, 19, 29...aluminum electrode.
Claims (1)
点金属膜の上からイオン注入を行なうことにより
該高融点金属膜と前記シリコンとの界面を混合し
次いで非酸化性雰囲気中で加熱して前記高融点金
属と前記シリコンを反応せしめて高融点金属シリ
サイド膜を形成した後未反応の高融点金属を除去
し、次いで酸化性雰囲気中で熱酸化することによ
り、該高融点金属シリサイド表面に酸化膜を形成
することを特徴とする半導体装置の製造方法。1. Depositing a high melting point metal film on silicon, mixing the interface between the high melting point metal film and the silicon by implanting ions from above the high melting point metal film, and then heating in a non-oxidizing atmosphere. After the high melting point metal and the silicon are reacted to form a high melting point metal silicide film, the unreacted high melting point metal is removed, and then thermal oxidation is performed in an oxidizing atmosphere to oxidize the surface of the high melting point metal silicide. A method for manufacturing a semiconductor device, characterized by forming a film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1736282A JPS58134427A (en) | 1982-02-05 | 1982-02-05 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1736282A JPS58134427A (en) | 1982-02-05 | 1982-02-05 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58134427A JPS58134427A (en) | 1983-08-10 |
| JPH0154853B2 true JPH0154853B2 (en) | 1989-11-21 |
Family
ID=11941917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1736282A Granted JPS58134427A (en) | 1982-02-05 | 1982-02-05 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58134427A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4558507A (en) * | 1982-11-12 | 1985-12-17 | Nec Corporation | Method of manufacturing semiconductor device |
| JPS61274325A (en) * | 1985-05-29 | 1986-12-04 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS6242524A (en) * | 1985-08-20 | 1987-02-24 | Fujitsu Ltd | Manufacture of semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56158454A (en) * | 1980-05-12 | 1981-12-07 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
-
1982
- 1982-02-05 JP JP1736282A patent/JPS58134427A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56158454A (en) * | 1980-05-12 | 1981-12-07 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58134427A (en) | 1983-08-10 |
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