JPS6242524A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPS6242524A
JPS6242524A JP18229085A JP18229085A JPS6242524A JP S6242524 A JPS6242524 A JP S6242524A JP 18229085 A JP18229085 A JP 18229085A JP 18229085 A JP18229085 A JP 18229085A JP S6242524 A JPS6242524 A JP S6242524A
Authority
JP
Japan
Prior art keywords
temperature
silicide
wafer
gas atmosphere
inert
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18229085A
Other languages
Japanese (ja)
Inventor
Kazuyuki Fujiwara
和幸 藤原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18229085A priority Critical patent/JPS6242524A/en
Publication of JPS6242524A publication Critical patent/JPS6242524A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To form an SiO2 film having no defect on the surface of a metallic silicide by elevating the temperature of the silicide in an inert-gas atmosphere, changing over the inert-gas atmosphere into an oxidizing atmosphere and oxidizing the silicide when the temperature of the silicide reaches a fixed temperature, changing over the oxidizing atmosphere into the inert-gas atmosphere again and lowering the temperature of the silicide. CONSTITUTION:A wafer in which a poly Si layer 17 and a metallic silicide layer 18 are laminated on a substrate 11 is preheated, and the wafer is heated for a fixed time in an inert-gas atmosphere at a temperature lower than an oxidizing temperature and the temperature of the wafer is elevated. When the temperature of the wafer reaches the oxidizing temperature, the inert-gas atmospheres is changed over to an oxygen atmosphere, and the wafer is oxidized for a predetermined time. The oxygen atmosphere is changed over to the inert- gas atmosphere again, and the wafer is cooled slowly. Accordingly, oxidation is started after a point of time when Si in sufficient quantity diffuses in the inert-gas atmosphere, thus coating the wafer with an SiO2 film 20 having no defect.

Description

【発明の詳細な説明】 〔概要〕 金属珪化物(以下には単にシリサイドという)を不活性
ガス中で勾配的に加熱する(以下ランピングという)こ
とにより、シリサイドの変形などの発生がないようにす
る。
[Detailed Description of the Invention] [Summary] A metal silicide (hereinafter simply referred to as silicide) is heated in a gradient manner in an inert gas (hereinafter referred to as ramping) to prevent deformation of the silicide. do.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置の製造方法に関するもので、さらに
詳しく言えば、半導体装置に用いるシリサイドを酸化す
る方法の改善に関するものである。
The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to an improvement in a method for oxidizing silicide used in a semiconductor device.

〔従来の技術〕[Conventional technology]

シリサイドを半導体装置に用いる技術が実用化されるよ
うになり、最近では例えばMOS l−ランジスタのゲ
ート電極にシリサイドが利用されている。
Techniques for using silicide in semiconductor devices have come into practical use, and recently silicide has been used, for example, in gate electrodes of MOS l-transistors.

それを作る工程を第2図の断面図を参照して説明すると
、半導体基板11に形成されたゲート電極16は、多結
晶シリコン(ポリシリコン)層17と珪化モリブデン(
Mo−5i2)のようなシリサイド層18の2屓構造に
よって作られる。なお第2図において、12はフィール
ド酸化膜、13はソース、14はドレイン、15はゲー
トa化膜を示す。ゲート電極16にシリサイド層18を
用いる理由は、それによってゲート電極の抵抗が小さく
抑えられるからである。
The process of making it will be explained with reference to the cross-sectional view of FIG.
It is made by a bilayer structure of a silicide layer 18 such as Mo-5i2). In FIG. 2, 12 is a field oxide film, 13 is a source, 14 is a drain, and 15 is a gate a-oxide film. The reason why the silicide layer 18 is used for the gate electrode 16 is that the resistance of the gate electrode can be kept low thereby.

MOSトランジスタの製造工程において、ゲート電極1
6の表面を酸化することが行われる。その理由は、ゲー
ト電極16を形成するには、半導体基板11上に順にポ
リシリコンを例えば化学気相成長(CVD)法で堆積し
、その上にMoSi2をスパッタまたはCVD法で成長
し、しかる後にMoSi2の層とポリシリコン層とをエ
ツチングして第2図に示される電極を作る。この工程で
電極が第2図に点線で示すようにエツチングされたとす
ると、後の工程で絶縁膜を例えば燐・シリケート・ガラ
ス(PSG)で作ったとき、電極の実線で示す両側部と
点線の間の部分にPSGが完全に埋らず、絶縁不良の原
因となる。
In the manufacturing process of a MOS transistor, the gate electrode 1
Oxidation of the surface of 6 is performed. The reason is that to form the gate electrode 16, polysilicon is sequentially deposited on the semiconductor substrate 11 by, for example, chemical vapor deposition (CVD), MoSi2 is grown thereon by sputtering or CVD, and then The MoSi2 layer and the polysilicon layer are etched to create the electrode shown in FIG. Assuming that the electrode is etched in this step as shown by the dotted line in Figure 2, when the insulating film is made of, for example, phosphorus silicate glass (PSG) in a later step, the two sides of the electrode shown by the solid line and the dotted line PSG is not completely filled in the space between the two, leading to poor insulation.

または、ソース13とドレイン14は不純物のイオン注
入によって形成するが、そのためには、5iOz膜15
のゲート電極以外の部分を1度エツチングし、基板表面
を露出し、再度SiO2膜を形成する。前記したエツチ
ングはフッ酸系の液を用いてなされるが、そのときゲー
ト酸化膜も符号19を付した部分がエツチングされる。
Alternatively, the source 13 and drain 14 are formed by ion implantation of impurities, but for that purpose, the 5iOz film 15 is
The portion other than the gate electrode is etched once to expose the substrate surface, and a SiO2 film is formed again. The above-mentioned etching is performed using a hydrofluoric acid solution, and at this time, the portion of the gate oxide film designated by reference numeral 19 is also etched.

そこで、第3図に示される如くにゲート電極16の表面
を酸化してシリサイド酸化膜20を形成し、上記の欠陥
を修正する。そのためには、第2図に示すデバイスが作
られたウェハを第4図に示す炉に入れ、第5図の線図に
示される順序でランピングして熱酸化する。なお第4図
において、31は炉芯管、32は石英ボート、33はウ
ェハ、34はヒータを示す。
Therefore, as shown in FIG. 3, the surface of the gate electrode 16 is oxidized to form a silicide oxide film 20 to correct the above defects. For this purpose, the wafer on which the device shown in FIG. 2 has been fabricated is placed in the furnace shown in FIG. 4, and is ramped and thermally oxidized in the order shown in the diagram of FIG. In FIG. 4, 31 is a furnace core tube, 32 is a quartz boat, 33 is a wafer, and 34 is a heater.

第5図を参照すると、ウェハは酸素雰囲気で置換した炉
内に入れられ、クランクなどを防止するため所定の時間
をかけて緩やかに800℃程度にまで予熱され、次いで
900℃に昇温しで所定の時間900°Cで加熱され、
次いで10℃/分のレートで950°Cまで昇温され、
950℃で所定の時間加熱された後に不活性ガス例えば
N2ガス雰囲気に切り換え4℃/分のレートで徐冷され
る。このとき、シリサイドの表面では MoSi2+ 02−= MOO3+ 5iOz   
(1)または MoSi2+ 02− Mo + 5iOz    (
21の反応が発生するものと解される。
Referring to FIG. 5, the wafer is placed in a furnace purged with oxygen, and is slowly preheated to about 800°C over a predetermined period of time to prevent cranking, and then heated to 900°C. heated at 900°C for a predetermined time,
The temperature was then increased to 950°C at a rate of 10°C/min.
After being heated at 950° C. for a predetermined period of time, the atmosphere is changed to an inert gas such as N2 gas and slowly cooled at a rate of 4° C./min. At this time, on the surface of the silicide, MoSi2+ 02-= MOO3+ 5iOz
(1) or MoSi2+ 02- Mo + 5iOz (
It is understood that 21 reactions occur.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記したシリサイドの熱酸化法において、シリサイド層
を酸化した後に検査したところ、シリサイド層の表面に
粉(MOO3の粉末と解される)が出てきたり、場合よ
っては表面がくずれていることが観察され、そのような
シリサイド層をもった電極は使用することができない。
In the silicide thermal oxidation method described above, when the silicide layer was inspected after oxidation, it was observed that powder (interpreted as MOO3 powder) appeared on the surface of the silicide layer, and in some cases, the surface collapsed. Therefore, electrodes with such silicide layers cannot be used.

本発明はこのような点に鑑みて創作されたもので、シリ
サイドの酸化を上記した如き欠陥が発生することな〈実
施する方法を提供することを目的とする。
The present invention was created in view of these points, and it is an object of the present invention to provide a method for carrying out the oxidation of silicide without causing the above-mentioned defects.

〔問題点を解決するための手段〕[Means for solving problems]

第1図は本発明の方法の順序(シーケンス)を示す線図
である。
FIG. 1 is a diagram showing the sequence of the method of the invention.

本発明の方法においては、前記した予熱の後に、先ず不
活性ガス例えばN2ガスに置換した炉内へ酸化すべきシ
リサイドとポリシリコン層からなる電極が設けられたウ
ェハを入れ、900“Cにて所定の時間加熱した後に9
50℃まで昇温し、そこで酸素雰囲気に切り換え、酸素
雰囲気中で所定の時間加熱して酸化を行い、再び不活性
ガス雰囲気に切り換え、徐冷する。
In the method of the present invention, after the above-mentioned preheating, the wafer provided with electrodes made of silicide and polysilicon layers to be oxidized is first placed in a furnace purged with an inert gas, such as N2 gas, and heated at 900"C. After heating for the specified time 9
The temperature is raised to 50° C., then switched to an oxygen atmosphere, heated in the oxygen atmosphere for a predetermined time to perform oxidation, then switched to an inert gas atmosphere again and slowly cooled.

〔作用〕[Effect]

上記した方法においては、シリサイド内に十分な量のシ
リコンが拡散するまでは不活性ガス雰囲気内に置き、十
分な量のシリコンの拡散がなされた時点から酸化を開始
し、それによってシリサイドの表面をSiO:+膜で覆
うものである。
In the above method, the silicide is kept in an inert gas atmosphere until a sufficient amount of silicon has diffused into the silicide, and oxidation is started when a sufficient amount of silicon has diffused, thereby increasing the surface of the silicide. It is covered with a SiO:+ film.

〔実施例〕〔Example〕

以下、図面を参照して本発明の実施例を詳細に説明する
Embodiments of the present invention will be described in detail below with reference to the drawings.

ポリシリコン層の上にシリサイド層をもったポリシリコ
ン/シリサイド電極の酸化において、前記した反応fl
) 、 (21が発生するための条件は、シリサイド層
にシリコンが十分に拡散し、このシリコンが酸化して十
分な量のSiO2が形成されることであると解される。
In the oxidation of a polysilicon/silicide electrode having a silicide layer on a polysilicon layer, the above reaction fl.
), (It is understood that the conditions for the occurrence of 21 are that silicon is sufficiently diffused into the silicide layer, and this silicon is oxidized to form a sufficient amount of SiO2.

従来例においてはシリコンが十分にシリサイド層に拡散
しないうちに、すなわち酸化速度〉シリコン拡散速度の
条件の下で加熱されたので、5i02が形成される前に
Mo03またはMoが遊離し、それが表面に出てシリサ
イド層が(ずれたものと解される。
In the conventional example, heating was carried out before silicon was sufficiently diffused into the silicide layer, that is, under the condition of oxidation rate > silicon diffusion rate, Mo03 or Mo was liberated before 5i02 was formed, and it spread to the surface. It is understood that the silicide layer has shifted.

そこで、本発明においては、酸化速度≦シリコン拡散速
度を作り出した。
Therefore, in the present invention, the following relationship was created: oxidation rate≦silicon diffusion rate.

第1図を参照すると、従来と同じ予熱をなした後に、ウ
ェハのおかれる炉芯管内をN2ガス雰囲気にし、900
℃で所定の時間加熱した後に950℃まで10℃/分の
レートで昇温する(ランピング)。
Referring to FIG. 1, after preheating the same as in the conventional method, the inside of the furnace core tube in which the wafer is placed is made into an N2 gas atmosphere, and
After heating at ℃ for a predetermined time, the temperature is raised to 950 ℃ at a rate of 10 ℃/min (ramping).

この時間帯内ポリシリコン層のシリコンはシリサイド層
に拡散するが、シリサイドの酸化は未だ始まらない。
During this time period, silicon in the polysilicon layer diffuses into the silicide layer, but oxidation of the silicide has not yet begun.

950℃に達したところで、N2ガス雰囲気から酸素ガ
ス雰囲気に切り換えて、形成すべき酸化膜の膜厚などで
決定される所定時間内950℃の温度を保ち酸化を行う
。この段階ではシリサイド層に十分な量のシリコンが拡
散しているので、前記反応下のSiO2が十分に作られ
る。
When the temperature reaches 950° C., the N2 gas atmosphere is switched to the oxygen gas atmosphere, and oxidation is performed while maintaining the temperature at 950° C. for a predetermined time determined by the thickness of the oxide film to be formed. At this stage, a sufficient amount of silicon has diffused into the silicide layer, so that a sufficient amount of SiO2 is produced under the reaction.

所定の時間が経過した後酸素ガス雰囲気をN2ガス雰囲
気に切り換え、4℃/分のレートで徐冷し、最後に炉か
らウェハを取り出す。
After a predetermined period of time has elapsed, the oxygen gas atmosphere is switched to a N2 gas atmosphere, and the wafer is slowly cooled at a rate of 4° C./min. Finally, the wafer is taken out from the furnace.

MoSi2がポリシリコン層の上に設けられた前記の電
極の酸化において、本発明者の行った実験において不良
品は1個も発生せず、すべての電極に満足しべき酸化膜
が形成されていることが確認された。
In the oxidation of the above-mentioned electrodes in which MoSi2 is provided on a polysilicon layer, no defective products were generated in experiments conducted by the present inventor, and satisfactory oxide films were formed on all electrodes. This was confirmed.

〔発明の効果〕〔Effect of the invention〕

以上述べてきたように本発明によれば、ポリシリコン層
の上にシリサイド層を設けた構造体の酸化において、不
良品の発生が皆無となり、半導体装置製造の歩留りを著
しく改善した。なお、上記はMoS L+を例に説明し
たが、本発明の通用範囲はその場合に限定されるもので
なく、タングステンシリサイドなどの如きその他のシリ
サイドの場合にも及ぶものであり、また不活性ガスはN
2ガスに限定されることな(、アルゴン(Ar)の如き
その他のガスを含むものである。
As described above, according to the present invention, there is no generation of defective products in the oxidation of a structure in which a silicide layer is provided on a polysilicon layer, and the yield of manufacturing semiconductor devices is significantly improved. Although the above description has been made using MoS L+ as an example, the scope of the present invention is not limited to that case, but also extends to the case of other silicides such as tungsten silicide. is N
2 gases (but includes other gases such as argon (Ar)).

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明方法の酸化シーケンスの線図、′MS2
図はポリシリコンJi/シリサイド層からなるゲート電
極の断面図、 第3図は酸化膜でおおわれた第2図のゲートの断面図、 第4図は酸化炉の断面図、 第5図は従来の酸化シーケンスの線図である。 第2図ないし第4図において、 11は半導体基板、 12はフィールド酸化膜、 13と14はソースとドレイン、 15は 5i02膜、 16はゲート電極、 17はポリシリコン層、 18はシリサイド層、 19はゲート酸化膜のエツチングされた部分、31は炉
芯管、 32は石英ボート、 33はウェハ、 34はヒータである。 苓発鳴ろユのシーグンス碌図 第1図 i′ンシシコソ1/シ芦イト“1P′r−ト電不i虻i
の第2図 酵イu1であ景われち兎20のゲート胃屁−合面図第3
図 酸イこスリ5錦fヤ1図 第4図
FIG. 1 is a diagram of the oxidation sequence of the method of the invention, 'MS2
The figure shows a cross-sectional view of a gate electrode made of polysilicon Ji/silicide layer. Figure 3 is a cross-sectional view of the gate of Figure 2 covered with an oxide film. Figure 4 is a cross-sectional view of an oxidation furnace. FIG. 2 is a diagram of an oxidation sequence. In FIGS. 2 to 4, 11 is a semiconductor substrate, 12 is a field oxide film, 13 and 14 are sources and drains, 15 is a 5i02 film, 16 is a gate electrode, 17 is a polysilicon layer, 18 is a silicide layer, 19 31 is an etched portion of the gate oxide film, 31 is a furnace core tube, 32 is a quartz boat, 33 is a wafer, and 34 is a heater. 1P'r-todenfui 虦i
2nd figure of U1 and the gate of U1 20's stomach fart - face view 3rd
Figure 4

Claims (1)

【特許請求の範囲】 多結晶シリコン層の上に形成された金属珪化物の酸化に
おいて、 前記金属珪化物を酸化温度に達するまで不活性ガス雰囲
気中で昇温せしめ、 酸化温度に達した後に不活性ガス雰囲気を酸素ガス雰囲
気に切り換えて作られる酸化雰囲気で所定の時間酸化し
、 しかる後に不活性ガス雰囲気に切り換えて降温すること
を特徴とする半導体装置の製造方法。
[Claims] In the oxidation of a metal silicide formed on a polycrystalline silicon layer, the metal silicide is heated in an inert gas atmosphere until the oxidation temperature is reached, and after reaching the oxidation temperature, the metal silicide is inactivated. A method for manufacturing a semiconductor device, which comprises oxidizing for a predetermined period of time in an oxidizing atmosphere created by switching an active gas atmosphere to an oxygen gas atmosphere, and then switching to an inert gas atmosphere to lower the temperature.
JP18229085A 1985-08-20 1985-08-20 Manufacture of semiconductor device Pending JPS6242524A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18229085A JPS6242524A (en) 1985-08-20 1985-08-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18229085A JPS6242524A (en) 1985-08-20 1985-08-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6242524A true JPS6242524A (en) 1987-02-24

Family

ID=16115694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18229085A Pending JPS6242524A (en) 1985-08-20 1985-08-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6242524A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02249230A (en) * 1988-11-25 1990-10-05 Fujitsu Ltd Forming method for metal electrode

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58134427A (en) * 1982-02-05 1983-08-10 Nec Corp Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58134427A (en) * 1982-02-05 1983-08-10 Nec Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02249230A (en) * 1988-11-25 1990-10-05 Fujitsu Ltd Forming method for metal electrode

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