JP2739593B2 - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method

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Publication number
JP2739593B2
JP2739593B2 JP1141451A JP14145189A JP2739593B2 JP 2739593 B2 JP2739593 B2 JP 2739593B2 JP 1141451 A JP1141451 A JP 1141451A JP 14145189 A JP14145189 A JP 14145189A JP 2739593 B2 JP2739593 B2 JP 2739593B2
Authority
JP
Japan
Prior art keywords
film
polysilicon
rto
forming
cvd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1141451A
Other languages
Japanese (ja)
Other versions
JPH036022A (en
Inventor
均 丹羽
章滋 中西
Original Assignee
セイコーインスツルメンツ株式会社
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Publication date
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Priority to JP1141451A priority Critical patent/JP2739593B2/en
Publication of JPH036022A publication Critical patent/JPH036022A/en
Application granted granted Critical
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Expired - Lifetime legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体素子、例えばポリシリコン2層構造の
半導体不揮発性メモリ、ポリシリコンスタック型ダイナ
ミックランダムアクセスメモリなどに用いられる高性
能,高信頼性をもった基板もしくはポリシリコン電極上
の絶縁膜の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a high-performance and high-reliability semiconductor device, for example, a semiconductor nonvolatile memory having a polysilicon two-layer structure, a polysilicon stack type dynamic random access memory, and the like. The present invention relates to a method for forming an insulating film on a substrate or a polysilicon electrode having a pattern.

〔発明の概要〕[Summary of the Invention]

本発明では、シリコン基板もしくはポリシリコン電極
上に急速ランプ熱酸化(RTO(Rapid Thermal Oxidatio
n))法によりシリコン酸化膜(以下RTO(Rapid Therma
l Oxide)膜と呼ぶ)を形成し、次にこのRTO膜上に化学
気相成長(CVD)法によりCVDシリコン窒化膜を堆積させ
た。そしてこのCVDシリコン窒化膜を熱酸化することに
よりその膜表面上に熱酸化シリコン窒化膜を形成した。
以上の一連の工程によりシリコン基板もしくはポリシリ
コン上の多層絶縁膜を形成した。
In the present invention, rapid thermal oxidation (RTO) is performed on a silicon substrate or a polysilicon electrode.
n)) silicon oxide film (hereinafter referred to as RTO (Rapid Therma
l Oxide) film, and a CVD silicon nitride film was deposited on the RTO film by a chemical vapor deposition (CVD) method. The CVD silicon nitride film was thermally oxidized to form a thermally oxidized silicon nitride film on the surface of the film.
Through the above series of steps, a multilayer insulating film on a silicon substrate or polysilicon was formed.

〔従来の技術〕[Conventional technology]

従来の技術を図面を用いて説明する。第2図(a)〜
(c)は従来の技術を用いて作成されたポリシリコン電
極上の多層絶縁膜の形成工程を示す断面図である。ま
ず、半導体基板1の表面上に薄いゲート絶縁膜2が形成
されており、その上に1層目のポリシリコン電極3がCV
D法により堆積されている(第2図(a))。次にこの
1層目のポリシリコン電極3を熱酸化してポリシリコン
熱酸化膜8を形成する。その後、このポリシリコン熱酸
化膜8の上にCVD法によりCVDシリコン窒化膜5を堆積さ
せる(第2図(b))。さらにこのCVDシリコン窒化膜
5を熱酸化して、その膜表面上に熱酸化シリコン窒化膜
6を形成させる。そして最後に2層目のポリシリコン電
極7をCVD法により堆積させている(第2図(c))。
A conventional technique will be described with reference to the drawings. Fig. 2 (a)-
(C) is a cross-sectional view showing a step of forming a multilayer insulating film on a polysilicon electrode formed using a conventional technique. First, a thin gate insulating film 2 is formed on the surface of a semiconductor substrate 1, and a first polysilicon electrode 3 is formed on the gate insulating film 2 by CV.
It is deposited by the D method (FIG. 2 (a)). Next, the first-layer polysilicon electrode 3 is thermally oxidized to form a polysilicon thermal oxide film 8. Thereafter, a CVD silicon nitride film 5 is deposited on the polysilicon thermal oxide film 8 by a CVD method (FIG. 2B). Further, the CVD silicon nitride film 5 is thermally oxidized to form a thermal silicon oxide nitride film 6 on the film surface. Finally, a second-layer polysilicon electrode 7 is deposited by the CVD method (FIG. 2C).

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

しかし、従来の形成工程では以下の二つの課題があ
る。まず第1に濃いリン濃度でドープされた1層目のポ
リシリコン電極のポリシリコン酸化を行う場合、ドープ
された不純物であるリンのためその酸化速度が速いので
大口径シリコンウエハでは面内膜厚均一性を得るのが難
しい。第2に良い膜質を得るため1000℃以上の高温雰囲
気でポリシリコンの酸化を行う場合、1層目のポリシリ
コン電極堆積後に長時間の高温熱処理工程を行うと100
Å以下の薄いゲート絶縁膜の膜質を著しく劣化させると
いう結果が得られている。
However, the conventional formation process has the following two problems. First, in the case of performing polysilicon oxidation of a first-layer polysilicon electrode doped with a high phosphorus concentration, the oxidation rate is high because of phosphorus, which is a doped impurity. It is difficult to obtain uniformity. Secondly, when oxidizing polysilicon in a high-temperature atmosphere of 1000 ° C. or higher to obtain good film quality, a long-time high-temperature heat treatment after depositing the first-layer polysilicon electrode may result in 100%.
The result that the film quality of the thin gate insulating film of Å or less is significantly deteriorated is obtained.

〔課題を解決するための手段〕[Means for solving the problem]

以上の課題を解決するために、本発明では、ポリシリ
コン電極上の通常酸化炉でのポリシリコン熱酸化膜の代
わりに、より短い高温熱処理時間で形成が可能なRTO膜
を用いた。
In order to solve the above problems, in the present invention, an RTO film that can be formed in a shorter high-temperature heat treatment time is used instead of a polysilicon thermal oxide film in a normal oxidation furnace on a polysilicon electrode.

〔作用〕[Action]

上記のRTO膜は高温短時間の熱処理方法であるので通
常酸化炉による熱酸化ほどリン不純物濃度の影響をうけ
ない。さらに、RTO膜の形成時間は、通常酸化炉でのポ
リシリコンの熱酸化時間より極めて短い時間(2〜3分
程度)で同膜厚のシリコン酸化膜を形成できる。
Since the above RTO film is a heat treatment method of high temperature and short time, it is not affected by the concentration of phosphorus impurities as much as thermal oxidation in an ordinary oxidation furnace. Further, the silicon oxide film of the same thickness can be formed in a time (about two to three minutes) much shorter than the thermal oxidation time of polysilicon in an ordinary oxidation furnace.

以上のようにRTO膜は本発明の多層絶縁膜の下地酸化
膜に最適である。
As described above, the RTO film is most suitable as the base oxide film of the multilayer insulating film of the present invention.

〔実施例〕〔Example〕

以下に、本発明の実施例を図面に基づいて詳細に説明
する。第1図(a)〜(c)は本発明の技術を用いて作
成されたポリシリコン電極上の多層絶縁膜の形成工程を
示す断面図である。まず半導体基板1の表面上に薄いゲ
ート絶縁膜が形成されており、その上に1層目のポリシ
リコン電極3がCVD法により堆積されている(第1図
(a))。次にこのポリシリコン電極3上にRTO法よりR
TO膜4を形成する。そしてその上に薄いCVDシリコン窒
化膜5を堆積させる(第1図(b))。さらにこのCVD
シリコン窒化膜5を熱酸化して、その膜表面上に熱酸化
シリコン窒化膜6を形成させる。そして最後に2層目の
ポリシリコン電極7をCVD法により堆積させた(第1図
(c))。上記のごとくポリシリコン電極上の多層絶縁
膜を形成する場合、RTO膜は急速熱処理であるので大口
径シリコンウエハでもリン不純物濃度によらず、面内膜
厚均一性は良好である。さらにRTO膜の形成は、通常の
酸化炉でのポリシリコンの熱酸化より極めて速い(1〜
2分程度)ので通常酸化炉より高温処理しても100Å以
下の薄いゲート絶縁膜を膜質を著しく劣化させることを
防止できる。またRTO膜は短時間処理であるのでポリシ
リコンのアスペリティを発生させないという利点も持っ
ている。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. 1 (a) to 1 (c) are cross-sectional views showing steps of forming a multilayer insulating film on a polysilicon electrode formed by using the technique of the present invention. First, a thin gate insulating film is formed on the surface of a semiconductor substrate 1, and a first-layer polysilicon electrode 3 is deposited thereon by a CVD method (FIG. 1A). Next, R is formed on the polysilicon electrode 3 by the RTO method.
The TO film 4 is formed. Then, a thin CVD silicon nitride film 5 is deposited thereon (FIG. 1 (b)). Furthermore, this CVD
The silicon nitride film 5 is thermally oxidized to form a thermally oxidized silicon nitride film 6 on the film surface. Finally, a second-layer polysilicon electrode 7 was deposited by a CVD method (FIG. 1C). When a multilayer insulating film is formed on a polysilicon electrode as described above, since the RTO film is a rapid heat treatment, even in a large-diameter silicon wafer, the in-plane film thickness uniformity is good regardless of the phosphorus impurity concentration. Furthermore, the formation of the RTO film is much faster than the thermal oxidation of polysilicon in a normal oxidation furnace (1- 1).
(Approximately 2 minutes), so that even if the temperature is higher than that of an ordinary oxidation furnace, it is possible to prevent the thin gate insulating film having a thickness of 100 ° or less from significantly degrading the film quality. Further, since the RTO film is processed in a short time, there is an advantage that asperity of polysilicon is not generated.

〔発明の効果〕〔The invention's effect〕

本発明は、以上説明したように多層絶縁膜のポリシリ
コン熱酸化膜の代わりにRTO膜を用いることにより、そ
れ自体の膜厚均一性、膜質が優れており、さらに、前工
程で形成される薄いゲート絶縁膜への悪影響がほとんど
ないという、優れた特徴をもたせることが可能となっ
た。
As described above, the present invention uses the RTO film in place of the polysilicon thermal oxide film of the multilayer insulating film, thereby having excellent film thickness uniformity and film quality of itself, and further, is formed in a previous step. It is possible to provide an excellent feature that there is almost no adverse effect on a thin gate insulating film.

【図面の簡単な説明】[Brief description of the drawings]

第1図(a)〜(c)は本発明のポリシリコン電極上の
多層絶縁膜の形成工程順断面図である。 第2図(a)〜(c)は従来のポリシリコン電極上の多
層絶縁膜の形成工程順断面図である。 1……半導体基板 2……Gate絶縁膜 3……1層目のポリシリコン電極 4……RTO膜 5……CVD窒化膜 6……熱酸化シリコン窒化膜 7……2層目のポリシリコン電極
1 (a) to 1 (c) are cross-sectional views in the order of forming a multilayer insulating film on a polysilicon electrode according to the present invention. 2 (a) to 2 (c) are cross-sectional views in the order of steps of forming a multilayer insulating film on a conventional polysilicon electrode. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Gate insulating film 3 ... First layer polysilicon electrode 4 ... RTO film 5 ... CVD nitride film 6 ... Thermal silicon oxide nitride film 7 ... Second layer polysilicon electrode

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 FI H01L 29/788 29/792 (56)参考文献 特開 昭63−224367(JP,A) 特開 昭61−147576(JP,A) 特開 平1−117332(JP,A) 特開 昭64−15985(JP,A)──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 6 Identification symbol FI H01L 29/788/29/792 (56) References JP-A-63-224367 (JP, A) JP-A-61-147576 (JP, A) JP-A-1-117332 (JP, A) JP-A-64-15985 (JP, A)

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】シリコン基板上に膜厚100Åを越えない薄
いゲート絶縁膜を形成する工程と、前記薄いゲート絶縁
膜の上にゲート電極として化学気相成長(CVD)法によ
りポリシリコンを堆積する工程と、前記ポリシリコン上
で急速ランプ熱酸化(RTO)法によりシリコン酸化膜を
形成する工程と、前記シリコン酸化膜上に化学気相成長
(CVD)法によりシリコン窒化膜を堆積する工程と、前
記シリコン窒化膜上に薄い熱酸化シリコン窒化膜を形成
する工程と、前記熱酸化シリコン窒化膜上に化学気相成
長(CVD)法によりポリシリコンを堆積する工程からな
ることを特徴とする半導体装置の製造法。
1. A step of forming a thin gate insulating film having a thickness of not more than 100 ° on a silicon substrate, and depositing polysilicon as a gate electrode on the thin gate insulating film by a chemical vapor deposition (CVD) method. Forming a silicon oxide film on the polysilicon by a rapid ramp thermal oxidation (RTO) method; and depositing a silicon nitride film on the silicon oxide film by a chemical vapor deposition (CVD) method. Forming a thin thermal oxide silicon nitride film on the silicon nitride film; and depositing polysilicon on the thermal silicon oxide nitride film by chemical vapor deposition (CVD). Manufacturing method.
【請求項2】前記RTO法によりシリコン酸化膜を形成す
る工程は、ランプ加熱時間が2分以下で行われる請求項
1記載の半導体装置の製造法。
2. The method according to claim 1, wherein the step of forming the silicon oxide film by the RTO method is performed with a lamp heating time of 2 minutes or less.
【請求項3】前記RTO法によりシリコン酸化膜を形成す
る工程は、ランプ加熱温度が1000℃以上である請求項1
記載の半導体装置の製造法。
3. The step of forming a silicon oxide film by the RTO method, wherein a lamp heating temperature is 1000 ° C. or higher.
The manufacturing method of the semiconductor device described in the above.
JP1141451A 1989-06-02 1989-06-02 Semiconductor device manufacturing method Expired - Lifetime JP2739593B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1141451A JP2739593B2 (en) 1989-06-02 1989-06-02 Semiconductor device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1141451A JP2739593B2 (en) 1989-06-02 1989-06-02 Semiconductor device manufacturing method

Publications (2)

Publication Number Publication Date
JPH036022A JPH036022A (en) 1991-01-11
JP2739593B2 true JP2739593B2 (en) 1998-04-15

Family

ID=15292221

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1141451A Expired - Lifetime JP2739593B2 (en) 1989-06-02 1989-06-02 Semiconductor device manufacturing method

Country Status (1)

Country Link
JP (1) JP2739593B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06318588A (en) * 1993-03-11 1994-11-15 Nec Corp Manufacture of semiconductor device
KR100274351B1 (en) * 1997-06-30 2001-01-15 김영환 Method of gate oxide film in a semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0669099B2 (en) * 1984-12-21 1994-08-31 株式会社東芝 MIS type semiconductor device
JPH0640588B2 (en) * 1987-03-13 1994-05-25 株式会社東芝 Semiconductor memory device
JP2570324B2 (en) * 1987-10-30 1997-01-08 日本電装株式会社 Nonvolatile semiconductor memory and method of manufacturing the same

Also Published As

Publication number Publication date
JPH036022A (en) 1991-01-11

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