JP3244336B2 - Ferroelectric element - Google Patents
Ferroelectric elementInfo
- Publication number
- JP3244336B2 JP3244336B2 JP09681593A JP9681593A JP3244336B2 JP 3244336 B2 JP3244336 B2 JP 3244336B2 JP 09681593 A JP09681593 A JP 09681593A JP 9681593 A JP9681593 A JP 9681593A JP 3244336 B2 JP3244336 B2 JP 3244336B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- ferroelectric
- electrode
- ferroelectric element
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Semiconductor Memories (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、強誘電体素子の改良に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a ferroelectric device.
【０００２】[0002]
【従来の技術】従来、強誘電体素子としては、図４に示
すものが知られている。図中の符号１は、ｐ型のシリコ
ン基板である。この基板１の上には、リン，ボロン等の
不純物を含んだ酸化シリコンからなる絶縁膜２が被膜さ
れている。この絶縁膜２上には、前記絶縁膜２上に形成
された第１の電極３と、この第１の電極３の上に形成さ
れたジルコン酸チタン酸鉛（ＰＺＴ）等からなる強誘電
体膜４と、この強誘電体膜４上に形成された第２の電極
５とから構成される強誘電体素子６が形成されている。
ここで、前記第１の電極３は、前記絶縁膜２との接着層
として設けられたＴｉ，Ｔａ，ＴｉＮ等からなる下層膜
７と、Ｐｔ等からなる上層膜８とから構成されている。2. Description of the Related Art Conventionally, a ferroelectric device shown in FIG. 4 is known. Reference numeral 1 in the figure is a p-type silicon substrate. An insulating film 2 made of silicon oxide containing impurities such as phosphorus and boron is coated on the substrate 1. On the insulating film 2, a first electrode 3 formed on the insulating film 2 and a ferroelectric material made of lead zirconate titanate (PZT) formed on the first electrode 3 are formed. A ferroelectric element 6 composed of the film 4 and a second electrode 5 formed on the ferroelectric film 4 is formed.
Here, the first electrode 3 is composed of a lower film 7 made of Ti, Ta, TiN or the like provided as an adhesive layer with the insulating film 2 and an upper film 8 made of Pt or the like.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、従来の
強誘電体素子によれば、第１の電極３を成膜後にＰＺＴ
等の強誘電体膜４を成膜するため、強誘電体膜４に熱処
理を施さなければならない状況が生じた時に、熱により
第１の電極３の下層膜７もしくは絶縁膜２の強誘電体膜
４への影響が問題になっている。例えば、下層膜７とし
てＴｉ、上層膜８としてＰｔ、強誘電体膜４としてＰＺ
Ｔ、第２電極５としてＰｔを用いて強誘電体素子６を作
成した場合、強誘電体膜４を成膜後に約８００℃の熱処
理が施されるために、下層膜７のＴｉもしくは絶縁膜２
中のリン，ボロン等が上層膜８のＰｔ内を拡散して強誘
電体膜であるＰＺＴと反応し、強誘電体素子の分極特性
を劣化させる原因となっている。また、下層膜７として
Ｔａを用いても同様なことが起きる。更に、ＴｉＮを下
層膜として用いた場合には、絶縁膜２との界面では膜剥
がれが発生するという問題点が生じる。However, according to the conventional ferroelectric element, after the first electrode 3 is formed, the PZT
When the ferroelectric film 4 needs to be subjected to a heat treatment in order to form the ferroelectric film 4 or the like, the lower film 7 of the first electrode 3 or the ferroelectric film of the insulating film 2 is heated. The effect on the film 4 is a problem. For example, the lower film 7 is Ti, the upper film 8 is Pt, and the ferroelectric film 4 is PZ.
T, when the ferroelectric element 6 is formed using Pt as the second electrode 5, a heat treatment at about 800 ° C. is performed after the ferroelectric film 4 is formed. 2
Phosphorus, boron, and the like diffuse in the Pt of the upper layer film 8 and react with PZT, which is a ferroelectric film, to cause deterioration of polarization characteristics of the ferroelectric element. The same occurs when Ta is used for the lower film 7. Further, when TiN is used as the lower layer film, there is a problem that film peeling occurs at the interface with the insulating film 2.
【０００４】本発明はこうした事情を考慮してなされた
もので、電極又は絶縁膜と強誘電体膜との反応を防止
し、分極特性の劣化のない安定した強誘電体素子を提供
することを目的とする。The present invention has been made in view of such circumstances, and it is an object of the present invention to provide a stable ferroelectric element which prevents a reaction between an electrode or an insulating film and a ferroelectric film and does not deteriorate polarization characteristics. Aim.
【０００５】[0005]
【課題を解決するための手段】本発明は、基板上に絶縁
膜を介して設けられ、前記絶縁膜上に形成されかつ２つ
以上の組成からなる下層膜及び該下層膜上の上層膜から
構成される第１の電極と、この第１の電極上に形成され
た強誘電体膜と、この強誘電体膜上に形成された第２の
電極とを具備した強誘電体素子において、前記第１の電
極内の前記下層膜の組成比に勾配もたせたことを特徴と
する強誘電体素子である。SUMMARY OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, comprising: a lower film formed on an insulating film on a substrate, the lower film having two or more compositions formed on the insulating film, and an upper film formed on the lower film. A ferroelectric element comprising: a first electrode configured; a ferroelectric film formed on the first electrode; and a second electrode formed on the ferroelectric film. A ferroelectric element, wherein a composition ratio of the lower layer film in the first electrode has a gradient.
【０００６】[0006]
【作用】本発明によれば、第１の電極と絶縁膜間の密着
（膜剥がれが発生しない状態）を保ちつつ、第１の電極
の下層膜成分もしくは絶縁膜中のリン，ボロン等の第１
の電極の上層膜への拡散を防止することができ、安定し
た強誘電体膜を形成できる。また、下層膜を成膜した後
でかつ上層膜を成膜する前に熱処理を施す製造方法によ
り、上記同様に下層成分もしくは絶縁膜中のリン，ボロ
ン等の上層膜への拡散を防止することができ、安定した
強誘電体膜を形成できる。According to the present invention, while maintaining the close contact between the first electrode and the insulating film (in a state in which film peeling does not occur), the lower electrode component of the first electrode or the second electrode such as phosphorus or boron in the insulating film. 1
Can be prevented from diffusing into the upper layer film of the electrode, and a stable ferroelectric film can be formed. In addition, a method of performing heat treatment after forming the lower layer film and before forming the upper layer film to prevent diffusion of the lower layer component or the phosphorus or boron in the insulating film into the upper layer film in the same manner as described above. And a stable ferroelectric film can be formed.
【０００７】[0007]
【実施例】以下、本発明の一実施例を図１を参照して説
明する。図中の符号11は、ｐ型のシリコン基板である。
この基板１の上には、例えばリン，ボロン等の不純物を
含んだホウ素−リンケイ酸ガラス（ＢＰＳＧ）膜12が被
膜されている。このＢＰＳＧ膜12上には、前記ＢＰＳＧ
膜12上に形成された第１の電極13と、この第１の電極13
の上に形成されたジルコン酸チタン酸鉛（ＰＺＴ）から
なる強誘電体膜14と、この強誘電体膜14上に形成された
Ｐｔからなる第２の電極15とから構成される強誘電体素
子16が形成されている。ここで、前記第１の電極13は、
ＴｉＮx からなる厚み１００nmの下層膜17と、Ｐｔから
なる厚み２００nmの上層膜18とから構成されている。ま
た、前記強誘電体膜14は厚さ２００〜４００nm、第２の
電極15の厚さは約２００nmである。前記下層膜17は、Ｂ
ＰＳＧ膜12との界面では窒素がほとんど含まれていない
組成からなり、上層膜18に近づくほど窒素リッチな組成
勾配をもつ構造になっている。図２は、下層膜17の厚み
とＴｉＮx のｘ値との関係を示す特性図である。次に、
こうした構成の強誘電体素子の製造方法について説明す
る。まず、基板11上にＢＰＳＧ膜12を形成する。つづい
て、Ｔｉもしくは窒素量の少ないＴｉＮx ターゲットを
用いて、Ｎ2 ガスを反応ガスとして反応性スパッタ法に
より、Ｎ2 ガスの量を制御しながら厚み方向にｘ値が大
きくなるようにＴｉＮx からなる下層膜17を成膜した。
次に、８００℃，３０分間のアニール処理を施した後、
スパッタリング法により上層膜18を成膜した。更に、ス
パッタリング法，ゾルーゲル法，ＣＶＤ法などの手法を
用いて強誘電体膜14を成膜した。更に、強誘電体膜14上
にスパッタリング法により第２の電極15を成膜した。An embodiment of the present invention will be described below with reference to FIG. Reference numeral 11 in the drawing denotes a p-type silicon substrate.
On this substrate 1, a boron-phosphosilicate glass (BPSG) film 12 containing impurities such as phosphorus and boron is coated. On the BPSG film 12, the BPSG
A first electrode 13 formed on the film 12 and the first electrode 13
A ferroelectric film composed of a ferroelectric film 14 made of lead zirconate titanate (PZT) and a second electrode 15 made of Pt formed on the ferroelectric film 14 An element 16 is formed. Here, the first electrode 13 is
The lower layer 17 is made of TiN x and has a thickness of 100 nm, and the upper layer 18 is made of Pt and has a thickness of 200 nm. The thickness of the ferroelectric film 14 is 200 to 400 nm, and the thickness of the second electrode 15 is about 200 nm. The lower film 17 is made of B
The interface with the PSG film 12 has a composition containing almost no nitrogen, and has a structure having a nitrogen-rich composition gradient as approaching the upper layer film 18. FIG. 2 is a characteristic diagram showing the relationship between the thickness of the lower film 17 and the x value of TiN x . next,
A method for manufacturing a ferroelectric element having such a configuration will be described. First, a BPSG film 12 is formed on a substrate 11. Subsequently, using less TiN x target with Ti or nitrogen content, by reactive sputtering with N 2 gas as the reaction gas, the TiN x As x value is increased in the thickness direction while controlling the amount of N2 gas A lower film 17 was formed.
Next, after annealing at 800 ° C. for 30 minutes,
The upper layer film 18 was formed by a sputtering method. Further, the ferroelectric film 14 was formed by using a technique such as a sputtering method, a sol-gel method, and a CVD method. Further, a second electrode 15 was formed on the ferroelectric film 14 by a sputtering method.
【０００８】上記実施例に係る強誘電体素子によれば、
第１の電極13の下層膜17がＢＰＳＧ膜12との界面では窒
素がほとんど含まれていない組成からなり、上層膜18に
近づくほど窒素リッチな組成勾配をもつ構造になってい
るため、下層膜17として ＴｉＮを使用した時に発生し
たＢＰＳＧ膜12界面での膜剥がれを防止でき、かつ下層
膜17としてＴｉもしくはＴａを使用した時に発生した下
層膜材料または絶縁膜材料のＰｔ膜への拡散をＴｉＮ膜
によって防止でき、安定した強誘電体素子を実現でき
る。According to the ferroelectric element according to the above embodiment,
Since the lower film 17 of the first electrode 13 has a composition containing almost no nitrogen at the interface with the BPSG film 12 and has a structure having a nitrogen-rich composition gradient as approaching the upper film 18, the lower film 17 It is possible to prevent film peeling at the interface of the BPSG film 12 generated when TiN is used as 17 and to diffuse the lower film material or insulating film material generated when using Ti or Ta as the lower film 17 into the Pt film. It can be prevented by the film, and a stable ferroelectric element can be realized.
【０００９】図３は、本発明及び従来例に係る第１の電
極の下層膜から強誘電体膜のアニール処理までのプロセ
スチャートを示す。従来のプロセスでは下層膜と上層膜
を連続で成膜していたが、本発明によるプロセスでは上
層膜を成膜する前に強誘電体膜のアニール処理と同じ条
件のアニール処理工程（８００℃，３０分間）を追加し
た。この結果、従来プロセスで発生していた下層膜材料
又は絶縁膜材料のＰｔ膜への拡散を防止でき、安定した
強誘電体素子が可能となった。FIG. 3 shows a process chart from the lower layer film of the first electrode to the annealing of the ferroelectric film according to the present invention and the conventional example. In the conventional process, the lower film and the upper film are continuously formed. However, in the process according to the present invention, before forming the upper film, an annealing process (800 ° C., 30 minutes). As a result, it is possible to prevent the lower layer material or the insulating film material from being diffused into the Pt film, which has been generated in the conventional process, and a stable ferroelectric element has become possible.
【００１０】なお、上記実施例では、第１の電極の下層
膜がＴｉＮx 、上層膜がＰｔ、強誘電体膜がＰＺＴ、第
２の電極がＰｔからなる場合について述べたが、これに
限らず、他の材料を用いてもよいことはもちろんのこと
である。In the above embodiment, the case where the lower layer of the first electrode is made of TiN x , the upper layer is made of Pt, the ferroelectric film is made of PZT, and the second electrode is made of Pt, but is not limited to this. Of course, other materials may be used.
【００１１】[0011]
【発明の効果】以上詳述したようにこの発明によれば、
電極又は絶縁膜と強誘電体膜との反応を防止し、分極特
性の劣化のない安定した強誘電体素子を提供できる。As described in detail above, according to the present invention,
It is possible to provide a stable ferroelectric element in which a reaction between the electrode or the insulating film and the ferroelectric film is prevented and the polarization characteristics are not deteriorated.
【図１】本発明の一実施例に係る強誘電体素子の断面
図。FIG. 1 is a sectional view of a ferroelectric element according to one embodiment of the present invention.
【図２】本発明及び従来に係る下層膜の成膜から強誘電
体膜のアニール処理までのプロセスチャート。FIG. 2 is a process chart from the formation of a lower layer film to the annealing treatment of a ferroelectric film according to the present invention and the related art.
【図３】下層膜の厚みとＴｉＮx のｘ値との関係を示す
特性図。FIG. 3 is a characteristic diagram showing a relationship between a thickness of a lower layer film and an x value of TiN x .
【図４】従来の強誘電体素子の断面図。FIG. 4 is a sectional view of a conventional ferroelectric element.
11…シリコン基板、 12…ＢＰＳＧ膜、 13…
第１の電極、14…強誘電体膜、 15…第２の電
極、 16…強誘電体素子、17…下層膜、
18…上層膜。11 ... silicon substrate, 12 ... BPSG film, 13 ...
1st electrode, 14 ... ferroelectric film, 15 ... second electrode, 16 ... ferroelectric element, 17 ... lower film,
18 ... Upper layer film.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平４−92468（ＪＰ，Ａ) 特開 平５−67792（ＪＰ，Ａ) 特開 平６−200366（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 27/105 ────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-4-92468 (JP, A) JP-A-5-67792 (JP, A) JP-A-6-200366 (JP, A) (58) Field (Int.Cl. 7 , DB name) H01L 27/105
Claims (1)
絶縁膜上に形成されかつ２つ以上の組成からなる下層膜
及び該下層膜上の上層膜から構成される第１の電極と、
この第１の電極上に形成された強誘電体膜と、この強誘
電体膜上に形成された第２の電極とを具備した強誘電体
素子において、前記第１の電極内の前記下層膜の組成比
に勾配もたせたことを特徴とする強誘電体素子。A first electrode provided on a substrate via an insulating film, formed on the insulating film and including a lower film having two or more compositions, and a first electrode formed on the lower film; ,
In a ferroelectric element including a ferroelectric film formed on the first electrode and a second electrode formed on the ferroelectric film, the lower layer film in the first electrode A ferroelectric element characterized by having a gradient in the composition ratio of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP09681593A JP3244336B2 (en) | 1993-03-31 | 1993-03-31 | Ferroelectric element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP09681593A JP3244336B2 (en) | 1993-03-31 | 1993-03-31 | Ferroelectric element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06291272A JPH06291272A (en) | 1994-10-18 |
| JP3244336B2 true JP3244336B2 (en) | 2002-01-07 |
Family
ID=14175090
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP09681593A Expired - Fee Related JP3244336B2 (en) | 1993-03-31 | 1993-03-31 | Ferroelectric element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3244336B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101647432B (en) * | 2008-08-11 | 2012-08-08 | 漳州市英格尔农业科技有限公司 | Artificially synthesized lima bean pod borer sex pheromone |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5390631B2 (en) | 2009-10-27 | 2014-01-15 | キヤノンアネルバ株式会社 | Nonvolatile memory element and manufacturing method thereof |
-
1993
- 1993-03-31 JP JP09681593A patent/JP3244336B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101647432B (en) * | 2008-08-11 | 2012-08-08 | 漳州市英格尔农业科技有限公司 | Artificially synthesized lima bean pod borer sex pheromone |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06291272A (en) | 1994-10-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0563205A (en) | Semiconductor device | |
| JPH08264735A (en) | Ferroelectric capacitor | |
| JPH07153761A (en) | Wiring preparation of semiconductor element | |
| JP3244336B2 (en) | Ferroelectric element | |
| JP3432359B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3276351B2 (en) | Method for manufacturing semiconductor device | |
| JP2753170B2 (en) | Crystallization method of ferroelectric film | |
| JPH0745475A (en) | Thin film capacitor and fabrication thereof | |
| JP3142457B2 (en) | Method of manufacturing ferroelectric thin film capacitor | |
| JPH0922884A (en) | Manufacture of semiconductor element | |
| JP2739593B2 (en) | Semiconductor device manufacturing method | |
| JPH0294476A (en) | Manufacture of gate electrode of semiconductor device | |
| JPH11204757A (en) | Manufacturing semiconductor device | |
| KR100275120B1 (en) | Method for forming ferroelectric film of capacitors | |
| US20020135031A1 (en) | Method for forming a dielectric layer and semiconductor device incorporating the same | |
| JP3116048B2 (en) | Semiconductor device having ferroelectric layer and method of manufacturing the same | |
| JP3248475B2 (en) | Method of manufacturing ferroelectric nonvolatile memory cell structure | |
| JPS5984570A (en) | Manufacture of capacitor for semiconductor device | |
| JPH02113532A (en) | Semiconductor device | |
| JP2945023B2 (en) | Method for manufacturing thin film transistor | |
| JPS6248069A (en) | Semiconductor device | |
| JPS59188957A (en) | Manufacture of capacitor for semiconductor device | |
| JP3178867B2 (en) | Method for manufacturing semiconductor device | |
| JPH07221299A (en) | Manufacture of semiconductor device | |
| JP2857170B2 (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20011002 |
|
| LAPS | Cancellation because of no payment of annual fees |