JPH03222367A - Insulated gate type field effect transistor - Google Patents

Abstract

PURPOSE:To prevent a transistor of this design from deteriorating in characteristics by a method wherein a gate electrode of silicon carbide layer is formed on a one conductivity type semiconductor substrate through the intermediary of an insulating layer, and opposite conductivity type impurities are introduced into the exposed part of the substrate on the sides to form a source and drain region. CONSTITUTION:An isolation insulating layer 2 is formed on an N-type silicon substrate 1, a gate oxide film 3 is formed on the exposed surface of the substrate 1, and an SiC film 4 is formed on the entire surface. Then, a resist mask 5 is formed, and a plasma etching is carried out onto the exposed SiC film 4 to form a gate electrode 41, and then the exposed gate oxide film 3 is also etched to make the silicon substrate 1 exposed. Then, the resist mask 5 is removed, the surface of the silicon substrate 1 is treated to form an oxide film 32 on the exposed surface of the substrate 1, and a source region and drain region 6 of P-type are formed on the substrate 1. In succession, the oxide film 32 is removed, an interlaminar insulating layer 7 of phospho-silicate glass is formed on the surface of the silicon substrate 1, a contact hole 71 is formed, and a wiring 8 connected to the source and the drain regions 6 is formed to complete a transistor of this design.

Description

[Detailed description of the invention] 〔overview〕 Insulated gate field effect Regarding Seki.

The purpose is to avoid deterioration of transistor characteristics caused by contamination by gate electrode constituent materials remaining after forming a gate electrode in a transistor (IG-FET).

The structure of the 1G-FET includes a - conductivity type semiconductor substrate, a gate electrode formed on the semiconductor substrate, and
an insulating layer interposed between the gate electrode and the semiconductor substrate;
A source region and a drain region are formed by selectively introducing impurities of opposite conductivity type into the semiconductor substrate exposed on both sides of the gate electrode.

[Industrial application field]

The present invention is an insulated gate transistor (IG-FET)
In particular, the present invention relates to an IG-FET using a material having a lower resistance than polycrystalline silicon as a gate electrode.

(Prior art) With the increase in the density of semiconductor integrated circuits, the width of gate electrodes has been reduced.For this reason, lower resistance of gate electrodes is required.As a method for realizing a low resistance gate electrode, A gate electrode with a double structure called polycide, in which a silicide layer is laminated on a polycrystalline silicon layer, is in practical use.The silicide mentioned above is tungsten silicide (
WSiz).

Molybdenum silicide (MoSiz), titanium silicide (TiSiz), etc. are used. These silicides have lower resistance than polycrystalline silicon, but SiO□
Since polycrystalline silicon has excellent adhesion to the insulating layer made of polycrystalline silicon, it has the double structure as described above.

[Problems to be Solved by the Invention] The gate electrode having the above-mentioned polycide structure is obtained by sequentially depositing a polycrystalline silicon layer and a silicide layer on a silicon substrate, and then depositing these layers in one layer using, for example, hydrogen bromide/hydrogen (HBr) gas and chlorine gas. (ch
) The gate electrode is processed into a gate electrode of a predetermined size by plasma etching using a mixed gas as an etching agent. Then, a wet process is performed to remove the resist used in the etching and the residues of the etching reaction products.

Steps such as ion implantation for forming source/drain regions and formation of interlayer insulating layers are performed.

In the above-mentioned wet treatment, the silicon substrate on which the gate electrode is formed is immersed in a nitric acid solution at 70'C. do. The metal components adsorbed in this way remain without being removed even by washing with water or the like, and are then diffused into the substrate to the channel region while the silicon substrate undergoes various heat treatment steps. For this reason,
There are problems that seriously affect transistor characteristics, such as forming undesirable impurity levels and lowering the threshold voltage (V) of the IG-FET than a desired value.

An object of the present invention is to solve the problems caused by using a gate electrode having a polycide structure as described above, and to make it possible to form an IG-FET having desired characteristics.

[Means for Solving the Problems] The above object is to - provide a conductive type semiconductor substrate, a gate electrode formed on the semiconductor substrate and a silicon carbide (SiC) layer, and a structure between the gate electrode and the semiconductor substrate; and a source region and a drain region formed by selectively introducing impurities of opposite conductivity type into the semiconductor substrate exposed on both sides of the gate electrode. This is achieved by the IGFET according to the invention.

[For production]

SiC is chemically stable and is not attacked by most acids. Moreover, its specific resistance is lower than that of polycrystalline silicon. Moreover, it has excellent adhesion to insulating layers such as SiO□ layers. Therefore, it is a suitable material for gate electrodes of high-density integrated circuits, and there is no fear of producing metal components such as polycide, which are impurities that are undesirable for transistor characteristics.

It also has the advantage of being lower in cost than other chemically stable and low-resistance materials such as gold and platinum.

Furthermore, the work function difference with silicon is large, and the dark value voltage (
νth) can be obtained.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

As shown in FIG. 1(a), an isolation insulating layer 2 is formed on, for example, an n-type silicon substrate 1 by the well-known LOCO method, and the surface of the silicon substrate 1 in the element region exposed from the isolation insulating layer 2 is heated. A gate oxide film 3 is formed by oxidation.

Next, as shown in FIG. 1(b), a SiC film 4 having a thickness of about 1000 nm is formed on the metal surface of the silicon substrate 1. Then, as shown in FIG. The SiC film 4 may be formed by, for example, a well-known CVD method using trichlorosilane (SiHCh) and propane (C3HI) as source gases. An example of the formation conditions is as follows: The flow rates of 5iHCh, C, H6, and carrier gas hydrogen (H2) are 700S, respectively.
CCM40SCCM, 7000SCCM, substrate temperature 1000''C1 total gas pressure 200Pa.

Next, using the well-known glue sogelaf technique, Figure 1 (C)
As shown in the figure, a resist mask 5 corresponding to the gate electrode is formed on the SiC film 4, and the SiC film 4 exposed from the resist mask 5 is etched with plasma using nitrogen trifluoride (NFI) as an etching gas. Apply etching. As a result, as shown in FIG. 1(d).

A gate electrode 41 made of SiCp is formed. In the above etching, the gate oxide film 3 in the region exposed from the resist mask 5 is also etched, and the silicon substrate 1 is exposed.

Here, the resist mask 5 is removed, and the surface of the silicon base 1 is further treated with a nitric acid aqueous solution as in the conventional method. In this treatment, the SiC film 4 is not dissolved, and therefore is not adsorbed as an impurity on the surface of the silicon substrate 1.

Next, the exposed surface of the silicon substrate I is thermally oxidized.

As shown in FIG. 1(e), after forming the oxide film 32, the gate electrode 41 and the isolation insulating layer 2 are used as a mask.

A P-type impurity such as boron (B) is ion-implanted into the silicon substrate 1 in the element region. In this way, p-type source and drain regions 6 are formed.

Next, the oxide film 32 is removed again using a hydrofluoric acid solution. Even in this treatment, the gate electrode 41 made of the SiC film is not dissolved and is not adsorbed as an impurity on the surface of the silicon substrate 1.

After the above, as shown in FIG.
An interlayer insulating layer 7 is then formed. Then, after forming a contact hole 71 in the interlayer insulating layer 7 on the source and drain region 6, a wiring 8 connected to the source and drain region 6 through the contact hole 71 is formed on the glabella insulating layer 7. A semiconductor device according to the above is completed.

〔Effect of the invention〕

According to the present invention, deterioration of transistor characteristics due to impurities caused by polycide constituent metals dissolved in a processing solution, which occurs when a polycide structure is used, is prevented.

Furthermore, compared to the combination of a polycide-structured gate electrode and a silicon substrate, the combination of a SiC gate electrode and a silicon substrate has a larger difference in work function, and the threshold voltage (Vth) of the IG-FET is larger.

As a result, it is possible to omit the process of selective ion implantation (channel doping) performed on the region immediately below the gate electrode for adjusting the dark voltage (Vth).

[Brief explanation of drawings]

FIG. 1 is a sectional view of a main part in a process of an embodiment of the present invention. In fig. 1 is a silicon substrate, 2 is an isolation insulating layer 3 which is a gate oxide film, and 4 is a SiC film. 5 is a resist mask. 6 is a source and drain region. 7 is an interlayer insulating layer, 32 is an oxide film 41 as a gate electrode, and 71 is a contact hole. Associate figure

Claims (1)

[Scope of Claims] A semiconductor substrate of one conductivity type, a gate electrode made of a silicon carbide layer formed on the semiconductor substrate, an insulating layer interposed between the gate electrode and the semiconductor substrate, and the gate electrode. 1. An insulated gate field effect transistor comprising a source region and a drain region formed by selectively introducing impurities of opposite conductivity type into the semiconductor substrate exposed on both sides of the semiconductor substrate.