KR100274748B1 - Method for forming barrier metal film of semiconductor device - Google Patents

Method for forming barrier metal film of semiconductor device Download PDF

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Publication number
KR100274748B1
KR100274748B1 KR1019960076291A KR19960076291A KR100274748B1 KR 100274748 B1 KR100274748 B1 KR 100274748B1 KR 1019960076291 A KR1019960076291 A KR 1019960076291A KR 19960076291 A KR19960076291 A KR 19960076291A KR 100274748 B1 KR100274748 B1 KR 100274748B1
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South Korea
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film
tin
barrier metal
semiconductor device
forming
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KR1019960076291A
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Korean (ko)
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KR19980057021A (en
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문영화
홍택기
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: A method for forming barrier metal film of a semiconductor device is provided to prevent a spiking between a silicon substrate and a metal film by forming barrier metal films of Ti/TiN using O2 plasma treatment. CONSTITUTION: A gate oxide(12) and a gate electrode(13) are sequentially formed on an active region of a silicon substrate(10). An interlayer dielectric(14) having a contact hole is formed on the resultant structure. A Ti film(15) is formed on the entire surface of the resultant structure. By performing O2 plasma treatment, a TiOx film(16) is formed on the Ti film. A first TiN film(17) is formed on the TiOx film(16). A TiN2O film(18) is formed on the first TiN film(17) by performing O2 plasma treatment. A second TiN film(19) is formed on the TiN2O film(18).

Description

반도체소자의 장벽 금속막 형성방법Method of forming barrier metal film of semiconductor device

본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자의 장벽 금속막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of forming a barrier metal film of a semiconductor device.

일반적으로, 반도체 소자의 금속 배선 형성 공정에는 금속막과 실리콘 기판간의 스파이킹(spiking) 현상을 방지하기 위한 장벽 금속막 형성 공정을 포함하고 있으며, 장벽 금속막으로는 주로 Ti/TiN막이 사용되고 있다.In general, a metal wiring forming process of a semiconductor device includes a barrier metal film forming process for preventing a spiking phenomenon between a metal film and a silicon substrate, and a Ti / TiN film is mainly used as the barrier metal film.

그러나, 종래의 장벽 금속으로 사용되고 있는 Ti/TiN막을 스퍼터링(sputtering) 방식으로 증착하게 되면 후속 고온 금속막 증착시 접합 스파이킹(junction spiking)이 발생하여 누설 전류가 증가하는 문제점이 여전히 나타나고 있다.However, when the Ti / TiN film used as a barrier metal is deposited by sputtering, there is still a problem that junction spiking occurs during subsequent high temperature metal film deposition, thereby increasing leakage current.

이러한 현상은 TiN막의 주상정 구조에 기인하는데, TiN막을 전자 현미경을 통해 관찰하면 막 내에 빈 공간이 수직하게 연속적으로 배열됨을 쉽게 알 수 있다.This phenomenon is due to the columnar structure of the TiN film. When the TiN film is observed through an electron microscope, it can be easily seen that the empty spaces are arranged vertically and continuously in the film.

본 발명은 접합 스파이킹 방지를 비롯한 장벽 기능을 보다 향상시킬 수 있는 반도체 소자의 장벽 금속막 형성방법을 재공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a barrier metal film of a semiconductor device which can further improve a barrier function including preventing junction spiking.

제1(a)도 내지 제1(d)도는 본 발명의 일 실시예에 따른 반도체 소자의 금속배선 형성 공정도.1 (a) to 1 (d) is a process diagram of forming a metal wiring of a semiconductor device according to an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 실리콘 기판 11 : 소자 분리막10 silicon substrate 11 device isolation film

12 : 게이트 산화막 13 : 게이트 전극12 gate oxide film 13 gate electrode

14 : 층간 절연막 15 : Ti막14 interlayer insulating film 15 Ti film

16 : TiOx막 17 : 제1 TiN막16: TiO x film 17: First TiN film

18 : TiN20막 19 : 제2 TiN막18: TiN 2 0 film 19: second TiN film

20 : 배선 금속막20: wiring metal film

상기의 기술적 과제를 달성하기 위한 본 발명의 특징적인 반도체 소자의 장벽 금속막 형성방법은, 금속 콘택홀이 형성된 기판 전체구조 표면을 따라 Ti막을 형성하는 제1 단계; 02플라즈마 처리를 실시하여 상기 Ti막 표면에 TiOx막을 형성하는 제2 단계; 상기 TiOx막 상에 제1 TiN막을 형성하는 제3 단계; O2플라즈마 처리를 실시하여 상기 제1 TiN막 표면에 TiN20막을 형성하는 제4 단계; 및 상기 TiN2O 막 상에 제2 TiN막을 형성하는 제5 단계를 포함하여 이루어진다.According to another aspect of the present invention, there is provided a method of forming a barrier metal film of a semiconductor device, the method including: forming a Ti film along the entire surface of a substrate on which a metal contact hole is formed; Performing a 0 2 plasma treatment to form a TiO x film on the Ti film surface; Forming a first TiN film on the TiO x film; Performing a O 2 plasma treatment to form a TiN 2 0 film on the surface of the first TiN film; And a fifth step of forming a second TiN film on the TiN 2 O film.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

첨부된 도면 제1(a)도 내지 제1(e)도는 본 발명의 일 실시예에 따른 금속 배선 형성 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.1 (a) to 1 (e) of the accompanying drawings illustrate a metal wiring forming process according to an embodiment of the present invention, which will be described with reference to the following.

먼저, 제1(a)도에 도시된 바와 같이 소자 분리막(11), 게이트 산화막(12), 게이트 전극(13) 등의 소정의 하부층이 형성된 실리콘 기판(10) 상에 층간 절연막(14)을 형성하고, 이를 선택적 식각하여 금속 배선 콘택을 위한 콘택홀을 형성한다.First, as shown in FIG. 1 (a), an interlayer insulating film 14 is formed on a silicon substrate 10 on which a predetermined lower layer such as the device isolation film 11, the gate oxide film 12, and the gate electrode 13 is formed. And forming a contact hole for the metal wiring contact by selectively etching the same.

다음으로, 제1(b)도에 도시된 바와 같이 Ti막(15)을 전체구조 상부에 증착하고, 02플라즈마 처리를 실시한다. Ti막(15)은 실리콘 기판(10) 상의 활성 영역과 접촉하는 막으로서, 주로 접촉 저항을 낮추는 역할을 한다. 이때, 02플라즈마 처리는 챔버 내에 02가스를 유입한 후 플라즈마를 발생시켜 산소 원자 및 이온이 Ti막(15) 표면 부분에 침투하여 얇은 TiOx막(16)이 형성되도록 한다.Next, as shown in FIG. 1 (b), the Ti film 15 is deposited on the entire structure and subjected to 0 2 plasma treatment. The Ti film 15 is a film in contact with the active region on the silicon substrate 10 and mainly serves to lower the contact resistance. At this time, the 0 2 plasma treatment introduces 0 2 gas into the chamber and generates a plasma so that oxygen atoms and ions penetrate the surface portion of the Ti film 15 to form a thin TiO x film 16.

이어서, 제1(c)도에 도시된 바와 같이 전체구조 상부에 제1 TiN막(17)을 증착하고, 다시 O2플라즈마 처리를 실시한다. 이때, O2플라즈마 처리는 제1 TiN막(17)의 장벽 금속으로서의 기능을 향상시키기 위한 것으로, 이러한 O2플라즈마 처리에 의해 제1 TiN막(17) 표면 부분에 얇은 TiN2O(18)이 형성된다.Subsequently, as shown in FIG. 1 (c), the first TiN film 17 is deposited on the entire structure, and then subjected to O 2 plasma treatment. At this time, the O 2 plasma treatment is to improve the function of the first TiN film 17 as a barrier metal. The thin TiN 2 O 18 is deposited on the surface portion of the first TiN film 17 by the O 2 plasma treatment. Is formed.

계속하여, 제1(d)도에 도시된 바와 같이 전체구조 상부에 제2 TiN막(19)을 증착한다. 제2 TiN막(19)은 제1 TiN막(17)에 비해 산소의 이동이 적으며 금속막과의 접촉 특성을 개선하기 위한 것이다. 이때, 제1 TiN막(17)과 제2 TiN막(19)의 두께비는 1.5 : 1 이상으로 한다.Subsequently, as shown in FIG. 1 (d), a second TiN film 19 is deposited over the entire structure. The second TiN film 19 has less oxygen movement than the first TiN film 17 and is intended to improve contact characteristics with the metal film. At this time, the thickness ratio of the first TiN film 17 and the second TiN film 19 is 1.5: 1 or more.

끝으로, 제1(e)도에 도시된 바와 같이 열처리를 실시하고, 제2 TiN막(19) 상부에 배선 금속막(20)을 증착한다. 이때, 배선 금속막(20)으로는 텅스텐막 또는 알루미늄막을 사용한다.Finally, heat treatment is performed as shown in FIG. 1 (e), and the wiring metal film 20 is deposited on the second TiN film 19. At this time, a tungsten film or an aluminum film is used as the wiring metal film 20.

상기와 같은 장벽 금속막 형성 공정은 인-시츄(in-situ) 방식으로 진행이 가능하며, Ti 및 TiN의 02플라즈마 처리를 적용하여 장벽 금속으로서의 기능을 향상시킴으로써 종래 방벽 금속으로 사용되는 Ti/TiN막의 문제점인 접합 스파이킹 현상을 개선할 수 있다.The barrier metal film formation process as described above may be performed in-situ, and Ti / Ti, which is used as a barrier metal by improving the function as a barrier metal by applying 0 2 plasma treatment of Ti and TiN, may be used. The junction spiking phenomenon, which is a problem of the TiN film, can be improved.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

전술한 본 발명은 Ti/TiN막 형성시 02플라즈마 처리를 적용함으로써 Ti/TiN 구조의 장벽 금속 기능을 향상시키는 효과가 있으며, 이로 인하여 반도체 소자의 신뢰도를 향상시키는 효과가 있다.The present invention described above has the effect of improving the barrier metal function of the Ti / TiN structure by applying a 0 2 plasma treatment when forming the Ti / TiN film, thereby improving the reliability of the semiconductor device.

Claims (4)

금속 콘택홀이 형성된 기판 전체구조 표면을 따라 Ti 막을 형성하는 제1 단계; O2플라즈마 처리를 실시하여 상기 Ti막 표면에 TiOx막을 형성하는 제2 단계; 상기 TiOx막 상에 제1 TiN막을 형성하는 제3 단계; 02플라즈마 처리를 실시하여 상기 제1 TiN막 표면에 TiN2O막을 형성하는 제4 단계; 및 상기 TiN20막 상에 제2 TiN막을 형성하는 제5 단계를 포함하여 이루어진 반도체 소자의 장벽 금속막 형성방법.Forming a Ti film along the entire surface of the substrate on which the metal contact holes are formed; Performing a O 2 plasma treatment to form a TiO x film on the Ti film surface; Forming a first TiN film on the TiO x film; Performing a 0 2 plasma treatment to form a TiN 2 O film on the surface of the first TiN film; And a fifth step of forming a second TiN film on the TiN 2 0 film. 제1항에 있어서, 상기 제5 단계 수행 후, 열처리를 실시하는 제6 단계를 더 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 장벽 금속막 형성방법.The method of claim 1, further comprising a sixth step of performing a heat treatment after the fifth step is performed. 제1항 또는 제2항에 있어서, 상기 제1 단계 내지 제5 단계가, 하나의 챔버 내에서 수행되는 것을 특징으로 하는 반도체 소자의 장벽 금속막 형성밥법.The method of forming a barrier metal film of a semiconductor device according to claim 1 or 2, wherein the first to fifth steps are performed in one chamber. 제1항 또는 제2항에 있어서, 상기 제1 TiN막이, 상기 제2 TiN막에 비하여 1.5 배 이상의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 장벽 금속막 형성방법.The method of forming a barrier metal film of a semiconductor device according to claim 1 or 2, wherein the first TiN film is formed to be 1.5 times or more thicker than the second TiN film.
KR1019960076291A 1996-12-30 1996-12-30 Method for forming barrier metal film of semiconductor device KR100274748B1 (en)

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KR100318433B1 (en) * 1999-12-28 2001-12-24 박종섭 Method for forming local interconnection in ferroelectric memory device
KR100420406B1 (en) * 2001-06-30 2004-03-04 주식회사 하이닉스반도체 Oxygen stuffing method for titanium nitride layer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0350730A (en) * 1989-07-18 1991-03-05 Seiko Epson Corp Semiconductor device
JPH0536627A (en) * 1991-08-01 1993-02-12 Sony Corp Forming method of wiring
JPH05121356A (en) * 1991-09-12 1993-05-18 Sony Corp Wiring formation method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0350730A (en) * 1989-07-18 1991-03-05 Seiko Epson Corp Semiconductor device
JPH0536627A (en) * 1991-08-01 1993-02-12 Sony Corp Forming method of wiring
JPH05121356A (en) * 1991-09-12 1993-05-18 Sony Corp Wiring formation method

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