KR100401498B1 - Method of forming barrier layers in semiconductor devices - Google Patents
Method of forming barrier layers in semiconductor devices Download PDFInfo
- Publication number
- KR100401498B1 KR100401498B1 KR10-2001-0001494A KR20010001494A KR100401498B1 KR 100401498 B1 KR100401498 B1 KR 100401498B1 KR 20010001494 A KR20010001494 A KR 20010001494A KR 100401498 B1 KR100401498 B1 KR 100401498B1
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- forming
- titanium
- film
- wiring
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체장치의 배리어층 형성방법에 관한 것으로서, 특히, 배선층으로 알루미늄층을 사용할 경우 배리어층인 Ti층 또는 TiN층 표면에 산소를 플로잉시켜 산화막을 얇게 형성한 후 알루미늄층을 형성하므로서 TiAl3에 의한 배리어층과 배선층간의 접촉저항 증가를 방지하도록 한 반도체장치의 금속층/배리어층간의 접촉저항 감소방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a barrier layer of a semiconductor device. In particular, when an aluminum layer is used as a wiring layer, TiAl is formed by flowing oxygen on the surface of a Ti layer or a TiN layer as a barrier layer to form an aluminum layer and then forming an aluminum layer. The present invention relates to a method for reducing contact resistance between a metal layer and a barrier layer of a semiconductor device to prevent an increase in contact resistance between a barrier layer and a wiring layer by 3 .
본 발명에 따른 반도체장치의 배리어층 형성방법은 반도체 기판상에 티타늄막을 형성하는 제 1 단계와, 노출된 상기 티타늄막 표면에 티타늄산화막을 형성하는 제 2 단계와, 상기 티타늄산화막상에 알루미늄층을 형성하는 제 3 단계를 포함하여 이루어진다. 바람직하게, 상기 제 2 단계는 상기 티타늄막의 표면에 산소가스를 플로잉시키는 단계로 이루어지고, 상기 제 2 단계는 상기 티타늄막 표면에 산소가스 유량을 5-50sccm으로 공정시간을 10-120초 동안 흘려주는 것으로 이루어지며, 상기 제 1 단계는 상기 티타늄막 표면에 티타늄질화막을 형성하는 단계를 더 포함하여 이루어진다.A barrier layer forming method of a semiconductor device according to the present invention includes a first step of forming a titanium film on a semiconductor substrate, a second step of forming a titanium oxide film on the exposed titanium film surface, and an aluminum layer on the titanium oxide film. Forming a third step. Preferably, the second step is to flow the oxygen gas on the surface of the titanium film, the second step is the flow rate of oxygen gas on the surface of the titanium film 5-50sccm for 10-120 seconds It is made to flow, the first step further comprises the step of forming a titanium nitride film on the surface of the titanium film.
Description
본 발명은 반도체장치의 배리어층 형성방법에 관한 것으로서, 특히, 배선층으로 알루미늄층을 사용할 경우 배리어층인 Ti층 또는 TiN층 표면에 산소를 플로잉시켜 산화막을 얇게 형성한 후 알루미늄층을 형성하므로서 TiAl3에 의한 배리어층과 배선층간의 접촉저항 증가를 방지하도록 한 반도체장치의 금속층/배리어층간의 접촉저항 감소방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a barrier layer of a semiconductor device. In particular, when an aluminum layer is used as a wiring layer, TiAl is formed by flowing oxygen on the surface of a Ti layer or a TiN layer as a barrier layer to form an aluminum layer and then forming an aluminum layer. The present invention relates to a method for reducing contact resistance between a metal layer and a barrier layer of a semiconductor device to prevent an increase in contact resistance between a barrier layer and a wiring layer by 3 .
반도체소자의 고집적화에 따라 칩의 크기가 더욱 축소됨에 따라 한정된 디멘션을 갖는 칩내에서 형성되는 금속배선 형성공정 수가 증가하게 되었다. 따라서, 반도체장치에 있어서 다층 배선을 형성하는 공정이 더욱 중요한 관심사가 되었다. 다층배선 형성공정시 공정단계 수의 감소 내지는 그 단순화가 제품의 생산단가를 낮추고 다른 제품과의 경쟁력을 확보하는데 있어서 중요한 관건이다.As the size of the chip is further reduced due to the higher integration of semiconductor devices, the number of metal wiring forming processes formed in the chip having a limited dimension increases. Therefore, the process of forming a multilayer wiring in semiconductor devices has become a more important concern. Reducing or simplifying the number of process steps in the multi-layered wiring forming process is an important factor in lowering the production cost of products and securing competitiveness with other products.
일반적으로 다층금속배선 형성에 사용되는 주요 금속은 알루미늄이다. 알루미늄은 낮은 비저항값을 갖는 훌륭한 도전물질이다. 일루미늄은 보편적으로 이베포레이션(evaporation)이나 스퍼터링 방식으로 용이하게 실리콘기판 위에 증착될 수 있는 장점을 가진 금속이다.In general, the main metal used for forming multi-layer metal wiring is aluminum. Aluminum is a good conductive material with low resistivity. Aluminum is a metal with the advantage that it can be easily deposited on a silicon substrate by evaporation or sputtering.
그러나, 알루미늄 증착 온도조건이 약 400℃ 이상일 때, 증착되는 알루미늄과 기판의 실리콘이 서로 충돌하게 되어 상호 용해도 차이에 의하여 실리콘이 알루미늄 쪽으로 확산되게 된다. 이는 알루미늄내의 실리콘의 용해도(solubility)가 우세하기 때문이다. 따라서 기판에는 확산으로 빠져나간 실리콘 원자 때문에 수많은 보이드(void)가 생성되고, 결국 졍션 스파이킹과 같은 결함이 유발된다.However, when the aluminum deposition temperature condition is about 400 ° C. or more, the deposited aluminum and the silicon of the substrate collide with each other, and silicon is diffused toward the aluminum due to mutual solubility difference. This is because the solubility of silicon in aluminum prevails. As a result, a large number of voids are generated in the substrate due to the silicon atoms that escaped through diffusion, and eventually defects such as cushion spiking are caused.
졍션 스파이킹(junction spiking)은 기판의 실리콘에 형성된 보이드 속으로 알루미늄이 침투하여 얕은 졍션(shallow junction)을 뚫게 되어 마침내 졍션단락을 초래하게 되는 현상이다.Junction spiking is a phenomenon in which aluminum penetrates into the voids formed in the silicon of the substrate and penetrates a shallow junction, resulting in a junction short circuit.
따라서, 졍션 스파이킹을 방지하기 위하여 알루미늄과 실리콘 사이에 확산방지용 배리어층이 필요하다. 대표적인 확산방지용 배리어층으로 Ti 또는 TiN이 사용되며, TiN층 형성방법은 먼저, 기판 위에 Ti층을 증착한 다음 그 위에 확상방지용 TiN을 증착한 후 후속 열처리를 실시하여 TiSi2를 형성하여 금속실리사이드 화합물을 형성한다.Therefore, a diffusion barrier layer between aluminum and silicon is needed to prevent cushion spikes. Representative diffusion-proof barrier layer of Ti or TiN is used, TiN layer forming method, first, depositing a Ti layer on the substrate then the above depositing a hwaksang preventing TiN by performing a subsequent heat treatment to form a TiSi 2 metal silicide compound To form.
그러나, 실리콘기판상에 배리어층으로 Ti층을 형성한 후 배선층으로 Al층을 형성하게되면 후속 열처리공정에서 Ti와 Al이 반응하여 TiAl3를 형성하게 된다.However, if the Ti layer is formed as a barrier layer on the silicon substrate and then the Al layer is formed as the wiring layer, Ti and Al react with each other in the subsequent heat treatment to form TiAl 3 .
이러한 반응 부산물인 TiAl3는 배선층인 Al층과 배리어층인 Ti층 사이에 개재되어 면저항이 증가하여 결국 배선저항이 증가하고, 또한, TiAl3막이 불균일하게 형성되어 배선 패터닝을 위한 식각시 후속공정의 재현성이 불량해진다.The reaction by-product TiAl 3 is interposed between the Al layer as the wiring layer and the Ti layer as the barrier layer, thereby increasing the sheet resistance and eventually increasing the wiring resistance. Also, the TiAl 3 film is formed nonuniformly, and the subsequent process during etching for wiring patterning is performed. The reproducibility is poor.
도 1a 내지 도 1b는 종래 기술에 따른 반도체장치의 배리어층 형성방법을 도시하는 공정단면도이다.1A to 1B are cross-sectional views illustrating a method of forming a barrier layer of a semiconductor device according to the prior art.
도 1a를 참조하면, 반도체기판인 실리콘기판(10)의 도전영역(표시안함)상에 배리어층(11)으로 Ti층(11)을 스퍼터링, 화학기상증착 등로 증착하여 형성한다. 이때, Ti는 확산방지용 배리어층을 형성하기 위한 소스금속(source metal)이다.Referring to FIG. 1A, the Ti layer 11 is formed on the conductive region (not shown) of the silicon substrate 10 as a semiconductor substrate by sputtering, chemical vapor deposition, or the like as the barrier layer 11. In this case, Ti is a source metal for forming the diffusion barrier layer.
그러나, Ti층(11)은 후속 열처리공정에 의하여 배선층인 알루미늄층과 반응하여 TiAl3를 형성하게 되어 배선층과 배선층간의 면저항이 증가한다.However, the Ti layer 11 reacts with the aluminum layer, which is the wiring layer, to form TiAl 3 by a subsequent heat treatment, thereby increasing the sheet resistance between the wiring layer and the wiring layer.
선택적으로, Ti층(11)상에 TiN층을 형성할 수 있다. TiN층은 Ti층 표면을 질화시키거나 스퍼터링 등의 방법으로 새로이 증착하여 형성할 수 있다.Alternatively, a TiN layer can be formed on the Ti layer 11. The TiN layer may be formed by newly depositing a Ti layer surface by nitriding or sputtering.
도 1b를 참조하면, 배리어층(11)인 Ti층(11)상에 배선층으로 알루미늄층(12)을 스퍼터링 등의 방법으로 증착하여 형성한다.Referring to FIG. 1B, the aluminum layer 12 is formed on the Ti layer 11, which is the barrier layer 11, by a sputtering method or the like as a wiring layer.
그러나, 상술한 확산방지용 배리어금속층 형성방법은 반응 부산물인 TiAl3는 배선층인 Al층과 배리어층인 Ti층 사이에 개재되어 면저항이 증가하여 결국 배선저항이 증가하고, 또한, TiAl3막이 불균일하게 형성되어 배선 패터닝을 위한 식각시 후속공정의 재현성이 불량한 문제점이 있다.However, in the above-described method for forming the barrier metal layer for preventing diffusion, TiAl 3 as a reaction byproduct is interposed between the Al layer as the wiring layer and the Ti layer as the barrier layer, thereby increasing the sheet resistance and eventually increasing the wiring resistance, and forming the non-uniform TiAl 3 film. Therefore, there is a problem in that reproducibility of subsequent processes is poor when etching for wiring patterning.
따라서, 본 발명의 목적은 배선층으로 알루미늄층을 사용할 경우 배리어층인 Ti층 또는 TiN층 표면에 산소를 플로잉시켜 산화막을 얇게 형성한 후 알루미늄층을 형성하므로서 TiAl3에 의한 배리어층과 배선층간의 접촉저항 증가를 방지하도록 한 반도체장치의 금속층/배리어층간의 접촉저항 감소방법을 제공하는데 있다.Accordingly, an object of the present invention is to contact the barrier layer with TiAl 3 and the wiring layer by forming an aluminum layer after forming a thin oxide film by flowing oxygen on the surface of the Ti layer or TiN layer as the barrier layer when the aluminum layer is used as the wiring layer. A method of reducing contact resistance between a metal layer and a barrier layer of a semiconductor device to prevent an increase in resistance is provided.
상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 배리어층 형성방법은 반도체 기판상에 티타늄막을 형성하는 제 1 단계와, 노출된 상기 티타늄막 표면에 티타늄산화막을 형성하는 제 2 단계와, 상기 티타늄산화막상에 알루미늄층을 형성하는 제 3 단계를 포함하여 이루어진다.The barrier layer forming method of the semiconductor device according to the present invention for achieving the above object comprises a first step of forming a titanium film on a semiconductor substrate, a second step of forming a titanium oxide film on the exposed titanium film surface, and the titanium And a third step of forming an aluminum layer on the oxide film.
바람직하게, 상기 제 2 단계는 상기 티타늄막의 표면에 산소가스를 플로잉시키는 단계로 이루어지고, 상기 제 2 단계는 상기 티타늄막 표면에 산소가스 유량을 5-50sccm으로 공정시간을 10-120초 동안 흘려주는 것으로 이루어지며, 상기 제 1 단계는 상기 티타늄막 표면에 티타늄질화막을 형성하는 단계를 더 포함하여 이루어진다.Preferably, the second step is to flow the oxygen gas on the surface of the titanium film, the second step is the flow rate of oxygen gas on the surface of the titanium film 5-50sccm for 10-120 seconds It is made to flow, the first step further comprises the step of forming a titanium nitride film on the surface of the titanium film.
도 1a 내지 도 1b는 종래 기술에 따른 반도체장치의 배리어층 형성방법을 도시하는 공정단면도1A to 1B are cross-sectional views illustrating a method of forming a barrier layer of a semiconductor device according to the prior art.
도 2a 내지 도 2c는 본 발명에 따른 반도체장치의 배리어층 형성방법을 도시하는 공정단면도[도면의 주요부분에 대한 부호설명]10 : 실리콘기판 21 : Ti층22 : 티타늄산화막 23 : 알루미늄층2A to 2C are cross-sectional views showing a method for forming a barrier layer of a semiconductor device according to the present invention [symbol description of major parts of the drawing] 10: silicon substrate 21: Ti layer 22: titanium oxide film 23: aluminum layer
본 발명은 반도체장치의 배선층의 상부 또는 하부에 형성되는 확산방지용 배리어금속층 형성방법에 관한 것으로서, Al 배선층의 하지층을 Ti 또는 TiN으로 형성할 경우, 배리어층 형성 후 배선층 형성전에 산소 플로잉공정을 추가하므로 배선층과 배리어층 사이에 얇은 산화막을 균일하게 형성하여 TiAl3의 형성을 방지하므로 계면에서의 면저항 증가를 방지한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a barrier metal layer for diffusion prevention formed on or under a wiring layer of a semiconductor device. When forming an underlayer of an Al wiring layer with Ti or TiN, an oxygen flow process is performed after formation of the barrier layer and before formation of the wiring layer. In addition, a thin oxide film is uniformly formed between the wiring layer and the barrier layer to prevent the formation of TiAl 3 , thereby preventing an increase in sheet resistance at the interface.
즉, 본 발명은 반도체장치 제조공정중 알루미늄/아크층을 이용하여 배선 드을 형성하기 위하여 Al층의 하지층인 배리어층으로 Ti(titanium)을 사용할 경우 후속 열처리시 TiAl3가 불균일하게 형성되어 배선의 면저항이 증가하는 문제점을, 하지층인 Ti층 표면에 얇은 티타늄산화막을 산소와 접촉시켜 형성하여 Ti층과 Al층간의 반응을 방해하므로 배선의 면저항 증가를 감소시킨다. 또한, 본 발명은 하지층으로 Ti/TiN을 형성한 경우에도 적용할 수 있다.That is, in the present invention, when Ti (titanium) is used as the barrier layer, which is the base layer of the Al layer, to form the interconnection layer using the aluminum / arc layer during the semiconductor device manufacturing process, the TiAl 3 is unevenly formed during the subsequent heat treatment. The problem that the sheet resistance is increased is formed by contacting oxygen with a thin titanium oxide film on the surface of the Ti layer, which is the underlying layer, thereby preventing the reaction between the Ti layer and the Al layer, thereby increasing the sheet resistance of the wiring. In addition, this invention is applicable also when Ti / TiN is formed from an underlayer.
현재 알루미늄으로 배선을 형성할 경우 알루미늄층의 하지층으로 Ti층을 널리 사용하고 있다. Ti층을 하지층으로 사용할 경우, 그 위에 형성되는 Al층의 (111) 방향성이 우수하여 전자이동현상(electromigration)에 대한 내구성이 증가하여 배선의 수명이 길어진다.Currently, when wiring is formed of aluminum, the Ti layer is widely used as the base layer of the aluminum layer. When the Ti layer is used as the underlayer, the (111) orientation of the Al layer formed thereon is excellent, so that the durability against electromigration is increased and the life of the wiring is long.
따라서, 본 발명에서는 Al층의 하지층으로 Ti(또는 Ti/TiN)을 사용할 경우, 하지층인 Ti층 형성 후 산소가스 플로잉공정을 추가하여 Ti층 표면에 티타늄산화막을 인위적으로 형성한다. 이때, 티타늄산화막의 형성 정도는 산소가스의 유량(flowing rate)이나 플로잉 진행시간을 이용하여 정량적인 제어가 가능하다. 따라서, Ti층과 Al층 사이 계면에 티타늄산화막이 위치하므로 후속 열공정이 의한 Ti층과 Al층의 반응을 완화시켜 배선의 면저항 증가를 감소시킴에 따라 배선 저항을 감소시킨다. 그 결과, 본 발명에서는 불균일하게 형성되는 TiAl3막의 형성을 방지하여 배선 형성용 금속층(Al층) 패터닝 제어가 용이해진다.Therefore, in the present invention, when using Ti (or Ti / TiN) as the base layer of the Al layer, a titanium oxide film is artificially formed on the surface of the Ti layer by adding an oxygen gas flow step after the Ti layer is formed. At this time, the degree of formation of the titanium oxide film can be quantitatively controlled by using a flow rate of oxygen gas or a flow progress time. Therefore, since the titanium oxide film is located at the interface between the Ti layer and the Al layer, the wiring resistance is reduced by reducing the increase of the sheet resistance of the wiring by mitigating the reaction between the Ti layer and the Al layer by a subsequent thermal process. As a result, in the present invention, the formation of the non-uniformly formed TiAl 3 film is prevented and the wiring layer forming metal layer (Al layer) patterning control is facilitated.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명에 따른 반도체장치의 배리어층 형성방법을 도시하는 공정단면도이다.2A to 2C are cross-sectional views showing a method of forming a barrier layer of a semiconductor device according to the present invention.
도 2a를 참조하면, 반도체기판인 실리콘기판(10)의 도전영역(표시안함)을 포함하는 기판상에 배리어층(21)으로 Ti층(21)을 스퍼터링, 화학기상증착 등로 증착하여 형성한다. 이때, Ti는 확산방지용 배리어층을 형성하기 위한 소스금속(source metal)이다.Referring to FIG. 2A, the Ti layer 21 is formed on the substrate including the conductive region (not shown) of the silicon substrate 10 as a semiconductor substrate by sputtering, chemical vapor deposition, or the like. . In this case, Ti is a source metal for forming the diffusion barrier layer.
그러나, Ti층(21)은 후속 열처리공정에 의하여 배선층인 알루미늄층과 반응하여 TiAl3를 형성하게 되어 배선층과 배선층간의 면저항이 증가한다.However, the Ti layer 21 reacts with the aluminum layer as the wiring layer by a subsequent heat treatment to form TiAl 3 , thereby increasing the sheet resistance between the wiring layer and the wiring layer.
선택적으로, Ti층(21)상에 TiN층(도시안함)을 형성할 수 있다. TiN층은 Ti층 표면을 질화시키거나 스퍼터링 등의 방법으로 새로이 증착하여 형성할 수 있다.Alternatively, a TiN layer (not shown) may be formed on the Ti layer 21. The TiN layer may be formed by newly depositing a Ti layer surface by nitriding or sputtering.
도 2b를 참조하면, Ti층 표면을 산화시켜 티타늄산화막(22)을 형성한다. 이때, 티타늄산화막(22)의 형성은 Ti층 표면에 산소가스를 플로잉시켜 형성할 수 있고, 그 형성조건은 반응챔버내로 산소가스 유량을 5-50sccm으로 공정시간을 10-120초 동안 흘려주고, 적정조건은 알루미늄층 형성의 생산량이 감소하지 않도록 결정한다. 상기에서, 반응챔버는 Ti층(21) 증착용 챔버를 그대로 이용하거나, 별도의 반응챔버를 사용할 수 있다.Referring to FIG. 2B, the titanium layer surface is oxidized to form a titanium oxide film 22. At this time, the formation of the titanium oxide film 22 may be formed by flowing oxygen gas on the surface of the Ti layer, and the forming condition is that the flow rate of oxygen gas flows into the reaction chamber at a flow rate of 5-50 sccm for 10-120 seconds. The titration conditions determine that the output of aluminum layer formation is not reduced. In the above, the reaction chamber may use a chamber for depositing the Ti layer 21 as it is or may use a separate reaction chamber.
도 2c를 참조하면, 티타늄산화막(22)상에 배선층으로 알루미늄층(23)을 스퍼터링 등의 방법으로 증착하여 형성한다. 따라서, 알루미늄층(23)과 Ti층(21) 계면에는티타늄산화막(22)이 위치하여 열공정 등의 후속공정에서 TiAl3가 형성되는 것이 방지된다.Referring to FIG. 2C, the aluminum layer 23 is formed on the titanium oxide film 22 by a sputtering method as a wiring layer. Therefore, the titanium oxide film 22 is positioned at the interface between the aluminum layer 23 and the Ti layer 21 to prevent the formation of TiAl 3 in a subsequent process such as a thermal process.
따라서, 본 발명은 Ti층과 Al층 사이 계면에 티타늄산화막을 형성시켜 후속 열공정이 의한 Ti층과 Al층의 반응을 배제하므로 배선의 면저항 증가를 감소시킴에 따라 배선 저항을 감소시키고, 또한, 불균일하게 형성되는 TiAl3막의 형성을 방지하여 배선 형성용 금속층(Al층) 패터닝 제어가 용이한 장점이 있다.Therefore, the present invention forms a titanium oxide film at the interface between the Ti layer and the Al layer, thereby excluding the reaction between the Ti layer and the Al layer by the subsequent thermal process, thereby reducing the wiring resistance as the sheet resistance of the wiring increases, and also the nonuniformity. By preventing the formation of the TiAl 3 film to be formed, there is an advantage in that the wiring layer metallization (Al layer) patterning control is easy.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2001-0001494A KR100401498B1 (en) | 2001-01-11 | 2001-01-11 | Method of forming barrier layers in semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2001-0001494A KR100401498B1 (en) | 2001-01-11 | 2001-01-11 | Method of forming barrier layers in semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20020060420A KR20020060420A (en) | 2002-07-18 |
| KR100401498B1 true KR100401498B1 (en) | 2003-10-17 |
Family
ID=27691361
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2001-0001494A KR100401498B1 (en) | 2001-01-11 | 2001-01-11 | Method of forming barrier layers in semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100401498B1 (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0350730A (en) * | 1989-07-18 | 1991-03-05 | Seiko Epson Corp | Semiconductor device |
| KR920001658A (en) * | 1990-06-29 | 1992-01-30 | 김광호 | Metal wiring formation method using amorphous titanium nitride film |
| JPH04196122A (en) * | 1990-11-26 | 1992-07-15 | Seiko Epson Corp | Manufacture of semiconductor device |
| JPH04280425A (en) * | 1991-03-07 | 1992-10-06 | Sony Corp | Wiring formation |
| KR940016499A (en) * | 1992-12-31 | 1994-07-23 | 김주영 | Method of forming barrier metal layer of semiconductor device |
| KR19980026305A (en) * | 1996-10-09 | 1998-07-15 | 김영환 | Metal wiring formation method of semiconductor device |
| KR20000062522A (en) * | 1999-02-03 | 2000-10-25 | 조셉 제이. 스위니 | Tailoring of a wetting/barrier layer to reduce electromigration in an aluminum interconnect |
-
2001
- 2001-01-11 KR KR10-2001-0001494A patent/KR100401498B1/en not_active IP Right Cessation
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0350730A (en) * | 1989-07-18 | 1991-03-05 | Seiko Epson Corp | Semiconductor device |
| KR920001658A (en) * | 1990-06-29 | 1992-01-30 | 김광호 | Metal wiring formation method using amorphous titanium nitride film |
| JPH04196122A (en) * | 1990-11-26 | 1992-07-15 | Seiko Epson Corp | Manufacture of semiconductor device |
| JPH04280425A (en) * | 1991-03-07 | 1992-10-06 | Sony Corp | Wiring formation |
| KR940016499A (en) * | 1992-12-31 | 1994-07-23 | 김주영 | Method of forming barrier metal layer of semiconductor device |
| KR19980026305A (en) * | 1996-10-09 | 1998-07-15 | 김영환 | Metal wiring formation method of semiconductor device |
| KR20000062522A (en) * | 1999-02-03 | 2000-10-25 | 조셉 제이. 스위니 | Tailoring of a wetting/barrier layer to reduce electromigration in an aluminum interconnect |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20020060420A (en) | 2002-07-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2811131B2 (en) | Wiring connection structure of semiconductor device and method of manufacturing the same | |
| KR100457843B1 (en) | Method for forming a contact | |
| KR0179827B1 (en) | Method of forming metal interconnector in semiconductor device | |
| KR100290467B1 (en) | Method of forming a metal barrier film in a semiconductor device | |
| KR100401498B1 (en) | Method of forming barrier layers in semiconductor devices | |
| KR100632115B1 (en) | Method for forming the metal interconnection of semiconductor device | |
| KR100243291B1 (en) | Method for forming silicide layers in processes fabricating a semiconductor device | |
| JP2002026021A (en) | Method of forming metal pattern of semiconductor device | |
| KR100724143B1 (en) | Method of forming a barrier layer in a semiconductor device | |
| KR0156126B1 (en) | Formation method of contact hole in semiconductor device | |
| KR100338106B1 (en) | Method for forming meta wiring in semiconductor device | |
| KR100399066B1 (en) | Method for aluminium-alloy in semiconductor device | |
| KR100850075B1 (en) | Method for fabricating semiconductor device | |
| KR100248620B1 (en) | Method for manufacturing wiring of semiconductor device | |
| KR100220947B1 (en) | Forming method for metal wiring of semiconductor device | |
| KR100210898B1 (en) | Process for forming metal interconnection in semiconductor device | |
| KR0167237B1 (en) | Method for wiring line on a semiconductor device | |
| JP3085745B2 (en) | Method for manufacturing semiconductor device | |
| KR20010003789A (en) | Method of forming an inter-layer insulating film in a semiconductor device | |
| KR0172283B1 (en) | Method of forming metal wire of a semiconductor device | |
| KR100252915B1 (en) | Metal line of semiconductor device and method for fabricating the same | |
| KR100443363B1 (en) | Method of forming metal interconnection in semiconductor device | |
| JP2765625B2 (en) | Method of manufacturing semiconductor device and method of preventing corrosion of Ti film in through hole | |
| KR19990059072A (en) | Method of forming barrier metal layer of semiconductor device | |
| JPH05160068A (en) | Manufacture of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| LAPS | Lapse due to unpaid annual fee |