KR100414745B1 - Method for forming metal interconnection of semiconductor device - Google Patents
Method for forming metal interconnection of semiconductor device Download PDFInfo
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- KR100414745B1 KR100414745B1 KR1019960079961A KR19960079961A KR100414745B1 KR 100414745 B1 KR100414745 B1 KR 100414745B1 KR 1019960079961 A KR1019960079961 A KR 1019960079961A KR 19960079961 A KR19960079961 A KR 19960079961A KR 100414745 B1 KR100414745 B1 KR 100414745B1
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- layer
- nitride layer
- titanium
- forming
- contact hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
Abstract
Description
본 발명은 반도체소자의 금속배선 형성 방법에 관한것으로, 특히 확산방지막으로 티타늄층, 티타늄 나이트라이드층 및 알루미늄 나이트라이드층의 적층 구조로 형성하고 그 상부에 상부 금속층을 증착하는 금속 배선 형성 방법에 관한것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring of a semiconductor device, and more particularly, to a metal wiring forming method for forming a multilayer structure of a titanium layer, a titanium nitride layer, and an aluminum nitride layer as a diffusion barrier and depositing an upper metal layer thereon. will be.
반도체소자의 금속 배선을 하부에 있는 도전배선으로 콘택하기 위해 콘택홀을 형성하고, 콘택홀의 표면에 확산방지막을 형성한다음, 그 상부에 상부 금속층을 증착한다.A contact hole is formed in order to contact the metal wiring of the semiconductor element with the lower conductive wiring, a diffusion barrier film is formed on the surface of the contact hole, and then an upper metal layer is deposited thereon.
도1을 참조하여 금속 배선을 하부도전 배선에 콘택하는 것을 설명하기로 한다. 하부 도전배선(1) 상부에 절연막(2)을 형성하고, 콘택영역에 해당되는 상기 절연막(2)을 식각하여 콘택홀(3)을 형성하고, 상기 콘택홀(3)의 저부면과 상기 절연막(2)의 표면에 확산방지막으로 티타늄층(4)과 티타늄 나이트라이드층(5)을 적층하고, 그 상부에 상부 금속층(6)으로 알루미늄층 또는 텅스텐층을 증착한다.Referring to FIG. 1, the contact of the metal wiring to the lower conductive wiring will be described. An insulating film 2 is formed on the lower conductive wiring 1, the insulating film 2 corresponding to the contact region is etched to form a contact hole 3, a bottom surface of the contact hole 3 and the insulating film. A titanium layer 4 and a titanium nitride layer 5 are laminated on the surface of (2) as a diffusion barrier, and an aluminum layer or a tungsten layer is deposited on top of the upper metal layer 6.
상기 확산방지막은 상부 금속층(6)을 증착할때 하부 도전배선(1) 예를들어 실리콘 기판과 접합 스파이크 현상을 방지하고, 상부 금속층(6)이 상기 절연막(2)의 표면에서는 잘 증착되지 않기 때문에 형성하는 것이다.The diffusion barrier prevents the lower conductive wiring (1), for example, the junction spike with the silicon substrate when depositing the upper metal layer (6), the upper metal layer (6) is not well deposited on the surface of the insulating film (2) Because of that.
한편, 콘택홀의 크기가 작아짐에 따라 상부 금속충의 스텝 커버리지가 저하되는데 스텝 커버리지를 증대시키기 위하여 PVD(physical vapor deposition)법을 이용하여 알루미늄 합금을 증착할때 고온 증착 공정이 이용되어야만 작은 콘택홀의 매립이 가능할 수 있다. 한편, 상기 고온 공정이 진행될경우 확산방지막의 두께를 증가시켜야 한다.On the other hand, as the contact hole size decreases, the step coverage of the upper metal worm decreases. In order to increase the step coverage, when the aluminum alloy is deposited by using a physical vapor deposition (PVD) method, a high temperature deposition process must be used to fill a small contact hole. It may be possible. On the other hand, when the high temperature process is performed to increase the thickness of the diffusion barrier.
그러나, 확산방지막의 두께가 증가할수록 실제 콘택홀의 크기는 상대적으로 작아지고 알루미늄을 이용한 금속 배선 공정에서 콘택홀 매립은 점점 어려워지고 있다.However, as the thickness of the diffusion barrier increases, the size of the actual contact hole becomes relatively small, and contact hole filling becomes more difficult in a metal wiring process using aluminum.
본 발명은 상기한 문제점을 해결하기 위하여 확산방지막으로 이용되는 티타늄층과 티타늄 나이트라이드층의 적층 구조 상부에 알루미늄 나이트라이드층을 증착한다음, 그 상부에 상부 금속층을 증착하는 금속 배선 형성 방법을 제공하는 데 그 목적이 있다.The present invention provides a metal wiring formation method for depositing an aluminum nitride layer on top of the laminated structure of the titanium layer and the titanium nitride layer used as a diffusion barrier in order to solve the above problems. Its purpose is to.
도 1은 종래 기술에 의해 하부 도전배선 상부에 확산방지막과 상부 금속층을 증착한 것을 도시한 단면도이다.1 is a cross-sectional view illustrating the deposition of a diffusion barrier layer and an upper metal layer on an upper portion of a lower conductive line by a conventional technique.
도 2는 본 발명에 의해 하부 도전배선 상부에 확산방지막과 상부 금속층을 증착한 것을 도시한 단면도이다.2 is a cross-sectional view illustrating the deposition of the diffusion barrier and the upper metal layer on the lower conductive wiring according to the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
1 : 하부 도전배선 2 : 절연막1: lower conductive wiring 2: insulating film
3 : 콘택홀 4 : 티타늄층3: contact hole 4: titanium layer
5 : 티타늄 나이트라이드층 6 : 상부 금속층5: titanium nitride layer 6: upper metal layer
10 : 알루미늄 나이트라이드층10: aluminum nitride layer
상기한 목적을 달성하기 위한 본 발명은 하부 도전배선 상부에 절연막을 형성하고, 상기 절연막의 일정부분을 식각하여 콘택홀을 형성하는 단계와,The present invention for achieving the above object is to form an insulating film on the lower conductive wiring, forming a contact hole by etching a portion of the insulating film,
상기 콘택홀을 포함하는 절연막상부에 확산방지막을 형성하는 단계와,Forming a diffusion barrier over the insulating film including the contact hole;
상부 금속층으로 알루미늄층을 증착하는 금속 배선 형성 방법에 있어서,In the metal wiring formation method of depositing an aluminum layer with an upper metal layer,
상기 확산방지막은 티타늄층, 티타늄 나이트라이드층 및 알루미늄 나이트라이드층의 적층 구조로 형성하는 것이다.The diffusion barrier layer is formed of a laminated structure of a titanium layer, a titanium nitride layer, and an aluminum nitride layer.
상기 확산방지막의 티타늄층과 티타늄 나이트라이드층은 물리증착법을 이용하여 각각 증착하는 것이다.The titanium layer and the titanium nitride layer of the diffusion barrier are deposited by physical vapor deposition, respectively.
확산방지막 표면에 알루미늄층을 증착할때 확산방지막의 붕괴는 알루미늄 나이트라이드막이 티타늄 나이트라이드층의 계면에 형성되면서 급속히 진행되기 때문이다. 따라서, 본 발명은 이와같은 알루미늄 나이트라이드층을 미리 티타늄 나이트라이드층표면에 미리 형성시켜 알루미늄 증착시 상기와같은 알루미늄 나이트라이드가 생성되지 않도록 하는 것이다.When the aluminum layer is deposited on the surface of the diffusion barrier film, the collapse of the diffusion barrier film is rapidly progressed as the aluminum nitride film is formed at the interface of the titanium nitride layer. Therefore, in the present invention, such an aluminum nitride layer is formed on the surface of the titanium nitride layer in advance so that the aluminum nitride is not produced when the aluminum is deposited.
참고로, 알루미늄 나이트라이드층이 그상부에 증착되는 알루미늄과 반응하여 티타늄 알루미늄 나이트라이드(TiAlN)를 형성할수 있다. 그러나 티타늄 알루미늄 나이트라이드층은 확산방지 효과를 증대시키는 효과가 있는 것이며, 도전성 박막이므로 콘택 저항이 오히려 감소된다.For reference, an aluminum nitride layer may react with aluminum deposited thereon to form titanium aluminum nitride (TiAlN). However, the titanium aluminum nitride layer has an effect of increasing the diffusion preventing effect, and because the conductive thin film, the contact resistance is rather reduced.
상술한 목적 및 특징들, 장점은 첨부된 도면과 관련한 다음의 상세한 설명을 통하여 보다 분명해 질 것이다. 이하 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하면 다음과 같다.The above objects, features, and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도2는 본 발명에 의해 하부도전 배선에 콘택되는 상부 금속층을 형성한 것을 도시한 단면도로서, 하부 도전배선(1) 상부에 절연막(2)을 형성하고, 콘택영역에 해당되는 상기 절연막(2)을 식각하여 콘택홀(3)을 형성하고, 상기 콘택홀(3)의 저부면과 상기 절연막(2)의 표면에 확산방지막으로 티타늄층(4), 티타늄 나이트라이드층(5) 및 알루미늄 나이트라이드층(10)을 적층하고, 그 상부에 상부 금속층(6)으로 알루미늄층을 증착한 것이다.FIG. 2 is a cross-sectional view showing an upper metal layer contacting a lower conductive wiring according to the present invention, wherein an insulating film 2 is formed over the lower conductive wiring 1, and the insulating film 2 corresponding to the contact region is formed. To form a contact hole (3), and the titanium layer (4), titanium nitride layer (5) and aluminum nitride as a diffusion barrier on the bottom surface of the contact hole (3) and the surface of the insulating film (2) The layer 10 is laminated, and an aluminum layer is deposited on top of the upper metal layer 6.
상기 티타늄층(4)과 티타늄 나이트라이드층(5)은 물리증착법을 이용하며 100-1000Å의 두께로 증착하고, 상기 알루미늄 나이트라이드층(10)은 반응성 스퍼터링법으로 증착할때 아르곤과 질소를 1 : 3 내지 1 : 7의 비율의 분위기, 1 - 10 mTorr의 압력과, 25- 550℃의 온도에서 증착하며, 상기 상기 알루미늄 나이트라이드층(10)에서 실리콘이 0.1-3%, 구리가 0.1-2% 포함될수 있다. 참고로, 상기 아르곤과 질소에 소량의 수소를 흘려주어 환원성 분위기를 만들어 주어도 된다.The titanium layer 4 and the titanium nitride layer 5 are deposited using a physical vapor deposition method to a thickness of 100-1000 Å, and the aluminum nitride layer 10 is formed of argon and nitrogen when deposited by reactive sputtering. : 3 to 1: 7 atmosphere, a pressure of 1-10 mTorr, and deposition at a temperature of 25-550 ℃, 0.1-3% silicon in the aluminum nitride layer 10, 0.1- copper 2% may be included. For reference, a small amount of hydrogen may be flowed into the argon and nitrogen to create a reducing atmosphere.
본 발명은 하부 도전층이 노출되는 콘택홀 상부에 금속 배선을 증착하기 전에 확산방지막으로 티타늄층, 티타늄 나이트라이드층 및 알루미늄 나이트라이드층의 적층구조로 형성하여 상기 확산방지막 상부에 상부 금속층으로 알루미늄층을 증착할때 알루미늄 나이트라이드층과는 반응이 일어나지 않아 티타늄 나이트라이드층이 소모되지 않도록 함으로써 티타늄 나이트라이드층의 두께를 얇은 두께로 형성할 수 있다.According to an embodiment of the present invention, an aluminum layer is formed as a top metal layer on the diffusion barrier layer by forming a laminate structure of a titanium layer, a titanium nitride layer, and an aluminum nitride layer as a diffusion barrier layer before depositing a metal wire on the upper contact hole where the lower conductive layer is exposed. When the deposition of the aluminum nitride layer does not occur so that the titanium nitride layer is not consumed to form a thin thickness of the titanium nitride layer.
아울러 본 발명의 바람직한 실시예들은 예시의 목적을 위해 개시된 것이며, 당업자라면 본 발명의 사상과 범위안에서 다양한 수정, 변경, 부가등이 가능할 것이며, 이러한 수정 변경 등은 이하의 특허 청구의 범위에 속하는 것으로 보아야 할 것이다.In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the following claims You will have to look.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960079961A KR100414745B1 (en) | 1996-12-31 | 1996-12-31 | Method for forming metal interconnection of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960079961A KR100414745B1 (en) | 1996-12-31 | 1996-12-31 | Method for forming metal interconnection of semiconductor device |
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| Publication Number | Publication Date |
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| KR19980060599A KR19980060599A (en) | 1998-10-07 |
| KR100414745B1 true KR100414745B1 (en) | 2004-03-30 |
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| JP6979888B2 (en) | 2018-01-18 | 2021-12-15 | 東京エレクトロン株式会社 | Tungsten film film forming method and film forming system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6477933A (en) * | 1987-09-19 | 1989-03-23 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH06120479A (en) * | 1992-10-05 | 1994-04-28 | Seiko Epson Corp | Semiconductor device and manufacture thereof |
| JPH07130742A (en) * | 1993-11-08 | 1995-05-19 | Nippondenso Co Ltd | Electrode wiring for semiconductor device |
| JPH0878416A (en) * | 1994-04-28 | 1996-03-22 | Nippondenso Co Ltd | Electrode wiring and its manufacture |
| KR980011925A (en) * | 1996-07-29 | 1998-04-30 | 김광호 | Method of filling a contact hole in a semiconductor device |
-
1996
- 1996-12-31 KR KR1019960079961A patent/KR100414745B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6477933A (en) * | 1987-09-19 | 1989-03-23 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH06120479A (en) * | 1992-10-05 | 1994-04-28 | Seiko Epson Corp | Semiconductor device and manufacture thereof |
| JPH07130742A (en) * | 1993-11-08 | 1995-05-19 | Nippondenso Co Ltd | Electrode wiring for semiconductor device |
| JPH0878416A (en) * | 1994-04-28 | 1996-03-22 | Nippondenso Co Ltd | Electrode wiring and its manufacture |
| KR980011925A (en) * | 1996-07-29 | 1998-04-30 | 김광호 | Method of filling a contact hole in a semiconductor device |
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| KR19980060599A (en) | 1998-10-07 |
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