JPH0794448A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0794448A JPH0794448A JP23977493A JP23977493A JPH0794448A JP H0794448 A JPH0794448 A JP H0794448A JP 23977493 A JP23977493 A JP 23977493A JP 23977493 A JP23977493 A JP 23977493A JP H0794448 A JPH0794448 A JP H0794448A
- Authority
- JP
- Japan
- Prior art keywords
- film
- titanium
- forming
- insulating film
- ion plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造に関
し、特に半導体基板上の絶縁膜に設けられた接続孔を介
して半導体基板に設けられた導電体領域と電気的に接続
する配線の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of a semiconductor device, and more particularly to a wiring for electrically connecting to a conductor region provided on a semiconductor substrate through a connection hole provided in an insulating film on the semiconductor substrate. It relates to a manufacturing method.
【０００２】[0002]
【従来の技術】近年、半導体装置の高集積化に伴い、半
導体基板に設けられた導電体領域と電気的接続を得るた
めの接続孔のアスペクト比（接続孔の深さ／口径）が高
くなってきている。図５に示すように、スパッタによる
チタン膜のボトムカバレッジは、アスペクト比の上昇と
もに急激に低下する。従来のスパッタ法を用いて接続孔
底部に充分なチタン膜厚を確保しようとすると、図６の
ように接続孔開口部がチタン膜で小さくなってしまいタ
ングステンの埋め込みに支障をきたすようになった。さ
らに高アスペクト比の接続孔では、接続孔底部に充分な
チタン膜厚を確保できず良好なコンタクトが得られなく
なった。2. Description of the Related Art In recent years, with the high integration of semiconductor devices, the aspect ratio (depth of connection hole / diameter) of a connection hole for electrically connecting to a conductor region provided on a semiconductor substrate has increased. Is coming. As shown in FIG. 5, the bottom coverage of the titanium film by sputtering sharply decreases as the aspect ratio increases. When an attempt is made to secure a sufficient titanium film thickness at the bottom of the connection hole by using the conventional sputtering method, the opening of the connection hole is made smaller by the titanium film as shown in FIG. 6, which hinders the burying of tungsten. . Further, in the case of a high aspect ratio contact hole, a sufficient titanium film thickness cannot be secured at the bottom of the contact hole, and good contact cannot be obtained.
【０００３】この問題の解決手段として、金属のイオン
または原子のビームを基板に入射して成膜する方法があ
る（例えば、特開平２−３５７２１）。この従来の方法
を、図面を用いて説明する。図４（ａ）に示すように、
シリコンからなる半導体基板４１の表面に形成された素
子分離領域４２，導電体領域４３上に絶縁膜４４を堆積
し、リソグラフィー及び、異方性ドライエッチング技術
により絶縁膜４４の所望の位置に接続孔４５を形成す
る。As a solution to this problem, there is a method of forming a film by injecting a beam of metal ions or atoms into a substrate (for example, Japanese Patent Laid-Open No. 2-35721). This conventional method will be described with reference to the drawings. As shown in FIG.
An insulating film 44 is deposited on the element isolation region 42 and the conductor region 43 formed on the surface of the semiconductor substrate 41 made of silicon, and a contact hole is formed at a desired position of the insulating film 44 by lithography and anisotropic dry etching. 45 is formed.
【０００４】そして、基板と垂直方向に５０〜３００ｅ
Ｖの運動エネルギーをもったイオンまたは、原子を用い
て図４（ｂ）のように、タングステン膜４６を成膜す
る。50-300e in the direction perpendicular to the substrate
As shown in FIG. 4B, a tungsten film 46 is formed by using ions or atoms having V kinetic energy.
【０００５】[0005]
【発明が解決しようとする課題】この従来の方法では、
基板と垂直方向に５０〜３００ｅＶの運動エネルギーを
持った金属のイオンまたは原子により、接続孔底部に露
出した導電体領域表面の自然酸化膜を破壊し、オーミッ
クなコンタクトを得ようとしている。この手法では、自
然酸化膜を完全に除去する前に、接続孔底部に露出した
導電体領域表面が金属膜で覆われてしまう。このため、
自然酸化膜を完全に除去する事ができない。また、接続
孔底部に露出した導電体領域表面の自然酸化膜を破壊す
るためのイオンまたは原子が、基板と水平方向の運動エ
ネルギー成分を持つ場合は、この粒子がコンタクトホー
ル側壁の絶縁膜と衝突し、絶縁膜をスパッタして導電体
領域表面に絶縁膜を付着させることになる。これらの結
果、コンタクト抵抗が高いという問題があった。SUMMARY OF THE INVENTION In this conventional method,
The metal oxide or atom having a kinetic energy of 50 to 300 eV in the direction perpendicular to the substrate destroys the natural oxide film on the surface of the conductor region exposed at the bottom of the contact hole to obtain an ohmic contact. In this method, the surface of the conductor region exposed at the bottom of the connection hole is covered with the metal film before the natural oxide film is completely removed. For this reason,
The natural oxide film cannot be completely removed. Also, if the ions or atoms that destroy the native oxide film on the surface of the conductor area exposed at the bottom of the contact hole have a kinetic energy component in the horizontal direction with the substrate, these particles collide with the insulating film on the sidewall of the contact hole. Then, the insulating film is sputtered to attach the insulating film to the surface of the conductor region. As a result, there is a problem that the contact resistance is high.
【０００６】[0006]
【課題を解決するための手段】本発明は、半導体基板表
面の絶縁膜に半導体基板の導電体領域への接続孔を形成
する工程と、接続孔底部に露出した上記導電体領域表面
の自然酸化膜を除去する工程と、イオンプレーティング
法を用いて、上記絶縁膜上及び接続孔にチタンを成膜す
る工程と、熱処理により接続孔底部にチタンシリサイド
を形成する工程を有する。According to the present invention, a step of forming a connection hole to a conductor region of a semiconductor substrate in an insulating film on the surface of the semiconductor substrate and a natural oxidation of the surface of the conductor region exposed at the bottom of the connection hole. The method includes a step of removing the film, a step of forming titanium on the insulating film and the contact hole by using an ion plating method, and a step of forming titanium silicide at the bottom of the contact hole by heat treatment.
【０００７】[0007]
【実施例１】次に、本発明の第一の実施例について図面
を参照して説明する。図１（ａ）〜（ｃ）は、本発明、
第一の実施例について工程順に示した断面図である。First Embodiment Next, a first embodiment of the present invention will be described with reference to the drawings. 1A to 1C show the present invention,
It is sectional drawing shown in order of a process about 1st Example.
【０００８】図１（ａ）に示すように、シリコンからな
る半導体基板１１上に素子分離領域１２、及び導電体領
域１３を形成した後、気相成長法により、膜厚１．８μ
ｍの絶縁膜１４を形成し、リソグラフィー及びエッチン
グ技術により所望の位置に、直径０．３μｍの接続孔１
５を形成する。そして、ＨＦ５０％、ＮＨ4 Ｆ４０％、
Ｈ2 Ｏ１０％からなるフッ素系洗浄液で１５秒間処理す
る事により、接続孔１５の底部に露出した導電体領域１
３表面の自然酸化膜（約２ｎｍ）を除去する。この洗浄
液１５秒間の処理にともなう、接続孔１５の直径の変化
は４０ｎｍである。As shown in FIG. 1A, after forming an element isolation region 12 and a conductor region 13 on a semiconductor substrate 11 made of silicon, a film thickness of 1.8 μm is formed by vapor phase epitaxy.
m insulating film 14 is formed, and the connection hole 1 having a diameter of 0.3 μm is formed at a desired position by lithography and etching techniques.
5 is formed. Then, HF50%, NH 4 F40% ,
The conductor region 1 exposed at the bottom of the connection hole 15 by being treated with a fluorine-based cleaning liquid containing H 2 O 10% for 15 seconds.
3 The native oxide film (about 2 nm) on the surface is removed. The change in the diameter of the connection hole 15 with the treatment of the cleaning liquid for 15 seconds is 40 nm.
【０００９】次に、図１（ｂ）のようにイオンプレーテ
ィング法を用いて、絶縁膜１４上の膜厚が３０ｎｍのチ
タン膜１６を成膜する。コンタクト抵抗を充分低下、安
定化させるのに必要な接続孔底部のチタン膜厚は１０ｎ
ｍである。イオンプレーティング法によるチタン膜は、
アスペクト比６の接続孔でも８０％以上のボトムカバレ
ッジを有するため、絶縁膜１４上に３０ｎｍのチタン膜
を堆積させれば、接続孔１５の底部に充分な膜厚のチタ
ンが得られる。絶縁膜上のチタン膜は底部の膜厚を確保
できる範囲で薄いほどよいので、本実施例の場合では、
３０ｎｍ程度が最適である。接続孔のアスペクト比が１
程度の場合は、１００％近いボトムカバレッジを示すた
め、絶縁膜上のチタン膜厚は１０ｎｍ程度で良い。接続
孔底部のチタン膜厚が１００ｎｍ以上になるとＰＮ接合
破壊が生じる。これらの理由のため、絶縁膜上のチタン
膜厚は、アスペクト比により最適値は変化するが、１０
〜１００ｎｍの範囲が良い。続いて、スパッタ法を用い
て、チタン膜１６の上に窒化チタン膜１７を形成する。Next, as shown in FIG. 1B, a titanium film 16 having a thickness of 30 nm is formed on the insulating film 14 by using an ion plating method. The titanium film thickness at the bottom of the contact hole required to sufficiently reduce and stabilize the contact resistance is 10n.
m. The titanium film by the ion plating method is
Even a contact hole having an aspect ratio of 6 has a bottom coverage of 80% or more, so that a titanium film having a sufficient thickness can be obtained at the bottom of the contact hole 15 by depositing a titanium film of 30 nm on the insulating film 14. Since it is better for the titanium film on the insulating film to be as thin as possible so long as the thickness of the bottom can be secured, in the case of this embodiment,
The optimum value is about 30 nm. Aspect ratio of connection hole is 1
In the case of about 10%, since the bottom coverage is close to 100%, the titanium film thickness on the insulating film may be about 10 nm. If the titanium film thickness at the bottom of the contact hole is 100 nm or more, PN junction breakdown occurs. For these reasons, the optimum value of the titanium film thickness on the insulating film changes depending on the aspect ratio.
The range of up to 100 nm is preferable. Subsequently, the titanium nitride film 17 is formed on the titanium film 16 by using the sputtering method.
【００１０】そして、図１（ｃ）のように窒素雰囲気中
の７００℃、３０秒のランプアニールにより接続孔１５
の底部にチタンシリサイド１８を形成する。この際、自
然酸化膜が多少あってもチタンにより還元され、良好な
チタンシリサイドが得られる。これにより、酸化膜のな
い、導電体領域１３とチタンシリサイド１８の界面を
得、低抵抗オーミックコンタクトを実現させる。同時
に、このランプアニール処理により窒化チタン膜１７の
バリア性を向上させる。フッ酸系の洗浄液で自然酸化膜
を除去し、ランプアニールによりチタンシリサイド１８
と導電体領域１３の界面を構成したので、成膜粒子のエ
ネルギーを特に限定する必要はない。その後、均一タン
グステン気相成長法によりタングステン膜１９を形成す
る。Then, as shown in FIG. 1C, the contact hole 15 is formed by lamp annealing in a nitrogen atmosphere at 700 ° C. for 30 seconds.
Titanium silicide 18 is formed on the bottom of the. At this time, even if there is some natural oxide film, it is reduced by titanium, and good titanium silicide is obtained. As a result, an interface between the conductor region 13 and the titanium silicide 18 having no oxide film is obtained, and low resistance ohmic contact is realized. At the same time, this lamp annealing treatment improves the barrier property of the titanium nitride film 17. The natural oxide film was removed with a hydrofluoric acid-based cleaning solution, and titanium silicide 18 was formed by lamp annealing.
Since the interface between and the conductor region 13 is formed, it is not necessary to particularly limit the energy of the film-forming particles. After that, the tungsten film 19 is formed by the uniform tungsten vapor deposition method.
【００１１】[0011]
【実施例２】次に、本発明の第２の実施例について図面
を参照して説明する。図２（ａ）〜（ｃ）は、本発明の
第２の実施例について工程順に示した断面図である。Second Embodiment Next, a second embodiment of the present invention will be described with reference to the drawings. 2A to 2C are sectional views showing the second embodiment of the present invention in the order of steps.
【００１２】実施例１と同様にして、図２（ａ），
（ｂ）に示すように、シリコンからなる半導体基板２１
上に素子分離領域２２、及び導電体領域２３、絶縁膜２
４、接続孔２５、を形成し、接続孔２５の底部の自然酸
化膜を除去し、チタン膜２６を成膜する。As in the first embodiment, as shown in FIG.
As shown in (b), the semiconductor substrate 21 made of silicon
Element isolation region 22, conductor region 23, and insulating film 2
4, the connection hole 25 is formed, the natural oxide film at the bottom of the connection hole 25 is removed, and the titanium film 26 is formed.
【００１３】続いて、反応性イオンプレーティング法を
用いて、チタン膜２６の上に３０ｎｍの窒化チタン膜２
７を形成する。イオンプレーティングによる膜は、スパ
ッタによる膜と異なり、主に接続孔の底部に成膜され、
接続孔側壁の膜厚は非常に薄い。また、ボトムカバレッ
ジが高いため、絶縁膜上の膜厚は薄くて良い。このた
め、実施例１に比べ、タングステンの埋め込みに悪影響
を与えることがなく、さらに高アスペクト比の接続孔に
も適用できる。Subsequently, a 30 nm thick titanium nitride film 2 is formed on the titanium film 26 by using the reactive ion plating method.
Form 7. Unlike the film formed by sputtering, the film formed by ion plating is mainly formed on the bottom of the connection hole.
The side wall of the connection hole is very thin. Further, since the bottom coverage is high, the film thickness on the insulating film may be thin. Therefore, as compared with the first embodiment, there is no adverse effect on the embedding of tungsten, and the invention can be applied to a connection hole having a high aspect ratio.
【００１４】そして、実施例１と同様にして、チタンシ
リサイド２８を形成し、その後、均一タングステン気相
成長法によりタングステン膜２９を形成する。Then, in the same manner as in Example 1, titanium silicide 28 is formed, and then a tungsten film 29 is formed by the uniform tungsten vapor deposition method.
【００１５】[0015]
【実施例３】次に、本発明の第３の実施例について図面
を参照して説明する。図３（ａ）〜（ｃ）は、本発明の
第３の実施例について工程順に示した断面図である。Third Embodiment Next, a third embodiment of the present invention will be described with reference to the drawings. 3 (a) to 3 (c) are cross-sectional views showing the third embodiment of the present invention in the order of steps.
【００１６】実施例１と同様にして、図３（ａ），
（ｂ）に示すように、シリコンからなる半導体基板３１
上に素子分離領域３２、及び導電体領域３３、絶縁膜３
４、接続孔３５、を形成し、接続孔３５の底部の自然酸
化膜を除去し、チタン膜３６を成膜する。Similarly to the first embodiment, as shown in FIG.
As shown in (b), the semiconductor substrate 31 made of silicon
The element isolation region 32, the conductor region 33, and the insulating film 3 are formed on the upper surface.
4, the connection hole 35 is formed, the natural oxide film at the bottom of the connection hole 35 is removed, and the titanium film 36 is formed.
【００１７】続いて、図３（ｃ）のように窒素雰囲気中
の７００℃、３０秒のランプアニールにより、チタン膜
３６の表面を窒化して窒化チタン膜３７を形成する。同
時に、この工程で実施例１と同様にして、チタンシリサ
イド２８を形成する。窒化による窒化チタン膜は、スパ
ッタによる膜と異なり、開口部径を全く変化させない。
このため実施例２同様、タングステンの埋め込みに悪影
響を与えない。そして、均一タングステン気相成長法に
よりタングステン膜３９を形成する。Subsequently, as shown in FIG. 3C, the surface of the titanium film 36 is nitrided by lamp annealing at 700 ° C. for 30 seconds in a nitrogen atmosphere to form a titanium nitride film 37. At the same time, titanium silicide 28 is formed in this step in the same manner as in the first embodiment. The titanium nitride film formed by nitriding does not change the opening diameter at all, unlike the film formed by sputtering.
Therefore, as in the second embodiment, the burying of tungsten is not adversely affected. Then, the tungsten film 39 is formed by the uniform tungsten vapor deposition method.
【００１８】この方法は、チタンシリサイドの形成と同
時に窒化チタンを成膜するという利点を持つが、実施例
１、実施例２と比べ窒化チタン膜のバリア性が劣る。こ
のため、タングステンの気相成長時にＳｉ基板とタング
ステンの原料ガスであるＷＦ6 が反応しやすいので、タ
ングステン気相成長時の温度は、低温にしたほうが良
い。また、自然酸化膜の除去方法として上記実施例では
フッ酸系洗浄液を用いたが、これに限る必要はなく、水
素プラズマによる還元等を用いても良い。This method has an advantage that titanium nitride is formed at the same time when titanium silicide is formed, but the barrier properties of the titanium nitride film are inferior to those of the first and second embodiments. For this reason, since the Si substrate and WF 6 which is the source gas of tungsten easily react during the vapor phase growth of tungsten, the temperature during the vapor phase growth of tungsten should be low. Further, as the method for removing the natural oxide film, the hydrofluoric acid-based cleaning liquid was used in the above-mentioned embodiment, but the method is not limited to this, and reduction by hydrogen plasma or the like may be used.
【００１９】[0019]
【発明の効果】以上説明したように本発明は、導電体領
域表面の自然酸化膜を除去し、イオンプレーティング法
を用いて接続孔底部に充分な膜厚のチタン膜を形成し、
熱処理によりチタンシリサイドを形成したので、導電体
領域とチタンシリサイドの界面には酸化膜が存在せず、
高アスペクト比の接続孔においても、低抵抗オーミック
コンタクトが得られるという効果を有する。As described above, according to the present invention, the natural oxide film on the surface of the conductor region is removed, and the titanium film having a sufficient film thickness is formed at the bottom of the connection hole by using the ion plating method.
Since titanium silicide is formed by heat treatment, there is no oxide film at the interface between the conductor region and titanium silicide,
It has an effect that a low resistance ohmic contact can be obtained even in a connection hole having a high aspect ratio.
【００２０】さらに成長するＴｉ膜厚は薄くてよいの
で、配線層全体の膜厚も薄くでき、配線の加工が容易と
なり微細化に有利となる効果及び接続孔の開口部でオー
バーハング形状とならないので、その後の均一タングス
テン気相成長法によるタングステン膜は良好な埋め込み
形状を示し、隙間なく接続孔を埋め込むことができると
いう効果もある。Since the Ti film to be further grown may be thin, the film thickness of the entire wiring layer can be made thin, the processing of the wiring is facilitated, which is advantageous for miniaturization, and an overhang shape is not formed at the opening of the connection hole. Therefore, the subsequent tungsten film formed by the uniform tungsten vapor deposition method has a good filling shape, and there is also an effect that the connection hole can be filled without a gap.
【図１】本発明の第一の実施例の工程順断面図FIG. 1 is a sectional view in order of steps of a first embodiment of the present invention.
【図２】本発明の第二の実施例の工程順断面図2A to 2C are sectional views in order of the processes of a second embodiment of the present invention.
【図３】本発明の第三の実施例の工程順断面図FIG. 3 is a sectional view in order of the processes of a third embodiment of the present invention.
【図４】従来工程の工程順断面図4A to 4C are cross-sectional views in order of process steps of a conventional process.
【図５】チタン膜ボトムカバレッジのアスペクト比依存
性FIG. 5: Aspect ratio dependence of titanium film bottom coverage
【図６】従来スパッタによるチタン膜を用いた場合の接
続孔部断面図FIG. 6 is a sectional view of a connection hole portion when a titanium film formed by conventional sputtering is used.
１１ 半導体基板 １２ 素子分離領域 １３ 導電体領域 １４ 絶縁膜 １５ 接続孔 １６ チタン膜 １７ 窒化チタン膜 １８ チタンシリサイド １９ タングステン膜 ２１ 半導体基板 ２２ 素子分離領域 ２３ 導電体領域 ２４ 絶縁膜 ２５ 接続孔 ２６ チタン膜 ２７ 窒化チタン膜 ２８ チタンシリサイド ２９ タングステン膜 ３１ 半導体基板 ３２ 素子分離領域 ３３ 導電体領域 ３４ 絶縁膜 ３５ 接続孔 ３６ チタン膜 ３７ 窒化チタン膜 ３８ チタンシリサイド ３９ タングステン膜 ４１ 半導体基板 ４２ 素子分離領域 ４３ 導電体領域 ４４ 絶縁膜 ４５ 接続孔 ４６ タングステン膜 ６１ 半導体基板 ６２ 絶縁膜 ６３ チタン膜 ６４ 窒化チタン膜 ６５ タングステン膜 11 semiconductor substrate 12 element isolation region 13 conductor region 14 insulating film 15 connection hole 16 titanium film 17 titanium nitride film 18 titanium silicide 19 tungsten film 21 semiconductor substrate 22 element isolation region 23 conductor region 24 insulating film 25 connection hole 26 titanium film 27 Titanium nitride film 28 Titanium silicide 29 Tungsten film 31 Semiconductor substrate 32 Element isolation region 33 Conductor region 34 Insulating film 35 Connection hole 36 Titanium film 37 Titanium nitride film 38 Titanium silicide 39 Tungsten film 41 Semiconductor substrate 42 Element isolation region 43 Conductor Region 44 Insulating film 45 Connection hole 46 Tungsten film 61 Semiconductor substrate 62 Insulating film 63 Titanium film 64 Titanium nitride film 65 Tungsten film
Claims (6)
基板表面の絶縁膜に半導体基板の導電体領域への接続孔
を形成する工程と、接続孔底部に露出した上記導電体領
域表面の自然酸化膜を除去する工程と、イオンプレーテ
ィング法を用いて、上記絶縁膜上及び接続孔にチタンを
成膜する工程と、熱処理により接続孔底部にチタンシリ
サイドを形成する工程を有する事を特徴とする半導体装
置の製造方法。1. A method of manufacturing a semiconductor device, comprising: forming a connection hole to a conductor region of a semiconductor substrate in an insulating film on the surface of a semiconductor substrate; and a natural oxide film on the surface of the conductor region exposed at the bottom of the connection hole. A step of removing titanium, a step of forming titanium on the insulating film and the contact hole by using an ion plating method, and a step of forming titanium silicide at the bottom of the contact hole by heat treatment. Device manufacturing method.
を成膜した後に、スパッタ法を用いて窒化チタン膜を形
成する工程を有することを特徴とする請求項１記載の半
導体装置の製造方法。2. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a titanium nitride film by a sputtering method after forming a titanium film by an ion plating method.
を成膜した後に、反応性イオンプレーティング法を用い
て窒化チタン膜を形成する工程を有することを特徴とす
る請求項１記載の半導体装置の製造方法。3. The semiconductor device according to claim 1, further comprising a step of forming a titanium nitride film by a reactive ion plating method after forming a titanium film by an ion plating method. Production method.
を成膜した後に、窒素雰囲気中の熱処理によりチタン膜
表面を窒化して、窒化チタン膜を形成する工程を有する
ことを特徴とする請求項１記載の半導体装置の製造方
法。4. The method according to claim 1, further comprising the step of forming a titanium nitride film by nitriding the surface of the titanium film by heat treatment in a nitrogen atmosphere after forming titanium by an ion plating method. A method for manufacturing a semiconductor device as described above.
〜１００ｎｍであることを特徴とする請求項１，２，
３，又は４記載の半導体装置の製造方法。5. The film thickness of titanium on the insulating film is 10 nm.
~ 100nm, Claims 1, 2,
3. The method for manufacturing a semiconductor device according to 3 or 4.
ン気相成長法によりタングステンを形成する工程を有す
ることを特徴とする請求項５記載の半導体装置の製造方
法。6. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of forming tungsten on the entire surface of the titanium nitride film by a uniform tungsten vapor deposition method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23977493A JPH0794448A (en) | 1993-09-27 | 1993-09-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23977493A JPH0794448A (en) | 1993-09-27 | 1993-09-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0794448A true JPH0794448A (en) | 1995-04-07 |
Family
ID=17049705
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23977493A Pending JPH0794448A (en) | 1993-09-27 | 1993-09-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0794448A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07161662A (en) * | 1993-12-08 | 1995-06-23 | Fujitsu Ltd | Manufacture of semiconductor device |
| US6452277B1 (en) | 1999-10-22 | 2002-09-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
| KR100626741B1 (en) * | 2000-06-30 | 2006-09-22 | 주식회사 하이닉스반도체 | Method for forming titanium silicide ohmic contact layer of semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61263159A (en) * | 1985-03-15 | 1986-11-21 | フエアチヤイルド セミコンダクタ コ−ポレ−シヨン | High temperature mutual connection for integrated circuit |
| JPS6353262A (en) * | 1986-08-22 | 1988-03-07 | Mitsubishi Electric Corp | Apparatus for forming thin film |
| JPH0529255A (en) * | 1991-07-19 | 1993-02-05 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPH05160065A (en) * | 1991-12-03 | 1993-06-25 | Sony Corp | Forming method of silicide plug |
-
1993
- 1993-09-27 JP JP23977493A patent/JPH0794448A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61263159A (en) * | 1985-03-15 | 1986-11-21 | フエアチヤイルド セミコンダクタ コ−ポレ−シヨン | High temperature mutual connection for integrated circuit |
| JPS6353262A (en) * | 1986-08-22 | 1988-03-07 | Mitsubishi Electric Corp | Apparatus for forming thin film |
| JPH0529255A (en) * | 1991-07-19 | 1993-02-05 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPH05160065A (en) * | 1991-12-03 | 1993-06-25 | Sony Corp | Forming method of silicide plug |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07161662A (en) * | 1993-12-08 | 1995-06-23 | Fujitsu Ltd | Manufacture of semiconductor device |
| US6452277B1 (en) | 1999-10-22 | 2002-09-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
| KR100626741B1 (en) * | 2000-06-30 | 2006-09-22 | 주식회사 하이닉스반도체 | Method for forming titanium silicide ohmic contact layer of semiconductor device |
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