KR20000013433A - Method of forming metal silicide layer selectively - Google Patents
Method of forming metal silicide layer selectively Download PDFInfo
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- KR20000013433A KR20000013433A KR1019980032290A KR19980032290A KR20000013433A KR 20000013433 A KR20000013433 A KR 20000013433A KR 1019980032290 A KR1019980032290 A KR 1019980032290A KR 19980032290 A KR19980032290 A KR 19980032290A KR 20000013433 A KR20000013433 A KR 20000013433A
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- South Korea
- Prior art keywords
- metal silicide
- metal
- interlayer insulating
- layer
- forming
- Prior art date
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- 239000002184 metal Substances 0.000 title claims abstract description 55
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 55
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 38
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims abstract description 12
- 239000010410 layer Substances 0.000 claims abstract description 24
- 239000011229 interlayer Substances 0.000 claims abstract description 18
- 239000010936 titanium Substances 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 6
- 239000010941 cobalt Substances 0.000 claims abstract description 6
- 229910017052 cobalt Inorganic materials 0.000 claims abstract description 6
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract 3
- 238000000059 patterning Methods 0.000 claims abstract 2
- 239000004065 semiconductor Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims 1
- 230000006866 deterioration Effects 0.000 abstract 1
- 238000002955 isolation Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
Abstract
Description
본 발명은 반도체 장치의 금속 실리사이드막 형성방법에 관한 것이다.The present invention relates to a method for forming a metal silicide film of a semiconductor device.
최근, 고속 반도체 메모리 소자의 개발을 위해 가능한 한 컨택등의 저항을 줄이는 것이 요구되고 있다. 이러한 요구에 따라서, 컨택 부위를 종래의 다결정 실리콘 대신에 금속 실리사이드막으로 형성하는 반도체 장치가 늘어나고 있다. 이러한 금속 실리사이드막은 텅스텐(W), 타이타늄(Ti), 코발트(Co) 등의 고융점 금속과 실리콘(Si)을 열처리하여 형성한다.In recent years, the development of high-speed semiconductor memory devices has been required to reduce the resistance of contacts and the like as much as possible. In response to these demands, semiconductor devices are being formed in which contact portions are formed of metal silicide films instead of conventional polycrystalline silicon. The metal silicide layer is formed by heat-treating a high melting point metal such as tungsten (W), titanium (Ti), cobalt (Co), and silicon (Si).
이렇게 컨택등이 형성되는 영역에 금속 실리사이드막을 형성함으로써, 컨택등의 저항을 낮게 하여 저전압, 고속 장치에 매우 유용하게 사용되고 있지만, 종래의 금속 실리사이드막 형성방법은 금속 실리사이드막이 형성되지 않아야 하는 부위에도 공정상 어쩔 수 없이 금속 실리사이드막을 형성한다는 단점이 있다.By forming the metal silicide film in the area where the contact light is formed in this way, the resistance of the contact light is lowered and is very useful for low voltage and high speed devices. However, the conventional method of forming the metal silicide film is performed on the part where the metal silicide film should not be formed. There is a disadvantage in that a metal silicide film is inevitably formed.
일예로 도1에 도시한 바와 같은 트랜지스터에서, 종래의 방법은 게이트 전극(14), 소오스 영역(16) 및 드레인 영역(18)의 전 영역에 금속 실리사이드막(20,22,24)을 형성한다. 이렇게 게이트, 소오스, 드레인 전 영역에 금속 실리사이드막을 형성하면, 게이트 전극의 측면과 소오스 또는 드레인 간의 누설전류가 증가하거나 단락이 일어나 트랜지스터의 오동작을 초래할 수 있으며, 게이트와 소오스 및 드레인 간의 저항감소로 인하여 정전기 방전(Electro-static discharge) 방지 특성이 저하한다.For example, in the transistor as shown in FIG. 1, the conventional method forms the metal silicide films 20, 22, and 24 in all regions of the gate electrode 14, the source region 16, and the drain region 18. FIG. . If the metal silicide film is formed in the entire gate, source, and drain regions, leakage current between the side of the gate electrode and the source or drain may increase or a short circuit may occur, resulting in malfunction of the transistor, and due to a decrease in resistance between the gate, source, and drain. The electrostatic discharge prevention property falls.
본 발명은 상기한 문제점을 해결하기 위하여 금속 실리사이드막이 형성되어야 할 부위만 선택적으로 금속 실리사이드막을 형성하는 방법을 제공하는 것을 목적으로 한다.In order to solve the above problems, an object of the present invention is to provide a method for selectively forming a metal silicide film only on a portion where a metal silicide film should be formed.
도1은 종래의 방법에 의해 금속 실리사이드막이 형성된 트랜지스터를 도시한 단면도이다.1 is a cross-sectional view showing a transistor in which a metal silicide film is formed by a conventional method.
도2 내지 도4는 본 발명의 실시예에 따라 선택적으로 금속 실리사이드막을 형성하는 과정을 도시한 단면도들이다.2 to 4 are cross-sectional views illustrating a process of selectively forming a metal silicide film according to an embodiment of the present invention.
상기의 목적을 달성하기 위한 본 발명에 따른 선택적 금속 실리사이드막 형성방법은 다음과 같이 이루어진다. 먼저, 금속 실리사이드막을 형성하고자 하는, 실리콘으로 이루어진 하부구조 상에 층간절연막을 적층한 후, 금속 실리사이드막을 형성하고자 하는 부위만 노출하도록 층간절연막을 패터닝한다. 이어 전면에 금속층을 증착하고 열처리하여 층간절연막이 제거된 부위에만 금속 실리사이드막을 형성한다.Method for forming a selective metal silicide film according to the present invention for achieving the above object is made as follows. First, an interlayer insulating film is laminated on a silicon substructure on which a metal silicide film is to be formed, and then the interlayer insulating film is patterned to expose only a portion where the metal silicide film is to be formed. Subsequently, a metal layer is deposited on the entire surface and heat-treated to form a metal silicide film only at a portion where the interlayer insulating film is removed.
여기서, 상기 금속은 타이타늄(Ti) 또는 코발트(Co)인 것을 특징으로 한다.Here, the metal is characterized in that the titanium (Ti) or cobalt (Co).
이와 같이, 본 발명은 금속 실리사이드막을 형성하고자 하는 구조물 위에 곧바로 금속 실리사이드막을 형성하지 않고, 먼저 층간절연막을 적층한 후 금속 실리사이드막을 형성하고자 하는 영역만 선택적으로 식각함으로써, 원하는 부위에만 금속 실리사이드막을 형성할 수 있다.As described above, the present invention does not directly form a metal silicide film on a structure on which a metal silicide film is to be formed, but first stacks an interlayer insulating film and then selectively etches only a region where a metal silicide film is to be formed, thereby forming a metal silicide film only on a desired portion. Can be.
이하, 첨부도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도2 내지 도4는 본 발명의 실시예에 따라 트랜지스터의 게이트 전극, 소오스 영역, 드레인 영역의 각 일부에만 금속 실리사이드막을 형성하는 과정을 도시한 단면도들이다.2 through 4 are cross-sectional views illustrating a process of forming a metal silicide film in only a part of a gate electrode, a source region, and a drain region of a transistor according to an embodiment of the present invention.
먼저 도2를 보면, 반도체 기판(100) 상에 게이트 산화막(120) 및 다결정 실리콘으로 이루어진 게이트 전극(140)이 형성되어 있고, 반도체 기판(100)의 소정영역에 불순물 주입에 의한 소오스 영역(160) 및 드레인 영역(180)이 형성되어 있다. 그리고, 게이트 전극(140), 소오스 영역(160) 및 드레인 영역(180)의 전면에 층간절연막(200)을 적층한다.First, referring to FIG. 2, a gate electrode 140 made of a gate oxide film 120 and polycrystalline silicon is formed on a semiconductor substrate 100, and a source region 160 by impurity implantation into a predetermined region of the semiconductor substrate 100. ) And the drain region 180 are formed. The interlayer insulating film 200 is stacked on the entire surface of the gate electrode 140, the source region 160, and the drain region 180.
이어서, 층간절연막을 식각하여 게이트 전극(140), 소오스 영역(160) 및 드레인 영역(180)의 각각 일부만을 노출하는 컨택홀들을 형성한다. 이 컨택홀들에는 후속공정에서 금속등의 도전성 물질이 채워져 각각 게이트 전극(140), 소오스 영역(160), 드레인 영역(180)을 위한 컨택을 형성한다.Subsequently, the interlayer insulating layer is etched to form contact holes exposing only a part of the gate electrode 140, the source region 160, and the drain region 180. The contact holes are filled with a conductive material such as metal in a subsequent process to form contacts for the gate electrode 140, the source region 160, and the drain region 180, respectively.
이렇게 형성된 컨택홀들과 식각된 층간절연막(210) 전면에 금속 실리사이드막 형성을 위한 금속층(300)을 증착하면 도3에 도시된 바와 같이 금속층(300)은 컨택홀 저면에서만 각각 실리콘으로 이루어진 게이트 전극(140), 소오스 영역(160) 및 드레인 영역(180)과 접촉하게 된다. 여기에 사용되는 금속으로는 타이타늄(Ti)이나 코발트(Co) 등이 될 수 있다.When the metal layer 300 for forming the metal silicide layer is deposited on the contact holes and the etched interlayer insulating layer 210, the metal layers 300 are each formed of silicon only at the bottom of the contact hole, as shown in FIG. 3. 140, the source region 160 and the drain region 180 are in contact with each other. The metal used herein may be titanium (Ti) or cobalt (Co).
도3과 같은 지금까지의 결과물을 열처리하면, 도4에 도시된 바와 같이, 금속층(300)이 실리콘과 접촉하는 컨택홀들의 저면에서만 금속과 실리콘이 반응하여 금속 실리사이드막(320,340,360)을 형성하게 된다.When heat treating the resultant material as shown in FIG. 3, as shown in FIG. 4, the metal and silicon react with only the bottom surfaces of the contact holes in contact with the silicon to form the metal silicide layers 320, 340, and 360. .
이후에, 층간절연막(210) 윗면과 측벽에 실리사이드화하지 않고 남아 있는 금속층은 제거하거나, 아니면 금속층을 제거하지 않고 후속공정에서 컨택홀에 컨택 플러그를 채운 후 화학기계적 연마(Chemical Mechanical Polishing) 등에 의해 층간절연막(210)의 윗면에 남은 금속층과 플러그 물질만 제거할 수 있다.Subsequently, the remaining metal layer without silicided on the top and sidewalls of the interlayer insulating film 210 is removed, or the contact hole is filled in the contact hole in a subsequent process without removing the metal layer, and then by chemical mechanical polishing. Only the metal layer and the plug material remaining on the upper surface of the interlayer insulating layer 210 may be removed.
이상 상술한 바와 같이 본 발명에 따르면, 금속 실리사이드막을 형성할 하부구조에 먼저 층간절연막을 적층하고 금속 실리사이드막을 형성할 부위만 노출하여 금속 실리사이드막을 형성함으로써, 원하는 부위에만 금속 실리사이드막을 형성할 수 있으므로, 원하지 않는 부위에 형성된 금속 실리사이드막에 의한 누설전류나 정전기 방전 방지특성의 저하를 피할 수 있다.As described above, according to the present invention, the metal silicide film may be formed only on a desired portion by forming a metal silicide film by first stacking an interlayer insulating film on a substructure on which the metal silicide film is to be formed and exposing only a portion to form the metal silicide film. The fall of the leakage current and the electrostatic discharge prevention characteristic by the metal silicide film formed in the unwanted site | part can be avoided.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980032290A KR20000013433A (en) | 1998-08-08 | 1998-08-08 | Method of forming metal silicide layer selectively |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980032290A KR20000013433A (en) | 1998-08-08 | 1998-08-08 | Method of forming metal silicide layer selectively |
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| KR20000013433A true KR20000013433A (en) | 2000-03-06 |
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| KR1019980032290A KR20000013433A (en) | 1998-08-08 | 1998-08-08 | Method of forming metal silicide layer selectively |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100459930B1 (en) * | 2002-07-19 | 2004-12-03 | 동부전자 주식회사 | Method of making partial self-aligned salicide contact |
| KR100469833B1 (en) * | 2001-09-27 | 2005-02-02 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device |
| KR100609239B1 (en) * | 2003-12-08 | 2006-08-02 | 동부일렉트로닉스 주식회사 | Method For Manufacturing Semiconductor Devices |
| KR100953332B1 (en) * | 2002-12-31 | 2010-04-20 | 동부일렉트로닉스 주식회사 | method for manufacturing a semiconductor device |
| KR20120050624A (en) * | 2010-11-11 | 2012-05-21 | 삼성전자주식회사 | Methods of manufacturing a semiconductor device |
-
1998
- 1998-08-08 KR KR1019980032290A patent/KR20000013433A/en not_active Application Discontinuation
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100469833B1 (en) * | 2001-09-27 | 2005-02-02 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device |
| KR100459930B1 (en) * | 2002-07-19 | 2004-12-03 | 동부전자 주식회사 | Method of making partial self-aligned salicide contact |
| KR100953332B1 (en) * | 2002-12-31 | 2010-04-20 | 동부일렉트로닉스 주식회사 | method for manufacturing a semiconductor device |
| KR100609239B1 (en) * | 2003-12-08 | 2006-08-02 | 동부일렉트로닉스 주식회사 | Method For Manufacturing Semiconductor Devices |
| KR20120050624A (en) * | 2010-11-11 | 2012-05-21 | 삼성전자주식회사 | Methods of manufacturing a semiconductor device |
| US8691693B2 (en) | 2010-11-11 | 2014-04-08 | Samsung Electronics Co., Ltd. | Methods of manufacturing semiconductor device |
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