NL7908534A - METHOD FOR MANUFACTURING A MOSS DEVICE WITH SELF-ALIGNED CONTACTS - Google Patents

Description

- * -1- 21045 / JF / yl

Applicant: American Microsystems, Inc., Santa Clara, California, United States of America.

Short designation: Method for manufacturing a MOS device with self-aligned contacts.

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The invention relates to a method for manufacturing an integrated circuit semiconductor device having a number of field-effect transistor elements with self-aligning electrical contacts on their source and drain regions and whose gate electrodes are connected to device connectors, as well as an integrated circuit semiconductor device with an array of field-effect transistor elements, each with self-aligned electrical contacts on their source and drain regions and on their gate electrodes for connection to the device connectors.

In general, the invention relates to integrated switching semiconductor devices and in particular to a method of manufacturing such devices with self-aligned contacts.

A widely integrated circuit with often thousands of 20 MOSFETs on a single semiconductor wafer must have a plurality of contacts to provide the necessary interconnections between circuit lines, source and drain regions, and gate electrodes of individual transistor elements. Using long-standing conventional procedures, it was necessary to oversize the conductive areas as well as larger contact openings to compensate for mask alignment tolerance. In general, this resulted in devices that require a relatively large adhesive surface.

Due to the rapid increase in widely integrated circuit devices with even greater numbers of MOSFET elements, attempts have been made to reduce not only the dimensions of the elements but also the dimensions of the required contacts. This, together with the trend towards smaller design tolerances and narrower connecting lines, became an increasingly serious problem. A proposed solution described in the Journal of Electro-chem. Soc. Solid State Science and Technology, Vol. 125, 35, No. 3, March, 1978, pages 71-472 provides a gate material of polycrystalline silicon coated on its sides and top with a thin silicon dioxide (SiO 2) layer. However, it has been found that this is insufficient, because the problems of short circuits due to the breaking of the 790 85 34 c v -2- 21045 / JF / jl ·

SiO 2 layer could not be prevented during subsequent process steps.

The object of the invention is to eliminate the above-mentioned drawbacks and to this end provides a method of the type mentioned in the preamble, characterized in that it comprises the following steps: providing a doped semiconducting substrate of a first conductivity type, scribing and providing field oxide regions on top of or sunken in the substrate, surrounding open areas on the substrate surface for each of the field effect transistor elements, forming a relatively thin gate dielectric layer within the open regions, forming and drawing a layer of conductive material in gate regions of a predetermined shape and thickness, over the dielectric gate layer within the open areas, forming a layer of dielectric material on the sides and top of each gate region of conductive material, forming within each open region surrounded by the field oxide-15 doped silicon source and drain regions of a second conductive unit type material opposite to the first conductivity type of the substrate, wherein the boundaries of the source and drain regions are determined by the edges of the predetermined gate regions provided in the fourth step, so that the source and drain regions are self-aligned with respect to the edges of the gate electrodes, forming a relatively thin layer of protective dielectric material over the entire device including all areas of conductive material in the open areas and the field oxide areas, covering the thin layer of protective material on the device without relatively thick layer of insulating material, marking and etching predetermined oversized access openings through the insulating material over the gate electrode and over the source and drain regions and removing oxide and dielectric material from the surfaces of the source and drain regions and predetermined portions of the gate electrodes, and he applying and marking a predetermined metal-type, highly electrically conductive connecting line pattern extending into the access openings for making electrical connections to the source and drain regions and to the gate electrodes.

The invention also provides a device of the type mentioned in the preamble, characterized in that the device comprises: a doped semiconductor substrate of a first conductivity type, field oxide regions on top of or recessed in the substrate, which open regions on the substrate surface surrounded for each of the field effect transducer elements, a layer of conductive material of predetermined shape and thickness, which forms the gate electrodes within the open areas, a layer of dielectric material on the sides, and 790 8 5 34 _3_ 21045 / JF / jl. on the top of each gate electrode, doped silicon source and drain regions of a second conductivity type material opposite to the primary conductivity type of the substrate on opposite sides of the gate electrodes, the boundaries of the source and drain regions being determined by the edges of the gate electrodes, a relatively thin layer of protective dielectric measure ri-10 which covers substantially the entire top portion of each gate electrode and a relatively thick layer of insulating material covering the thin layer of protective material on the device and having oversized access opening provided over the gate electrodes and over the source and drain regions, and a predetermined metal-type, highly electrically conductive connector pattern on the device extending into the access openings for making electrical connections to the self-aligned source and drain regions and to the gate electrodes.

In addition to overcoming the problems outlined above, the invention provides several other advantages, such as providing a means of making a widely integrated circuit device with a substantially smaller area per MOS transistor element than hitherto possible. was possible. In addition, the invention allows for the production of such small area devices where the source and drain regions of the MOSFET elements can be formed either by standard diffusion or by ion implantation techniques.

In accordance with the principles of the present invention, MOSFET elements with self-aligned contacts forming an integrated circuit device can be manufactured in a semiconductor substrate of a first conductivity type by a method of forming a permanent internal protective layer.

The first steps of the method use conventional manufacturing techniques. After the field oxide regions have been formed, with openings for transistor elements, polysilicon gate regions are disposed within the openings. Polysilicon conductive lines are also simultaneously formed on the field oxide surface at or adjacent to such openings as necessary. Thereafter, contact areas of the minimum required dimensions are formed on opposite sides of each gate region as well as where required on the conductive lines. In one embodiment of the method of the invention, all of these poly gates and conductive lines are first applied with a top layer of silicon nitride and then a thin oxide layer on its sides. Then, source and drain regions are formed by diffusion techniques, and then the thin silicon nitride protective layer is applied over the entire wafer, covering the field oxide regions, as well as the polysilicon regions and the regions surrounding the polyport regions. Then, a standard layer of phosphor impregnated glass 10 (PVX) is also applied to the entire slab to cover the thin nitride layer and a contact mask on the PVX layer is used to form the necessary contact holes by first etching away the PVX in the contact opening areas but stopping at the protective nitride layer. The thick field oxide and the thin oxide layer on the sides of the polyport regions are protected from PVX etching by the thin protective nitride layer. Subsequently, the thin nitride protective layer in the contact areas is etched away by an etchant which does not act on the field oxide and the protective polyoxide. Then, a poly contact mask is used to form contact openings in the PVX layer and the nitride top layer on the polylines for the contacts on the poly connecting lines. Both of the latter two masks can use the relatively large gaps to align themselves with the desired contact areas, because the previously used thin nitride layer provides protection for the field oxide and protects the polyoxide on the gate areas and short circuit between gates, polylines and N + connecting lines. Due to this added internal protection. the alignment tolerances previously required between the poly gates, polylines and contact openings have been substantially reduced, without the unusually low tolerance on the. contact masks for forming the contact openings are required. Thus, the invention significantly alleviates the problems of providing the integrated circuit devices with more densely packed elements per unit area and, moreover, greater yield.

In an alternative embodiment of the method of the invention, the polygates and conductive lines, after they are formed, are provided with a thin silicon dioxide layer on their sides and also on their top surface instead of the initial nitride layer. The source drain regions are then formed by ion implantation techniques 790 85 34 t-210-21045 / JF / µl in which the polysilicon gate serves as a mask, as is known in the art. Thereafter, the thin internal nitride protective layer is applied over the entire adhesive surface before completing its manufacture. The protective layer again aims to prevent internal short circuits and over-etching of the thin oxide layer on the conductive poly gates or polylines and during the formation of oversized holes in the insulating PVX layer.

In summary, the objects of the invention are: to provide an improved method of forming the semiconductor devices with self-aligned contacts, to provide a method which allows a reduction in the space between the contacts and the conductive mutual connecting lines, simplifying the manufacture of densely packed devices; providing a method which can be easily controlled with standard semiconductor manufacturing facilities and providing a method which produces the production yield of widely integrated semiconductor devices with self - will increase targeted contacts.

The invention will now be described with reference to preferred embodiments 20, with reference to the drawing, in which: Fig. 1 is a plan view of a typical MOS transistor structure with contacts formed according to the prior art; FIG. 2 is a top view of an MOS transistor structure formed with self-aligned contacts; Figures 3a to 14a show the steps for forming self-aligned contacts for a semiconductor device according to the method of the invention; and Figures 3b to 14b show the steps for forming self-aligned contacts for a semiconductor device using a slightly modified method according to the invention.

Fig. 1 of the drawing shows a plan view of a conventional MOS transistor 10 of the prior art with non-self-aligned source and drain contacts 12 and 14 and a gate contact 16. Generally accepted design rules for such transistors in a large scale integrated circuits require that each contact on a source and drain region 18 and on a gate electrode 20 extending thereover have a minimum surface area. Due to alignment tolerances in forming such contacts 790 85 34 * * __ -6-21045 / JF / jl using conventional fabrication procedures, it was necessary to make the underlying source-drain region 18 significantly larger than the minimum contact region in order to ensure correct alignment of the contacts. For example, to have the minimum required contact area, uniform tolerance around all sides of the contacts (shown at L1 and L ^) and predetermined minimum distance between contact edges and polysilicon edges (L ^) was required using conventional fabrication technology .

The design requirements resulted in a MOS semiconductor device as shown in FIG. 1, in order to avoid short circuit and leakage problems in an integrated circuit including many such MOS devices.

The reduction in adhesive area which can be achieved for a single MOS transistor 10a with self-aligned contacts is shown in Figure 2. Here the source 7, drain and gate contacts 12a, 14a and 16a all have the minimum area and are automatically expanded. with respect to the boundaries of the source drain region 18a or gate electrodes 20a and the surrounding field oxide. The tolerances L, and are reduced to nil, and each diffused region 18a can have a minimum size, both in width and length, using conventional design rules. Also, since each contact is self-aligned, or fully contained in the respective contact area, the distance from an adjacent conductive line can also be minimized, further reducing the total adhesive area required for a semiconductor device.

The more important process steps for manufacturing such a semiconductor device with self-aligned contacts according to the invention will now be described with reference to Figures 3a to 14a.

As shown in Fig. 3a, the method begins with providing a semiconductor substrate 22 (eg, <100> flat silicon material) doped in the appropriate range to provide the desired characteristics. This substrate is covered with an initial oxidation layer 24 of 500 to 1000 2, on which a second layer 26 of silicon nitride of approximately the same thickness is formed.

Using a field oxide mask, the layers 24 and 26 are removed by etching in the field areas as shown in Fig. 4a, and these areas are then field implanted as indicated 790 8 5 34 ψ -7-21045 / JF / jl with the dashed lines 28, in order to set field threshold levels in a conventional manner.

As shown in Fig. 5a, a relatively thick field oxide 30 is now grown in the field regions also in a conventional manner. This directs the field-implanted regions 28 further into the substrate 22 below the oxide regions. In a typical semiconductor structure, the field oxide is configured to form holes or openings within which MOS transistors are to be formed.

After the field oxide is formed, the original nitrile layer 26 and the gate oxide layer 24 are removed by etching. Thereafter, a new gate oxide layer 32 is formed within the hole in the field oxide.

Now, a thin (e.g. 150 to 300 2) nitride layer 35 is applied over the entire device surface including the new oxide layer 32 and the field oxide 30 (as shown in Fig. 6a) using conventional vapor deposition techniques. In order to ensure stability of the product, the top surface of this nitride layer is oxidized in steam from a dry oxygen environment (not shown). The step shown in Fig. 6a provides a new nitride / oxide sandwich that has not undergone the heat treatment applied during the field oxide formation adjusted to a suitable thickness. The original oxide / nitride sandwich 24, 26 shown in Figure 3a set to suitable thickness may be used as the gate dielectric.

In the next step of the method embodiment of FIG.

7a, a layer of 36 polycrystalline silicon (poly) is applied, by a standard vapor deposition process, to the entire surface of the wafer which is manufactured to a typical thickness of around 3000 to 5000 2.

A mask is then used to define gate 30 electrodes 38 within the active regions formed in the field oxide and connecting lines 40 disposed on the top of the field oxide 30 and adjacent one or more gate elements. At this time, all portions of conductive poly within a field oxide opening and on the field oxide are located on a nitride / oxide sandwich. Using known silicon gate procedures, in which the gate serves as a mask, ion implantation techniques, such as shown by the vertical arrows in Figure 9a, are used to form source and drain regions 42 and 44 just below the substrate surface within the field osopean regions. 790 85 34

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-8- 21045 / JF / jl ning and on opposite sides of the polysilicon port 38.

In the next step, as shown in Fig. 10a, a layer 46 of silicon dioxide is grown on all sides and also on the top of all conductive poly regions including the gate poly regions 38 and the adjacent polyconjunction lines 40 The thickness of this covering layer on the poly is usually much larger than the gate oxide 32 (e.g. around 3000 2) and its purpose is to provide a protective layer on the poly to create the self-aligned contact structure.

In the next step, as also shown in Fig. 10a, a thin nitride protective layer 48 is applied over the entire structure existing at this time, including the field regions 30, the source and drain regions 42 and 44 and the regions 38 and 40 of oxide-coated poly. This nitride layer will later serve to provide vital protection for the field oxide and polyoxide during subsequent process steps. Following the application of the thin nitride layer, the entire wafer, as shown in Fig. 11a, is covered with a relatively thick layer 50 of phosphosilicate glass (PVX) in a conventional manner.

Now, as shown in Fig. 12a, a first mask (not shown) for the N + contacts is applied to the PVX and an appropriate etchant (eg buffered hydrofluoric acid) is used to etch away the PVX layer 50 and the nitride. oxide sandwich 32, 34 in the contact area. Then, a second contact mask is applied to the wafer in the same manner as the first mask, and an etchant is used to etch away the PVX, nitbide and the oxide on the polysilicon lines. These latter two masks for the N and polysilicon contacts can be applied in reverse order if desired.

This causes the wafer, as shown in Fig. 13a, with the PVX layer 50 to coincide with the thin nitride layer 48 with windows for exposing the drain contact area 42 and also an exposed contact area 41 on the adjacent poly-bonding line 40 without oxide coating.

At this time, standard fabrication process steps can be used to apply metal to the contact areas to define metal contacts 52 and 54 as part of a desired metal connection pattern on the semiconductor device. Typically, these metalization steps include the evaporation of metal and definition thereof with a suitable metal mask and then applying a protective top dielectric layer over the entire slab (not shown) for passivation.

7908534 -9- 21045 / JF / jl

In a modified version of the method of the invention shown by Figures 3b to 14b, the steps of Figures 3b to 6b are identical to those of Figures 3a to 6a. However, this modified version avoids the need to use ion implantation equipment and procedures for forming the source and drain regions.

As shown in Fig. 7b, a poly layer 36 with a typical thickness in the range of 3000 2 to 5000 2 is formed on the slab over the gate nitride layer 34 by conventional chemical vapor deposition techniques. This poly layer is then doped by diffusion of phosphorus therein to make it more conductive. Thereafter, a nitride layer 56 having a thickness significantly greater than that of the gate nitride layer 34 (e.g., 1000 to 2000 2) is applied to the polysilicon layer 36.

As shown in Fig. 8b, the polysilicon layer 36 is defined in gate regions and connecting lines using a poly mask (not shown) and standard etching techniques that remove the unwanted material in the polynitride layer. This results in the structure having a doped polysilicon gate or electrode 38 within an area surrounded by field oxide 30 and an adjacent poly-bond line 40 located on the oxide, both of these poly elements having the nitride layer 56 on an upper surface.

In the next step shown in Fig. 9b, the poly gate members are provided with an oxide layer 46 on a side with a thickness of around 3000 2. This is accomplished by simple thermal oxidation in a chamber in accordance with known procedures.

Now, as shown in Fig. 10b, the source and drain regions 42 and 44 are formed by diffusion techniques. First, the gate nitride layer 34 is etched away from any surface except the tops of the 30 poly layers. Thereafter, the gate oxide layer 32 is etched in all areas surrounding the gate poly layer. Standard diffusion procedures are now used to form source and drain regions 42 and 44. Following this, a thin oxide layer 58 is formed in the diffused regions with a thickness of around 5,000.

A protective nitride layer 60 (for example 150 to 300 2) is applied to the structure shown in Fig. 10b. Thus, this layer 60 is much thinner than the nitride layer 56 and, as in the previous embodiment, layer 60 extends over the entire slab including the 790 85 34 -10-104545 / JF / µl field areas 30, the source drain areas and the nitride covered port 38 and line poly regions 40.

Now, the PVX layer 50 is applied and etched using a contact mask in the same manner as described above with respect to the first embodiment of the method. Also with oversized contact holes, in the PVXx layer as described above, the metalization of the MOS elements on the wafer is performed to form metal contacts 52 and 54 with associated connecting lines in a standard manner.

By using one of the embodiments of the method of the invention, it is possible to manufacture large-scale integrated semiconductor devices using a plurality of MOSFET elements with self-aligned contacts, requiring a minimal adhesive surface in a tightly packed array. For example, in a typical free-access memory (RAM), the area required for a single memory cell was 1344 square microns, while in the self-aligned contacts, using the method of the invention, the same memory cell with an area of to provide only 950 square microns, which amounts to an area reduction of about 30%. In addition, according to the method of the invention, the yield of a similarly densely packed self-aligning device may be even greater than conventional prior art devices, because the internal nitride protective layers 48 and 60 maintain circuit integrity during critical process steps, by the prevention of short circuits or errors, which have hitherto been caused during the various process steps. Although silicon nitride is a more preferred material for the protective layers, other materials such as silicon carbide or aluminum oxide can also be used. To those skilled in the art to which the invention pertains many changes in construction and significantly different embodiments and applications of the invention will suggest themselves without departing from the spirit and scope of the invention. The description is illustrative only and is not intended to be limiting in any way.

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Claims (15)

A method of manufacturing an integrated circuit semiconductor device having a plurality of field-effect transistor elements with self-aligning electrical contacts on their source and drain regions and whose gate electrodes are connected by device connectors, characterized in: comprising the following steps: providing a doped semiconducting substrate of a first conductivity type, marking and providing field oxides e-10 on top of or recessed into the substrate, which open areas on the substrate surface for each of the surrounded field effect transistor elements, forming a relatively thin gate dielectric layer within the open areas, forming and marking a layer of conductive material in gate areas of predetermined shape and thickness, over the gate dielectric layer within the open areas, forming of a layer of dielectric material on the sides and top of each gate area of conductive material, forming within each open region surrounded by the field oxide-doped silicon source and drain regions of a second conductivity type material opposite to the first conductivity type 20 of the substrate, the boundaries of the source and drain regions being determined by the edges of the predetermined gate regions provided in the fourth step, so that the source and drain regions are self-aligned with respect to the edges of the gate electrodes, forming a relatively thin layer of protective dielectric material over the entire device including all regions conductive material in the open areas and the field oxide regions, covering the thin layer of protective material on the device with a relatively thick layer of insulating material, marking and etching predetermined oversized access openings through the insulating material the gate electrode and over the source and drain regions and the ref depositing oxide and dielectric material from the surfaces of the source and drain regions and from predetermined portions of the gate electrodes, and applying and marking a predetermined metal-type, highly electrically conductive connector pattern extending into the access openings for Making electrical connections to the source and drain regions and to the gate electrodes. A method according to claim 1, characterized in that the silicon nitride protective layer is formed by vapor deposition at a 790 85 34 -12-2 21045 / JF / µl thickness in the range of 150 2 to 300 2. A method according to claim 2, characterized in that the top surface of the silicon nitride protective layer is oxidized before application of the insulating material. 5 The method according to claim 1, characterized in that the protective layer is silicon carbide. Process according to claim 1, characterized in that the protective layer is aluminum oxide. 6. A method according to claim 1, characterized in that the dielectric gate layer is a sandwich of silicon nitride over silicon dioxide. A method according to claim 1, characterized in that the conductive gate electrodes are polycrystalline silicon, covered on all sides and on the top with an outer layer of silicon dioxide. Method according to claim 7, characterized in that the source and drain regions are formed by ion implantation. Method according to claim 1, characterized in that the silicon dioxide layer on the gate electrodes has a thickness of around 3000 2 to 5000 2. Method according to claim 1, characterized in that the conductive gate electrodes are polycrystalline; silicon, the sides of which are covered with a layer of silicon dioxide and the top of which is covered with a layer of silicon nitride. 11. A method according to claim 10, characterized in that the thickness of a silicon dioxide layer on the sides of the gate electrodes is around 3000 2 to 5000 2 and in that the thickness of the silicon nitride layer on the top thereof is around 1000 2 to 2000 is 2. 12. A method according to claim 10, characterized in that the source and drain regions for each field effect transistor are formed by a diffusion process. A semiconductor device manufactured according to the method steps of claim 1. 14. Integrated circuit semiconductor device with an array of field-effect transistor elements, each with self-aligned electrical contacts on their source and drain regions and on their gate electrodes for connection to the device connectors, characterized in that the device includes: a doped semiconductor substrate of a first conductivity type, field oxide regions on top of or recessed 790 85 34 -13- 21045 / JF / µl surrounding the open areas on the substrate surface for each of the field effect transistor elements, a layer of conductive material having a predetermined shape and thickness which forms the gate electrodes within the open areas, a layer of dielectric material on the sides and on the top of each gate electrode, doped silicon source and drain areas of a second conductivity type? material opposite to the primitive conductivity type of the substrate on opposite sides of the gate electrodes, the boundaries of the source and drain regions being determined by the edges of the gate electrodes, a relatively thin layer of protective dielectric material which is essentially the covers the entire top portion of each gate electrode and a relief thick layer of insulating material covering the thin layer of protective material on the device and having oversized access aperture applied over the gate electrodes and. across the source and drain regions, and a predetermined metal-type, highly electrically conductive connector line pattern on the device extending into the access openings for making electrical connections to the self-aligned source and drain regions and to the gate electrodes. 15. A semiconductor device according to claim 14, characterized in that the internal protective layer is silicon nitride with a thickness in the range from 150 2 to 300 2. Eindhoven, November 1979. 790 35 34