KR0161394B1 - Method for fabricating semiconductor transistor - Google Patents

Abstract

Disclosed is a method of fabricating a transistor in a semiconductor device capable of preventing the reduction of the dielectric properties between the gate electrode and the buried contact layer by removing or suppressing the hump formed on the gate electrode side wall. The transistor manufacturing method of the present invention comprises the steps of forming a field oxide film on a semiconductor substrate, forming a gate oxide film on the semiconductor substrate and forming a doped polysilicon and tungsten silicide on the gate oxide film, PE-CVD And HTO exclusively (first and second embodiments) or mixed (third embodiment) to deposit an oxide film and sequentially etch the oxide film, tungsten silicide and doped polysilicon to form a polyside gate electrode. Removing a humper on the sidewall of the gate electrode generated in the gate electrode forming step (second embodiment); forming a source and a drain region on the semiconductor substrate; and forming a spacer on the sidewall of the gate electrode. And forming pad polysilicon on the drain region. According to the present invention, the hump of the sidewall of the gate electrode can be backwashed and removed by using an SC-1 solution and selecting an oxide film in consideration of a physical state change of tungsten silicide. Therefore, there is an advantage of reducing the leakage current between the gate electrode and the buried contact layer.

Description

Method of manufacturing transistor in semiconductor device

1 is a view showing pits formed on a semiconductor substrate.

2A through 2C are diagrams illustrating, in steps, a method of manufacturing a transistor of a semiconductor device using a conventional technology.

3A to 3C are diagrams illustrating, in steps, a method of manufacturing a transistor of a semiconductor device according to a first embodiment of the present invention.

4A through 4C are diagrams illustrating, in steps, a method of manufacturing a transistor of a semiconductor device according to a second embodiment of the present invention.

5A through 5C are diagrams illustrating, in steps, a method of manufacturing a transistor of a semiconductor device according to a third embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

2,30,60: Semiconductor substrate 10,38,68: Tungsten silicide layer pattern

12, 40, 70: oxide film 17a, 18, 46a, 74: spacer

15,42,72: hump

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for manufacturing a transistor of a semiconductor device. In particular, the manufacture of a transistor of a semiconductor device is characterized in that it suppresses the removal and continual growth of humps formed on the sidewalls of the gate electrode in connection with the formation of polyside gate electrodes. Provide a method.

Silicides are formed in an amorphous state when first formed. Such silicide is gradually crystallized from a predetermined temperature by appropriate heat treatment from the outside. In general, a transistor uses a doped polysilicon to lower the resistance of the gate electrode, but a lower resistance gate electrode is used due to the integration of semiconductor devices. Therefore, a polyside formed of polycrystalline silicon doped under the silicide is used as the gate electrode. Polysides reduce the line resistance by about 1/20 of polycrystalline silicon. There are many kinds of silicides constituting the polyside, but tungsten silicide is used a lot. Tungsten silicide is likewise present in an amorphous state after silicide formation. Tungsten silicide forms the WSix structure. In the amorphous state, the subscript x has a value between 2.5 and 2.8. The crystallization starts at around 450 DEG C by applying heat to the tungsten silicide from outside. The crystal structure in tungsten silicide transitions from a hexagonal system to a tetragonal system between 500 and 650 ° C, wherein the value of x is between 2.0 and 2.2. Therefore, as the temperature increases, the crystal structure changes and the crystal size grows, and out-diffusion of silicon occurs.

In the case of the gate electrode to form an insulating film on the electrode to block electrical contact with the outside, it is required to form in consideration of the silicide immediately below. This is because a gate insulating film is commonly used as a high temperature thermal oxide (HTO) (refer to USP 4774201). At this time, since the formation temperature is 800 ° C or higher, crystallization of the silicide proceeds and external diffusion occurs. In addition, in the etching step after deposition of the insulating layer, many by-products are formed due to the reaction between the etchant and the polyside. This will form a hump in the next step. It also degrades the dielectric properties between the pad polysilicon and the polyside gate electrode of the buried contact layer for connection with the upper metal layer and thereby generates a leakage current. This can lead to device defects.

If the photoresist film PR is used as a mask for patterning the polycrystalline silicon layer P-Si and the tungsten silicide layer WSi as shown in FIG. 1, a hump is applied as in the case of using HTO as a mask. It does not form. However, even when the photoresist is used as a mask, when the gap between the masks is narrow as in the case of (a) of FIG. 1, the etch rate is not affected when the gap between the masks is wide as in the case of (b) of FIG. A different loading dffect occurs. Such an effect is that in a thin device having a gate oxide thickness of 150 GPa or less, all of the gate oxide films are partially etched during polyside etching using the photoresist film, thereby forming a fitting (b1) on the semiconductor substrate. Therefore, it is a general trend to use an oxide film as a mask instead of a photoresist film. The oxide mask mainly used is HTO, which causes the above-mentioned problems and requires a new method.

A transistor manufacturing method of a semiconductor device using a conventional technique will be described in detail with the accompanying drawings.

2A through 2C are diagrams illustrating, in steps, a method of manufacturing a transistor of a semiconductor device using a conventional technology.

2A illustrates a step of forming a gate electrode pattern. Specifically, the field oxide film 3 is formed thick on the semiconductor substrate 1 to distinguish between the active region and the inactive region. Subsequently, a gate oxide film 5 is deposited on the entire surface of the semiconductor substrate 1. A doped polysilicon layer (not shown) is deposited on the gate oxide layer 5. Subsequently, tungsten is deposited on the doped polysilicon layer for heat treatment, or tungsten and silicon are simultaneously deposited for heat treatment to form a tungsten silicide layer (not shown). An oxide film (not shown) is deposited on the tungsten silicide layer. A photoresist film (not shown) is coated on the oxide film, and then patterned to form a photomask p1 defining a predetermined region of the oxide film. The oxide film is etched using the photomask p1 as an etching mask to form the oxide film pattern 11, and then the photomask p1 is removed. The tungsten silicide layer and the polysilicon layer are sequentially dry-etched using the oxide layer pattern 11 as an etching mask. As a result, the tungsten silicide layer pattern 9 and the polysilicon layer pattern 7 are formed. Subsequently, the same conductive impurity as the semiconductor substrate 1 is implanted at low concentration onto the entire surface of the substrate 1 to form the source 13a and the drain 13.

2b illustrates forming an oxide spacer. Specifically, the insulating film 17 is deposited on the entire surface of the resultant product of FIG. 2a. When the insulating layer 17 is reactive ion etched (hereinafter referred to as RIE), etching is performed along the dotted line to form an oxide spacer 17a on the sidewall of the gate electrode.

Figure 2c shows the step of forming a polycrystalline silicon layer for the pad. Specifically, the oxide spacer 17a on the side of the gate electrode is used as a mask to deeply implant the same conductive impurity as the semiconductor substrate to form deep impurity layers 19 and 19a in the source and drain regions to form an LDD structure. do. Subsequently, a pad polycrystalline silicon layer 21 for contact with the upper metal layer is formed on the drain region 13. The process then completes the transistor as usual. The gate oxide film is formed to be 100 Å and the doped polycrystalline silicon layer is 1,000 Å thick. The tungsten silicide layer WSix is formed to a thickness of 1,500 Å. In addition, the oxide film is formed to a thickness of 1,000-4,000Å. The oxide film and the spacer are formed using HTO. The tungsten silicide layer and the doped polysilicon layer are etched by two-step etching, and SF6 and Cl2 gas are used to etch the tungsten silicide layer as a first step. As a next step, the doped polysilicon layer is etched using Cl2, HBr and He-O2 gases. In the transistor manufacturing method of a semiconductor device using a conventional technique, many solid by-products (by-) when forming the oxide film and spacer using HTO and etching the tungsten silicide layer and the doped polysilicon layer. products: see Table 1).

When the solid by-products form spacers of the gate electrode, a hump 15, which is an irregular oxide layer, is formed on the side of the gate line. This hump weakens the dielectric properties between the gate electrode and the contact hole filling layer when forming contact holes on the source or drain as a subsequent process. Thus, the undesirable leakage current between the layers is rapidly increased, which causes a defect in the device.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to prevent the formation of humps by selectively depositing an oxide film in consideration of the physical state of the tungsten silicide layer to remove the formed humps or to prevent leakage between layers. The present invention provides a method for manufacturing a transistor of a semiconductor device that reduces current and improves dielectric properties.

In order to achieve the above object, the first embodiment of the present invention comprises the steps of forming a field oxide film (field-oxide) for separating the active region and the inactive region on the semiconductor substrate;

Forming a gate oxide film on the active region;

Forming a doped polysilicon layer on the gate oxide film;

Forming a tungsten silicide layer on the doped polysilicon layer;

Forming an oxide film using plasma enhanced chemical vapor deposition (PECVD) on the tungsten silicide layer;

Sequentially etching the oxide film, the tungsten silicide layer and the doped polysilicon layer to form a polyside gate electrode;

Forming a drain and a source region on the semiconductor substrate;

Forming an oxide spacer on the side of the gate electrode using plasma enhanced chemical vapor deposition (PECVD); And

It provides a method for manufacturing a transistor of a semiconductor device comprising the step of forming a buried contact layer on the drain region.

A second embodiment of the present invention for achieving the above object comprises the steps of sequentially forming a gate oxide film, a doped polysilicon layer and a tungsten silicide layer on a semiconductor substrate;

Forming an HTO film on the tungsten silicide layer;

Dry etching the HTO film, the tungsten silicide layer and the doped polysilicon layer to form a polyside gate electrode having a hump on the side;

Removing a hump formed on the side of the gate electrode; And

A method of manufacturing a transistor in a semiconductor device, the method comprising forming an HTO spacer in a form completely surrounding the gate electrode side surface.

A third embodiment of the present invention for achieving the above object comprises the steps of sequentially forming a gate oxide film, a doped polysilicon layer, a tungsten silicide layer and an HTO film on a semiconductor substrate;

Dry etching the HTO film, the tungsten silicide layer, and the doped polysilicon layer to form a polyside gate electrode having a hump on the side; And

A method of manufacturing a transistor of a semiconductor device, comprising forming an oxide spacer on a gate electrode side by using PE-CVD in a form of completely enclosing the entire side surface while including a hump formed on the side of the gate electrode. to provide.

In the first embodiment, an oxide film using plasma enhanced chemical vapor deposition (hereinafter referred to as plasma enhanced CVD or PE_CVD) is formed at around 400 ° C. Thus, the tungsten silicide layer is formed in an amorphous state. The side surface of the gate electrode is also formed by using PE-CVD, so that in the first embodiment, the tungsten silicide layer is kept in an amorphous state. Therefore, it does not form a hump.

In the second embodiment, the HTO film is formed at a high temperature and thus the tungsten silicide layer is crystallized. Subsequently, a W-O-F-Cl-based polymer is formed as a by-product by etching in the step of forming the gate electrode. The polymer is removed by treatment for 10 minutes or more with an SC-1 solution consisting of NH3OH + H2O2 + H2O (distilled water). See Table 2 below for the occurrence of hump defects depending on the type of gate mask used and the cleaning time of the SC-1 solution.

Regardless of the type of gate mask, it can be seen that a hump defect does not occur when the SC-1 solution is treated for 10 minutes or longer.

Subsequently, when the HTO spacer is formed on the side of the gate electrode, since the tungsten silicide layer is after crystallization is completed, no additional by-products are formed.

In the third embodiment, the oxide film is formed using an HTO film. Thus, as in the second embodiment, the tungsten silicide layer is crystallized. Therefore, after etching, a W-O-F-Cl-based polymer is partially formed on the side surface. By forming a gate electrode spacer on the polymer using PE-CVD, no further polymer is generated. The oxide films of the first, second and third embodiments are formed to have a thickness of 1,000-4,000 kPa.

The present invention forms an oxide film in consideration of the physical state of the tungsten silicide layer. Therefore, it is possible to minimize the formation of the hump on the side of the gate electrode or to remove the formed hump. This can improve dielectric properties between layers and reduce leakage current.

Hereinafter, the present invention will be described in detail with the accompanying drawings.

3A to 3C are diagrams illustrating, in steps, a method of manufacturing a transistor of a semiconductor device according to a first embodiment of the present invention.

3A shows a step of forming a gate electrode. Specifically, a field oxide film 4 is formed on the semiconductor substrate 2 to distinguish active and inactive regions. A gate oxide film 6 is deposited on the active region. A doped polysilicon layer (not shown) is deposited on the gate oxide film 6. An oxide film (not shown) is deposited on the tungsten silicide layer. A photoresist film (not shown) is applied on the oxide film, and then patterned to form a photo mask P2 defining a predetermined region of the oxide film. The oxide layer is patterned using the photomask P2 as an etching mask to form an oxide layer pattern 12, and then the photomask P2 is removed. The tungsten silicide layer and the doped polysilicon layer are sequentially dry-etched using the oxide layer pattern 12 as an etching mask. As a result, a gate electrode having tungsten silicide layer pattern 10 and polycrystalline silicon layer pattern 18 as a component is formed.

Subsequently, a low concentration of conductive impurities opposite to the semiconductor substrate are shallowly implanted using the gate electrode as a mask to form the drain 14a and the source 14 regions. The oxide film is formed to a thickness of 1,000-4,000Å by PE-CVD. At this time, the formation temperature is around 400 ℃ and the tungsten silicide layer is maintained in the amorphous state (amorphous) state as it is formed, no hump (hump) is formed. That is, since the tungsten silicide layer does not have a physical state change inside, a polymer of WO-Cl-F sequence, which is a by-product formed on the side of the gate electrode during the dry etching, is formed in an extremely small amount than that of the HTO film. .

3B illustrates a step of forming a spacer oxide film. Specifically, a spacer oxide layer 16 is formed on the entire surface of the resultant of FIG. Subsequently, when reactive ion etching (RIE) is performed on the entire surface of the spacer oxide layer 16, a spacer 18 shown by a dashed line is formed on the side of the gate electrode.

3C shows the step of forming the polycrystalline silicon layer for the pad in the state where the oxide film spacer 18 is formed. Specifically, using the spacer 18 as a mask, low-concentration deep conductive impurity layers 20 and 20a opposite to the substrate are formed in the source and drain regions to form an LDD structure. The LDD structure prevents electric field concentration due to a narrow gate width. Subsequently, a pad polycrystalline silicon layer 22 for contact with the upper metal wiring layer (bit line or the like) is formed on the drain. In the first embodiment, the oxide film is formed by PECVD to keep the silicide layer in an amorphous state, thereby suppressing external diffusion of Si to minimize the amount of by-products formed on the gate side. Therefore, the leakage current between the gate electrode and the buried layer of the contact hole is 10 As the degree (A), good dielectric properties can be maintained.

4A through 4C are diagrams illustrating, in steps, a method of manufacturing a transistor of a semiconductor device according to a second embodiment of the present invention.

4A shows a step of forming a gate electrode. Specifically, a gate oxide film 34 is deposited on the semiconductor substrate 30, and then a polycrystalline silicon layer (not shown), a tungsten silicide layer (not shown), and an HTO film (not shown) are deposited on the gate oxide film 34. Is deposited sequentially. A photo mask P3 is formed on the HTO film. When the HTO film is patterned using the photomask P3, an HTO film pattern 40 is formed on the tungsten silicide layer. After removing the photomask P3, the tungsten silicide layer and the doped polysilicon layer are dry-etched using the HTO layer pattern 40 as an etching mask. As a result, a gate electrode including the tungsten silicide layer pattern 38 and the polycrystalline silicon layer pattern 36 is formed. At this time, unlike the first embodiment, the tungsten silicide layer is crystallized, and the value of x in WSix decreases from 2.2 to 2.0. Therefore, external diffusion of silicon occurs, the crystal structure changes from hexagonal to tetragonal, and the size of the crystal increases. Due to the physical change of the tungsten silicide layer, the reaction between SF6 and Cl2 used to etch the tungsten silicide layer and Cl2, HBr and He-O2 gases used to dry etch the doped polysilicon layer A large amount of by-products, or humps 42, are formed on the side of the gate electrode. After forming the gate electrode, a hump (42) formed on the side of the gate electrode is treated for 10 minutes or more using an SC-1 solution (NGOH + HO + HO (distilled water)). In this way, the hump is completely removed.

4B and 4C show a step of forming a space oxide film and a polycrystalline silicon layer for a pad. Specifically, an oxide film 46 is deposited on the entire surface of the resultant product of FIG. 4a. The oxide film 46 is an HTO film. Subsequently, RIE of the oxide film 46 forms an oxide film 46a for spacer formation shown by a dashed line (Fig. 4B). Subsequently, the LDD structure and the step of forming the polysilicon layer for the pad (FIG. 4C) are the same as in the first embodiment. The second embodiment differs from the first embodiment in that the oxide film and the spacer are formed by using the HTO film and the physical state change of the tungsten silicide layer. That is, in the second embodiment, the tungsten silicide layer is crystallized in the HTO film forming step. Therefore, if the hump generated when the oxide film is formed by using the HTO film is removed, subsequent formation of the side spacers of the gate electrode is almost unaffected regardless of the forming means. Therefore, by treating the hump generated in the gate electrode forming step with a chemical solution, good dielectric properties between the gate electrode and the buried contact layer can be maintained as in the first embodiment. The tungsten silicide layer forming step is the same as the first embodiment. In addition, the step after spacer formation is the same.

In FIG. 4C, reference numerals 44, 50, 44a, and 50a are impurity layers forming an LDD structure, respectively, and reference numeral 52 is a polycrystalline silicon layer for a pad.

5A through 5C are diagrams illustrating, in steps, a method of manufacturing a transistor of a semiconductor device according to a third embodiment of the present invention.

5A shows a step of forming a gate electrode. Specifically, the gate oxide film 64 is formed on the semiconductor substrate 60. The second embodiment is performed until forming the HTO film pattern 70 using the photomask P4 and forming the polyside gate electrode including the doped polysilicon layer pattern 66 and the tungsten silicide layer pattern 68 using the same. Proceed as in the example. At this time, a small amount of hump 72 is formed on the side of the polyside gate electrode, and the tungsten silicide layer is crystallized. Subsequently, source and drain regions 73 and 75 are formed. Subsequently, the deposition of the oxide film 73 and the formation of the spacer 74 in FIG. 5B and the formation of the polysilicon layer 78 for the pad in FIG. 5C are performed according to the first embodiment. In this way, an oxide spacer 74 is formed to completely surround the side of the gate electrode on which the hump is formed.

The spacer 74 in the third embodiment is formed using PE-CVD to inhibit the formation of the HTO film and the continued growth of the etched hump of the tungsten silicide layer and the doped polysilicon layer. Thus, a smaller amount of hump is formed than when using the prior art. This provides another method which can suppress the formation of the hump in a manner different from those of the first and second embodiments. In the first, second and third embodiments, the oxide film is formed to have a thickness of 1,000-4,000 kPa.

The present invention forms an oxide film and an oxide spacer in consideration of the physical state of the tungsten silicide layer. That is, both the oxide film and the oxide spacer are formed by PE-CVD, or when the oxide film is formed, the HTO film is used, the hump is removed, and then the oxide spacer is formed of the HTO film, and the oxide film is formed. The HTO film is used when the oxide spacer is formed, and PE-CVD is used. As such, a variety of transistors can be used or mixed with PE-CVD or HTO films to suppress the removal or growth of the hump on the side of the polyside gate electrode, thereby improving the dielectric properties of the gate electrode and the buried contact layer and reducing leakage current. It provides a manufacturing method.

The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical idea of the present invention.

Claims (7)

Forming a field oxide on the semiconductor substrate, the field-oxide separating the active and inactive regions; Forming a gate oxide film on the active region; Forming a doped polysilicon layer on the gate oxide film; Forming a tungsten silicide layer on the doped polysilicon layer; Forming an oxide film using plasma enhanced chemical vapor deposition (PE-CVD) on the tungsten silicide layer; Sequentially etching the oxide film, the tungsten silicide layer and the doped polysilicon layer to form a polyside gate electrode; Forming a drain and a source region on the semiconductor substrate; Forming an oxide spacer on the side of the gate electrode using plasma enhanced chemical vapor deposition (PE-CVD); And forming a buried contact layer on the drain region. The method of claim 1, wherein the tungsten silicide layer is formed in an amorphous state. Sequentially forming a gate oxide film, a doped polysilicon layer, and a tungsten silicide layer on the semiconductor substrate; Forming an HTO film on the tungsten silicide layer; Dry etching the HTO film, the tungsten silicide layer and the doped polysilicon layer to form a polyside gate electrode having a hump on the side; Removing a hump formed on the side of the gate electrode; And forming an HTO spacer in a form completely surrounding the side of the gate electrode. 4. The method of claim 3, wherein the tungsten silicide layer is formed in a crystalline state. The method of claim 3, wherein the hump is removed by treatment with SC-1 (NH 3 OH + H 2 O 2 + H 2 O) for at least 10 minutes. Sequentially forming a gate oxide film, a doped polysilicon layer, a tungsten silicide layer, and an HTO film on the semiconductor substrate; Dry etching the HTO film, the tungsten silicide layer, and the doped polysilicon layer to form a polyside gate electrode having a hump on the side; And forming an oxide spacer on the side of the gate electrode by using PE-CVD in a form completely covering the entire side while including a hump formed on the side of the gate electrode. . 7. The method of claim 6, wherein the tungsten silicide layer is formed in a crystalline state.