KR101085910B1 - Method for manufacturing a semiconductor device - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can reduce the leakage current of the device and form a uniform silicide while applying the SC-1 cleaning process, in the present invention, forming a gate electrode on the semiconductor substrate And forming a source / drain region on the substrate exposed to both sides of the gate electrode, performing an SC-1 cleaning process on the entire surface of the substrate on which the gate electrode is formed, and the overall structure including the gate electrode. Depositing a metal layer along an upper step, depositing a Ti film on the metal layer, depositing a capping layer on the Ti film, and applying a salicide process to the surface of the substrate during the cleaning process. The gate electrode and the source / drain of which silicon is exposed while converting a chemical oxide film formed on the substrate into a porous material A semiconductor device including forming a silicide layer of a uniform shape on the surface of the station provides a method of manufacturing the same.

Silicide, DHF, SC1, cleaning, oxide film, Co / Ti / TiN.

Description

METHODS FOR MANUFACTURING A SEMICONDUCTOR DEVICE

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

Description of the Related Art

110 semiconductor substrate 111 device isolation film

112 gate insulating film 113 polysilicon film

114: gate electrode 115: spacer

116 source / drain regions 117 oxide film

118: cobalt film 119: titanium film

120: titanium nitride film 121: silicide layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a non-memory device in which a Salicide (SALICIDE) process having a line width of 0.25 μm or less is applied.

Recently, as the size of semiconductor devices decreases, line widths narrow and the effect of sheet resistance on RC delay increases, resulting in low resistivity gates, interconnections and low ohmic contact resistances. Interest is growing. For this reason, a Salicide (SALICIDE; Self Align siLICIDE) process has been proposed to form a silicide having a low resistivity value. As such, silicide having a low specific resistance has advantages such as excellent electromigration characteristics in addition to thermal stability. In addition, the silicide can be formed directly on the polycrystalline silicon without further processing and can maintain the basic polycrystalline silicon structure of the metal oxide semiconductor (MOS), which is still being actively researched.

Hereinafter, a method of manufacturing a semiconductor device according to the related art to which the salicide process is applied will be described with reference to FIGS. 1A to 1C. 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

First, as shown in FIG. 1A, the gate electrode 14 is formed on the semiconductor substrate 10 on which the device isolation film 11 is formed. At this time, the gate electrode 14 is composed of a gate oxide film 12 and a polysilicon film 13.

Subsequently, spacers 15 made of an insulating film are formed on both side walls of the gate electrode 14. At this time, the insulating film usually consists of an oxide film.

Next, the source / drain regions 16 are formed in the semiconductor substrate 10 exposed to both sides of the spacer 15.

Subsequently, a cleaning process using a diluted HF (DHF) solution is performed to remove the oxide film remaining on the surface of the semiconductor substrate 10 in the above-described process.

Subsequently, as shown in FIG. 1B, the cobalt film 17 (hereinafter referred to as Co film) and the titanium nitride film 18 (hereinafter referred to as TiN film) are formed along the steps of the entire structure including the gate electrode 14. Deposition sequentially.

Subsequently, as shown in FIG. 1C, a salicide process is performed to form a cobalt silicide layer 19 on the surfaces of the source / drain regions 16 and the polysilicon film 13. Here, the salicide process is performed as follows.

First, a first thermal process is performed at a temperature of about 500 ° C. to form a silicide layer (not shown) of a CoSi component on the surfaces of the source / drain regions 16 and the polysilicon film 13.

Subsequently, both the Co film 17 and the TiN film 18 which did not react at the time of the first thermal process are removed.

Subsequently, a second thermal process is performed at a temperature of about 750 ° C. to finally form a cobalt silicide layer 19 (CoSi ₂ layer) on the surfaces of the source / drain region 16 and the polysilicon film 13.

However, when the cleaning process using the DHF solution is performed as described above, the oxide film formed on the surface of the semiconductor substrate is easily removed, but the particles become hydrophobic and have static electricity, so that many particles adhere to the substrate. Problem occurs. Therefore, in order to solve such particle adhesion, the research on the DHF + SC-1 cleaning process which performs the SC-1 (Standard Cleaning-1) cleaning process following the DHF cleaning process has been actively performed recently.

The SC-1 cleaning process is a method of removing contaminants using NH ₄ OH, H ₂ O _2, and pure water (DI Water). After the process, several chemical oxide films are formed on the substrate surface. Therefore, when the low temperature SC-1 cleaning process is performed after the DHF cleaning process, the substrate becomes hydrophilic by a chemical oxide film formed on the surface of the substrate, thereby reducing the phenomenon that particles adhere to the substrate. On the other hand, the movement of Co atoms, i.e., diffusion, is disturbed by the chemical oxide film formed on the surface of the substrate, so that no silicide reaction occurs. Therefore, a problem arises in that the contact resistance of the semiconductor device increases and the leakage current increases.

As a result, in order to apply the SC-1 cleaning process, a sputtering etching process must be performed in an argon atmosphere before the Co film is deposited to remove all oxide films present on the substrate surface. However, this method may cause a problem in that the leakage current increases in the portion etched by etching not only the oxide layer but also the substrate during the sputter etching process.

Accordingly, the present invention has been proposed to solve the above problems of the prior art, and provides a method of manufacturing a semiconductor device capable of reducing the leakage current of the device and forming a uniform silicide while applying the SC-1 cleaning process. The purpose is.

According to an aspect of the present invention, there is provided a method including: forming a gate electrode on a semiconductor substrate, forming a source / drain region on the substrate exposed to both sides of the gate electrode, and Performing a SC-1 cleaning process on the entire surface of the substrate on which a gate electrode is formed, depositing a metal layer along a step of an upper portion of the entire structure including the gate electrode, depositing a Ti film on the metal layer, and Depositing a capping layer on the Ti film, and performing a salicide process to convert the chemical oxide film formed on the surface of the substrate into a porous material during the cleaning process to expose the gate electrode and the source / drain region of silicon. A method of manufacturing a semiconductor device comprising forming a silicide layer of uniform form on a surface of The.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

Example

2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 2A to 2D are the same elements performing the same function.

First, as shown in FIG. 2A, the gate insulating layer 112 and the polysilicon layer 113 are sequentially deposited on the semiconductor substrate 110 on which the device isolation layer 111 is formed, and then an etching process is performed. Form 114. In this case, the device isolation layer 111 may be formed by performing a shallow trench isolation (STI) or LOCOS (LOCal Oxidation of Silicon) process, which is formed by performing an STI process suitable for high integration of semiconductor devices. The polysilicon film 113 is formed of a doped or undoped polysilicon film 113. For example, the polysilicon layer 113 is formed by depositing a low pressure chemical vapor deposition (LPCVD) method using SiH ₄ or SiH ₄ and PH ₃ .

Although not shown in the drawings, a well (not shown) may be formed on the semiconductor substrate 110 on which the device isolation layer 111 is formed by performing a well ion implantation process. For example, N wells may be formed by implanting Phosphorus or Arsenic ions, or P wells may be formed by implanting Boron.

Subsequently, an insulating film (not shown) is deposited along the level of the upper part of the entire structure on which the gate electrode 114 is formed, followed by a dry etching process to form spacers 115 on both sidewalls of the gate electrode 114.

Next, a source / drain ion implantation process using the spacer 115 as a mask is performed to form source / drain regions 116 on the semiconductor substrate 110 exposed to both sides of the spacer 115.

Subsequently, as illustrated in FIG. 2B, a DHF + SC-1 cleaning process is performed to clean the semiconductor substrate 110 on which the gate electrode 114 and the spacer 115 are formed. At this time, when the DHF + SC-1 cleaning process is performed, a thin chemical oxide film 117 is formed on the surface of the semiconductor substrate 110. Accordingly, since the semiconductor substrate 110 becomes hydrophilic and the static electricity disappears, the particles attached to the substrate 110 are drastically reduced. Here, SC-1 washing | cleaning process is performed at the temperature of 10-100 degreeC.

Subsequently, as shown in FIG. 2C, a cobalt film 118 (hereinafter referred to as a Co film) is deposited on the metal layer for silicide formation along the step of the entire structure where the DHF + SC-1 cleaning process is completed. In this case, nickel may be deposited instead of the Co film 118.

Subsequently, a titanium film 119 (hereinafter referred to as a Ti film) is deposited on the Co film 118. At this time, the Ti film 119 is deposited to a thickness of 1 to 200 GPa. Here, the Ti film 119 has a property of bonding well with the oxide film, thereby improving the coupling property of the oxide film and the Co film 118.

Subsequently, a titanium nitride film 120 (hereinafter referred to as a TiN film) is deposited on the Ti film 119 as a capping layer. Here, the Ti film 119 and the TiN film 120 may be continuously deposited or separately deposited in one chamber.

Subsequently, as shown in FIG. 2D, a salicide process is performed to form the silicide layer 121 on the surfaces of the silicon exposed regions, that is, the source / drain regions 116 and the polysilicon film 113.

Here, the salicide process consists of two thermal processes after depositing the Co film 118, the Ti film 119 and the TiN film 120. For example, by performing a first thermal process, the chemical oxide film 117 is converted into a porous film quality so that mono silicide is formed in a uniform form on the surfaces of the source / drain regions 116 and the polysilicon film 113. A layer (CoSi; not shown) is formed. Then, a second thermal process is performed to convert the monosilicide layer into a CoSi ₂ layer. As a result, a silicide layer 121 made of CoSi ₂ is formed.

Here, the first thermal process is a rapid thermal annealing (RTA) process at 450 to 550 ° C. When the first thermal process is performed, the Ti atoms of the Ti film 119 move through the Co film 118 to move the semiconductor substrate 110. Reacts with the chemical oxide film 117 existing between and the Co film 118. As a result, the chemical oxide film 117 is converted into a porous film in the form of CoxTiyOz (x, y and z are natural numbers). Therefore, the silicide layer 121 of the CoSi component may be formed in a uniform form in the region where silicon is exposed. Here, when nickel (Ni) is deposited instead of the Co film 118, the first thermal process is performed at a temperature of 400 ° C. or lower to form the silicide layer 121 of the Ni ₂ Si component.

In addition, the second thermal process is a RTA process of 700 to 800 ° C, and finally forms a silicide layer 121 of CoSi ₂ form. In the case where nickel is deposited instead of the Co film 118, the second thermal process is performed at a temperature of 400 to 700 ° C. to form the silicide layer 121 of the NiSi component. At this time, a process of removing the Co film 118 and the TiN film 120 in a region that does not react during the first heat process is performed between the first heat process and the second heat process.

That is, according to the preferred embodiment of the present invention, after performing the DHF + SC-1 cleaning process on the entire substrate on which the gate electrode is formed, the Co (or Ni) / Ti / TiN film is sequentially deposited and then the salicide process is performed. As a result, a uniform silicide layer may be formed on the surface of the silicon, that is, the source / drain region and the surface of the gate electrode. Therefore, the yield can be increased by reducing the contact resistance and leakage current of the semiconductor device.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, after performing the DHF + SC-1 cleaning process on the entire substrate on which the gate electrode is formed, the Co (or Ni) / Ti / TiN film is sequentially deposited and then the salicide process is performed. As a result, a uniform silicide layer may be formed on the surface of the silicon, that is, the source / drain region and the surface of the gate electrode. Therefore, the yield can be increased by reducing the contact resistance and leakage current of the semiconductor device.

Claims (8)

Forming a gate electrode on the semiconductor substrate; Forming a source / drain region on the substrate exposed to both sides of the gate electrode; Performing an SC-1 cleaning process on the entire surface of the substrate on which the gate electrode is formed; Depositing a metal layer along a step above the entire structure including the gate electrode; Depositing a Ti film on the metal layer; Depositing a capping layer on the Ti film; And By performing a salicide process, a uniform silicide layer is formed on the surface of the gate electrode and the source / drain regions where silicon is exposed while converting the chemical oxide film formed on the surface of the substrate into a porous material during the cleaning process. Making; Method of manufacturing a semiconductor device comprising a. The method of claim 1, wherein the salicide process, Performing a first thermal process on the entire substrate on which the capping layer is deposited so that Ti atoms of the Ti film penetrate the metal layer and diffuse into the chemical oxide film to change the chemical oxide film into a porous material and to form a first silicide layer step; Removing all of the metal layer and the capping layer which have not been reacted during the first thermal process; And Performing a second thermal process to convert the first silicide layer to a second silicide layer; Method of manufacturing a semiconductor device comprising a. The method of claim 2, The metal layer is formed of Co or Ni. The method of claim 3, wherein The first thermal process is a semiconductor forming the first silicide layer of the CoSi component in an RTA process of 450 to 550 ° C. or forming the first silicide layer of the Ni ₂ Si component in an RTA process performed at a temperature of at least 400 ° C. Method of manufacturing the device. The method of claim 3, wherein The second thermal process is a method of manufacturing a semiconductor device to form the second silicide layer of CoSi ₂ component by RTA process of 700 to 800 ℃, or to form the second silicide layer of NiSi component by RTA process of 400 to 700 ℃ . The method according to claim 1 or 2, The capping layer is a method of manufacturing a semiconductor device formed of TiN. The method according to claim 1 or 2, A method of manufacturing a semiconductor device, further comprising a DHF cleaning step before the SC-1 cleaning step. The method of claim 7, wherein The SC-1 cleaning process is performed at a temperature of 10 to 100 ℃ to remove the oxide film formed on the substrate surface during the DHF cleaning process.

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