KR20010003697A - Fabricating method for semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to guarantee a stable electrical characteristic by preventing a grooving phenomenon on a surface of a doped polycrystalline silicon layer, and to prevent a defect by preventing the doped polycrystalline silicon layer and a tungsten silicide layer from diffusing to each other. CONSTITUTION: A gate insulating layer(42) and a doped polycrystalline silicon layer(43) are sequentially formed on a semiconductor substrate(41). An oxide layer as a diffusion barrier layer(44) is formed on the doped polycrystalline silicon layer. A tungsten silicide layer(45) is formed on the diffusion barrier layer. The doped polycrystalline silicon layer is formed by using SiH4 gas or Si2H6 gas containing phosphor or arsenic.

Description

Fabrication method for semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, when forming a gate electrode having a tungsten silicide film / doped polysilicon layer stacked structure, the doped polysilicon layer may be formed using an SC-1 solution, a piranha solution, and a H ₂ O. ₂ to form an oxide film which is a diffusion barrier film by washing with a solution containing ₂ or ozone water, and then forming a tungsten silicide film to prevent mutual diffusion between the tungsten silicide film and the polycrystalline silicon layer to prevent defects from occurring. A method of manufacturing a semiconductor device for improving reliability.

As semiconductor devices become more integrated, the gate electrode of a metal oxide semiconductor field effect transistor (hereinafter referred to as a MOS FET) is decreasing in width, but when the width of the gate electrode is reduced by N times, the electrical resistance of the gate electrode is decreased. There is a problem that the N times increased to decrease the operation speed of the semiconductor device. Therefore, in order to reduce the resistance of the gate electrode, polyside, which is a laminated structure of the polysilicon layer and the silicide, is used as the low resistance gate by using the property of the polysilicon layer / oxide film interface exhibiting the most stable MOSFET characteristics.

In general, the most important function of the transistor constituting the semiconductor circuit is the current driving capability, and the channel width of the MOS FET is adjusted in consideration of this. The most widely used MOS FET uses a polysilicon layer doped with impurities as a gate electrode, and a diffusion region doped with impurities on a semiconductor substrate is used as a source / drain region. Here, the sheet resistance of the gate electrode is about 30 to 70 Ω / □, the sheet resistance of the source / drain region is about 70 to 150 Ω / □ for N +, about 100 to 250 Ω / □ for P +, and the gate electrode or source / In the case of a contact formed on the drain region, the contact resistance is about 30 to 70? /? Per contact.

In order to reduce the high sheet resistance and contact resistance of the gate electrode and the source / drain regions, a metal silicide layer may be formed only on the gate electrode and the source / drain regions using a salicide (self-aligned silicide) method or a selective metal film deposition method. The current driving capability of the MOS FET was increased.

Tungsten silicide films are widely used in word lines as well as bit lines as DRAMs have high electrical resistance. As the DRAM becomes more integrated, capping polycrystalline silicon is used to lower the contact resistance of the bit line and word lines. Form a layer. In this case, when the tungsten silicide layer is deposited on the doped polysilicon layer, a cleaning process using hydrofluoric acid (HF) or B. O. (buffered oxide etchant, hereinafter referred to as BOE) is performed on the doped polysilicon layer. The organic oxide film was removed to thereby cause the surface of the doped polysilicon layer to become unstable and react with the tungsten silicide film, and after deposition to the capping polysilicon layer in a subsequent process, as shown in FIG. Defect will occur.

In the tungsten polyside structure as described above, the tungsten polysilicide has a MS process in which SiH ₄ (monosilane, MS) is reduced by WF ₆ gas, and a SiS ₂ Cl ₂ (dichlorosilane, DCS) is reduced by WF ₆ gas. Deposited by the process. Both DCS and MS processes use WF ₆ as a reducing gas for Si source gas, so that fluorine is deposited in the concentrations of 10 ¹⁶ to 10 ¹⁷ at / cm 2 and 10 ¹⁹ to 10 ²⁰ at / cm 2, respectively, in the deposited tungsten silicide film. Is contained.

The fluorine in the tungsten silicide film diffuses toward the gate insulating film during the subsequent thermal process, as shown in FIG. 2, to lower the dielectric constant of the gate oxide film and to increase the thickness thereof. To reduce GOI properties.

In the manufacturing method of the semiconductor device according to the prior art as described above, defects cause scattering of light in the mask process during subsequent word line patterning, making it difficult to form an accurate wire, and after etching, a residue remains after the bridge ( bridge) can be caused, so that it is impossible to secure a fine line width due to high integration, thereby deteriorating device characteristics or lowering yield.

The present invention to solve the problems of the prior art, a tungsten silicide film / polycrystal surface during the doping agent polysilicon layer forming the gate electrode of a silicon layer stacked structure SC-1 solution, blood Rana solution, H ₂ O ₂ is An oxide film is formed as a diffusion barrier by a cleaning process using a contained solution or ozone water to prevent mutual diffusion between the laminated structures and to prevent defects from occurring on the surface of the doped polysilicon layer, thereby improving GOI characteristics. It is an object of the present invention to provide a method for manufacturing a semiconductor device that improves characteristics and reliability.

1 is a micrograph of the defect by the method of manufacturing a semiconductor device according to the prior art.

2 is a cross-sectional view of a gate electrode formed by a method of manufacturing a semiconductor device according to the prior art.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

Figure 4 is a micrograph of the defect by the manufacturing method of the semiconductor device according to the first embodiment of the present invention.

5 is a cross-sectional view of a gate electrode formed by the method of manufacturing a semiconductor device according to the second embodiment of the present invention.

<Description of the code | symbol about the principal part of drawing>

11, 21, 41: semiconductor substrate 12, 22, 42: gate oxide film

13, 23, 43: Dfed polycrystalline silicon layer 14, 25, 45: Tungsten silicide film

24, 44: diffusion barrier film 26: capping polysilicon film

27 mask oxide film 28 antireflection film

Method for manufacturing a semiconductor device according to the present invention for achieving the above object,

Forming a gate insulating film and a doped polysilicon layer on the semiconductor substrate;

Forming an oxide film as a diffusion barrier on a surface of the doped polysilicon layer;

And forming a tungsten silicide film on the diffusion barrier.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3A to 3B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention, and are applied to a process of forming other conductive wirings such as word lines or bit lines.

First, an isolation layer (not shown) is formed on a portion of the semiconductor substrate 21 that is intended as an isolation region, and a gate insulating layer 22 is formed over the entire surface.

Next, a doped polysilicon layer 23 is formed on the gate insulating layer 22, and SiH ₄ or Si ₂ H ₆ gas is used, and the dopant gas is phosphorous or arsenic. A method of depositing a dope polycrystalline silicon or a polysilicon layer by using a gas containing, for example, a gas such as PH3, and performing a chemical vapor deposition method having a dopant concentration of 1E19 atoms / cm 2 to 9E21 atoms / cm 2 in situ. After deposition, a thermal diffusion doping method using POCl ₃ and an implant method are used.

Then, the surface of the doped polysilicon layer 23 is cleaned using hydrofluoric acid (HF) or a BOE solution. At this time, the surface of the doped polysilicon layer 23 is in an unstable state by the cleaning process.

Next, a diffusion barrier 24 is formed on the doped polysilicon layer 23 to have a thickness of 5 to 50 kHz.

The diffusion barrier 24 is formed by cleaning the surface of the doped polysilicon layer 23 with an SC-1 solution using an oxide film or by scrubbing or scrubbing the surface of the doped polysilicon layer 23 with a natural oxide film. Can be formed.

The diffusion barrier 24 has an interface between the two films because Si in the tungsten silicide film containing a large amount of Si is diffused along the tungsten silicide grain boundary to the adjacent doped polysilicon film during the subsequent thermal process. Since it is broken by a rugged phenomenon, it loses insulation and does not become a problem for the electrical conductivity of the gate electrode.

Next, a tungsten silicide layer 25 is formed on the diffusion barrier layer 24. The tungsten silicide layer 25 is formed by a chemical vapor deposition method using a WF ₆ gas and a SiH ₄ gas, and 2.5 to 5.0 sccm of WF ₆ gas and 200 to 500 sccm of SiH under 350 to 500 ° C. and 0.5 to 2.0 Torr. _{It is} formed using ₄ gas or by chemical vapor deposition using WF ₆ gas and SiH ₂ Cl ₂ gas, and 2.5 to 4.0 sccm of WF ₆ gas and 100 to 300 sccm under 500 to 700 ° C and 0.5 to 2.0 Torr. It is formed using a SiH ₂ Cl ₂ gas.

Next, a capping polysilicon layer 26 is formed on the tungsten silicide layer 25. The capping polysilicon layer 26 uses SiH ₄ or Si ₂ H ₆ gas, the dopant gas is a gas containing phosphorus or arsenic, for example, a gas such as PH 3, and the dopant concentration is 1E19 atoms / cm 2 to Dopant polysilicon was deposited in situ using a chemical vapor deposition method of 9E21 atoms / cm 2, using 0 to 200 sccm of PH ₃ gas and 500 to 2000 sccm of SiH ₄ gas at 500 to 600 ° C. and 180 to 300 Torr. Form.

Next, after forming the mask insulating film 27 and the anti-reflection film 28 on the capping polysilicon layer 26, the anti-reflection film by using a gate electrode mask that protects a portion intended as a gate electrode as an etching mask (28), the mask insulating film 27, the capping polysilicon layer 26, the tungsten silicide film 25, the diffusion barrier film 24 and the doped polysilicon layer 23 are etched to form a gate electrode.

4 is a micrograph of a defect by the method of manufacturing a semiconductor device according to the first embodiment of the present invention, and no defect can be found.

5 is a cross-sectional view of a gate electrode formed by the method of manufacturing a semiconductor device according to the second embodiment of the present invention.

An isolation layer (not shown) is formed on a portion of the semiconductor substrate 41 to be an isolation region, and a gate insulating layer 42 is formed on the semiconductor substrate 41 to a thickness of 40 to 100 Å.

Next, a doped polysilicon layer 43 doped with an impurity such as phosphorus is formed on the gate insulating layer 42, and the mixture ratio of SiH ₄ and PH ₃ gas is 1.1: 1.5 to 1.5: 1.8 at 500 to 700 ° C. Chemical vapor deposition method using a gas mixed with the deposited to 500 ~ 1000Å thickness.

Next, the surface of the doped polysilicon layer 43 is cleaned to form a diffusion barrier 44.

At this time, the diffusion barrier 44 is formed by a washing step using a basic solution of SC-1, NH ₄ OH: H ₂ O ₂ : H ₂ O is mixed in a volume ratio of 1: 0.5 to 1.5: 3 to 7. . The cleaning process is carried out by dipping the wafer into the SC-1 solution at 15 to 90 ° C. for 1 to 10 minutes, and the diffusion barrier 44 is formed to have a thickness of 5 to 30 μs by the cleaning process.

On the other hand, the washing step may be carried out using a piranha solution. The piranha solution is a solution in which H ₂ SO ₄ : H ₂ O ₂ is mixed in a volume ratio of 2 to 4: 1 and dipping the pyrana solution at 85 to 150 ° C. for 1 to 10 seconds to perform a washing process. It is also possible to form a diffusion barrier film having a thickness of 5 to 30 GPa by dipping for 2 to 10 minutes using ozone water (10 ppm to 50 ppm). In addition, the washing step can be carried out using a solution containing H ₂ O ₂ .

Next, a tungsten silicide film 45 is formed on the diffusion barrier 44, and the tungsten silicide film 45 is formed by a chemical vapor deposition method using WF ₆ gas and SiH ₄ gas, but the temperature is 500 to 650 ° C. 600 to 1500 kW using a mixed gas of WF ₆ gas and SiH ₄ gas mixed at 2 to 3.5: 1 or a mixed gas of WF ₆ gas and SiH ₂ Cl ₂ gas mixed at 2 to 3: 1 to 1.5 at Form to thickness. The tungsten silicide film 45 formed by the above process is formed of a WSi _x film having a value of 2 ≦ _x ≦ 2.8 in order to increase the adhesive strength with the doped polysilicon layer 43 and to improve oxidation characteristics.

In a subsequent process, a capping polysilicon layer (not shown), a mask insulating film (not shown), an antireflection film (not shown), or the like may be stacked on the tungsten silicide layer 45.

Table 1 below shows the comparison of GOI characteristics of pad oxide film formation conditions by application of the base condition and the cleaning process using the SC-1 solution. The base condition is the doped polycrystalline silicon without applying the SC-1 solution. In the case where the oxide film on the surface of the layer is completely removed, SC-1 is applied when the oxide film is formed on the surface of the doped polycrystalline silicon layer.

Table 1

Progress condition P1 VDP Rs (Ω / □) Gate insulation film thickness increase (T _ox -T _eff ) Breakdown field (MV / cm) Qbd (C / cm 3) Base 9.07 ± 1 18 ± 0.8 9.15 ± 1.5 7.16 ± 0.7 SC-1 application 9.32 ± 1 13 ± 0.7 10.38 ± 1.2 13.08 ± 1.1

The base condition, the condition in which SC-1 is applied, and the VDP (Vanderpaw) sheet resistance of the gate electrode are not significantly different.

In addition, the gate insulating film thickness increase, which is the value obtained by subtracting the thickness T _eff of the gate insulating film measured in the electrical environment from the actual gate insulating film thickness T _ox , was measured less when the SC-1 solution was applied. This is because the diffusion of fluorine from the tungsten silicide film is prevented and the reaction between the fluorine and the gate insulating film is suppressed.

In addition, the breakdown field in which the gate insulating film is destroyed when the voltage is constantly increased and the charge amount Qbd when the gate insulating film is broken down are larger, and the better is the case where the SC-1 solution is applied. Do.

As described above, in the method of manufacturing a semiconductor device according to the present invention, a surface of a doped polysilicon layer doped with impurities during the formation of a gate electrode having a tungsten polyside structure applied to a highly integrated device is used as an SC-1 solution. After washing to form a diffusion barrier layer, a tungsten silicide layer is formed to prevent grooving of the surface of the doped polysilicon layer, thereby securing a uniform interface to secure stable electrical characteristics. By preventing mutual diffusion between the polysilicon layer and the tungsten silicide layer to prevent defects from occurring, and preventing the fluorine in the tungsten silicide layer from diffusing into the gate insulating layer and the doped polycrystalline silicon layer, the GOI characteristics and the doped polycrystalline layer Improved resistance uniformity of the silicon layer enables high integration of semiconductor devices. And it has the advantage of improving the properties of the device and the process yield.

Claims (14)

Forming a gate insulating film and a doped polysilicon layer on the semiconductor substrate; Forming an oxide film as a diffusion barrier on a surface of the doped polysilicon layer; And forming a tungsten silicide film on the diffusion barrier. The method of claim 1, The doped polysilicon layer is formed by using a mixed gas containing phosphorus or arsenic in SiH ₄ gas or Si ₂ H ₆ gas. The method of claim 2, The mixed gas has a dopant concentration of 1E19 atoms / cm 2 to 9E21 atoms / cm 2. The method of claim 1, The doped polysilicon layer is deposited in-situ by a chemical vapor deposition method, or a method of manufacturing a semiconductor device, characterized in that formed by a thermal diffusion doping method or an implant method. The method of claim 1, The doped polysilicon layer is a method of manufacturing a semiconductor device, characterized in that 500 to 1000 Pa by a chemical vapor deposition method using SiH ₄ and PH ₃ gas as a reaction gas at 500 ~ 700 ℃. The method of claim 5, The reaction gas is a method of manufacturing a semiconductor device, characterized in that the gas mixed with SiH ₄ and PH ₃ gas in a mixing ratio of 1.1: 1.5 to 1.5: 1.8. The method of claim 1, The diffusion barrier is a manufacturing method of a semiconductor device, characterized in that formed in a thickness of 5 ~ 50Å. The method of claim 1, And the diffusion barrier layer is a natural oxide layer formed by scrubbing the doped polysilicon layer. The method of claim 1, The diffusion barrier is a chemical oxide film formed by cleaning the surface of the doped polysilicon layer using a SC-1 solution, a piranha solution, a solution containing H ₂ O ₂ or ozone water. . The method according to claim 1 or 9, The diffusion barrier film is a semiconductor device manufacturing method characterized in that the wafer formed with a doped polysilicon layer is dipped in 10 to 50ppm ozone water for 2 to 10 minutes to perform a cleaning process to form a thickness of 5 to 30Å. The method according to claim 1 or 9, The SC-1 solution is a method of manufacturing a semiconductor device, characterized in that the NH ₄ OH: H ₂ O ₂ : H ₂ O is a basic solution mixed in a volume ratio of 1: 0.5 to 1.5: 3 to 7. The method of claim 11, The cleaning process using the SC-1 solution is carried out by dipping the wafer into the SC-1 solution at 15 to 90 DEG C for 1 to 10 minutes. The method according to claim 1 or 9, The piranha solution is a method of manufacturing a semiconductor device, characterized in that the H ₂ SO ₄ : H ₂ O ₂ is a mixture of 2 to 4: 1 by volume ratio. The method of claim 13, The cleaning process using the piranha solution is carried out by dipping in the piranha solution at 85 to 150 ° C. for 1 to 10 minutes.