JPS6410649A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6410649A
JPS6410649A JP16631587A JP16631587A JPS6410649A JP S6410649 A JPS6410649 A JP S6410649A JP 16631587 A JP16631587 A JP 16631587A JP 16631587 A JP16631587 A JP 16631587A JP S6410649 A JPS6410649 A JP S6410649A
Authority
JP
Japan
Prior art keywords
insulating film
wiring layer
wall
contact hole
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16631587A
Other languages
Japanese (ja)
Inventor
Takeshi Okazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16631587A priority Critical patent/JPS6410649A/en
Publication of JPS6410649A publication Critical patent/JPS6410649A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make a contact hole in the manner of self alignment, and realize a fine structure, by forming an aperture part reaching a second specified region of a main surface in the vicinity of a first wiring layer by an etching method with anisotropy, and forming via the aperture part a second wiring layer extending on an insulating layer. CONSTITUTION:An impurity diffusion region 15 and a third insulating film 16 covering the side surfaces of a second insulating film 14 and a first wiring layer 13 are formed. When a contact hole is made in the third insulating film 16, a part of the third insulating film which is so called a side-wall is left on the side-walls of the first wiring layer 13 and the second insulating layer 14. This side-wall is inevitably formed on a vertical side-wall in the case of an etching such as RIE. Therefore, the first wiring layer is always protected by an insulating film (a part of the third insulating film), even if the contact hole is formed under the condition where the margin of mask alignment is zero. A second wiring layer is formed so as to come into electrical contact with the impurity diffusion region 15.
JP16631587A 1987-07-02 1987-07-02 Manufacture of semiconductor device Pending JPS6410649A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16631587A JPS6410649A (en) 1987-07-02 1987-07-02 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16631587A JPS6410649A (en) 1987-07-02 1987-07-02 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6410649A true JPS6410649A (en) 1989-01-13

Family

ID=15829070

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16631587A Pending JPS6410649A (en) 1987-07-02 1987-07-02 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6410649A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100265828B1 (en) * 1997-06-30 2000-09-15 김영환 A method for fabricating semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61174742A (en) * 1985-01-30 1986-08-06 Toshiba Corp Manufacture of semiconductor device
JPS6240765A (en) * 1985-08-15 1987-02-21 Toshiba Corp Read-only semiconductor memory and manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61174742A (en) * 1985-01-30 1986-08-06 Toshiba Corp Manufacture of semiconductor device
JPS6240765A (en) * 1985-08-15 1987-02-21 Toshiba Corp Read-only semiconductor memory and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100265828B1 (en) * 1997-06-30 2000-09-15 김영환 A method for fabricating semiconductor device

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