JPS6435937A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6435937A
JPS6435937A JP19002687A JP19002687A JPS6435937A JP S6435937 A JPS6435937 A JP S6435937A JP 19002687 A JP19002687 A JP 19002687A JP 19002687 A JP19002687 A JP 19002687A JP S6435937 A JPS6435937 A JP S6435937A
Authority
JP
Japan
Prior art keywords
wiring
width
film
wirings
aperture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19002687A
Other languages
Japanese (ja)
Inventor
Katsuyoshi Washio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP19002687A priority Critical patent/JPS6435937A/en
Publication of JPS6435937A publication Critical patent/JPS6435937A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make it possible to provide respectively through holes of the same width as a wiring width on fine wirings by a method wherein a first insulating layer having an aperture, a second insulating layer of a height equal almost with that of a first conducting layer for wiring and a second conducting layer for wiring, which is connected electrically with the first conducting layer through the aperture of the first insulating layer, are provided. CONSTITUTION:A wiring width at places, where are used as apertures (through holes) on wirings 10, is formed into the minimum processing dimension and an aperture of a first insulating film 5, which is larger by the amount of a mask alignment margin, is provided from the wiring 10. A second insulating film 30 is provided on the film 5 and its height is made equal with that of the wirings 10. Thereby, the wiring upper surface, which is not covered with the film 5, is exposed and an electrical connection with an upper wiring 20 can be obtained. Here, the film 30 exists on the side surfaces of the wirings at the through hole parts, the wiring upper surface only is exposed and the effective width of the through holes can be formed in the same width as the wiring width formed by processing in the minimum dimension.
JP19002687A 1987-07-31 1987-07-31 Semiconductor device Pending JPS6435937A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19002687A JPS6435937A (en) 1987-07-31 1987-07-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19002687A JPS6435937A (en) 1987-07-31 1987-07-31 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6435937A true JPS6435937A (en) 1989-02-07

Family

ID=16251135

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19002687A Pending JPS6435937A (en) 1987-07-31 1987-07-31 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6435937A (en)

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