JPS6477177A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6477177A
JPS6477177A JP23378587A JP23378587A JPS6477177A JP S6477177 A JPS6477177 A JP S6477177A JP 23378587 A JP23378587 A JP 23378587A JP 23378587 A JP23378587 A JP 23378587A JP S6477177 A JPS6477177 A JP S6477177A
Authority
JP
Japan
Prior art keywords
gaas
layer
inas
semiconductor layer
mbe
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23378587A
Other languages
Japanese (ja)
Inventor
Hideki Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP23378587A priority Critical patent/JPS6477177A/en
Publication of JPS6477177A publication Critical patent/JPS6477177A/en
Pending legal-status Critical Current

Links

Landscapes

  • Weting (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To allow a first semiconductor layer to be exposed without damage by a method wherein a second semiconductor layer constituting a contact layer is exposed to an etchant not affecting the first semiconductor layer to be a channel layer. CONSTITUTION:An N-GaAs layer 32 is formed by an epitaxial growth technique, such as MBE or OMVPE, on a GaAs substrate 30. Next, InAs atom layers 3 and GaAs atom layers 1 are formed by MBE on the N-GaAs layer 32, one upon the other, into an InAs-GaAs superlattice laminate 34. After this, a resist pattern 36 is formed, which is provided with an opening 36A at a location for a recess. A process follow wherein the resist pattern 36 serves as a mask in wet etching using hydrochloric acid. GaAs is not affected by hydrochloric acid but InAs is. As the result, the InAs-GaAs superlattice laminate 34 not protected by the resist 36 is etched away, without any noticeable damage left in the surface of the N-GaAs layer 32.
JP23378587A 1987-09-18 1987-09-18 Manufacture of semiconductor device Pending JPS6477177A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23378587A JPS6477177A (en) 1987-09-18 1987-09-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23378587A JPS6477177A (en) 1987-09-18 1987-09-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6477177A true JPS6477177A (en) 1989-03-23

Family

ID=16960531

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23378587A Pending JPS6477177A (en) 1987-09-18 1987-09-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6477177A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0218965A (en) * 1988-07-07 1990-01-23 Fujitsu Ltd Ohmic contact structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0218965A (en) * 1988-07-07 1990-01-23 Fujitsu Ltd Ohmic contact structure

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