KR19990030935A - Contact Forming Method of Semiconductor Device for Reducing Contact Resistance - Google Patents
Contact Forming Method of Semiconductor Device for Reducing Contact Resistance Download PDFInfo
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- KR19990030935A KR19990030935A KR1019970051426A KR19970051426A KR19990030935A KR 19990030935 A KR19990030935 A KR 19990030935A KR 1019970051426 A KR1019970051426 A KR 1019970051426A KR 19970051426 A KR19970051426 A KR 19970051426A KR 19990030935 A KR19990030935 A KR 19990030935A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
반도체 소자의 콘택형성 공정에서, 콘택저항을 낮추기 위하여 부도체 박막의 생성을 방지하거나 생성된 부도체 박막을 제거하는 개선된 방법이 개시된다. 서로 다른 도전층들간을 전기적으로 서로 연결하기 위해 층간 절연막을 통하여 콘택을 형성시 생성 가능한 부도체 박막은 콘택 개구의 형성직후에 비교적 높은 고주파로써 프리크리닝을 하거나 열적 분해를 함으로써 제거되며, 상기 콘택개구에 충진될 내열금속물질을 도포하기 직전에 반응 방지막을 개구상면에 도포하거나 상기 내열금속물질의 도포시 사용 가스량의 혼합비를 설정된 비율로 유지시킴으로써 생성이 방지된다.In the process of forming a semiconductor device, an improved method of preventing the formation of non-conductor thin films or removing the resulting non-conductor thin films in order to lower the contact resistance is disclosed. The non-conductive thin film that can be generated when forming a contact through an interlayer insulating film to electrically connect different conductive layers to each other is removed by precleaning or thermal decomposition at a relatively high frequency immediately after formation of the contact opening. The production is prevented by applying a reaction prevention film to the upper surface of the opening immediately before applying the heat-resistant metal material to be filled or by maintaining the mixing ratio of the amount of gas used in the application of the heat-resistant metal material at a set ratio.
Description
본 발명은 고집적 반도체 소자의 제조시 서로 다른 도전층들간을 전기적으로 서로 연결하기 위한 상호연결 방법에 관한 것으로, 특히 콘택 저항을 저감시킬 수 있는 콘택형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interconnection method for electrically connecting different conductive layers to each other in the manufacture of highly integrated semiconductor devices, and more particularly, to a contact formation method capable of reducing contact resistance.
일찌기 트랜지스터 소자들을 집적하는 기술이 본 분야에 소개된 이래로, 반도체 집적회로는 웨이퍼 프로세스기술의 진보에 따라 비약적으로 고집적 되어져 왔다. 마침내, VLSI시대를 거쳐 64비트 MPU 또는 수백메가 내지 수기가 비트급 저장용량의 DRAM을 등장시키고 있는 초고집적 집적회로(ULSI)시대가 도래되었다. 이에 따라 소자를 구성하는 서로 다른 도전층들간을 전기적으로 서로 연결하기 위한 상호연결기술도 더욱 어려워 지고 있다.Since the technology of integrating transistor devices was introduced in the art, semiconductor integrated circuits have been dramatically integrated with advances in wafer process technology. Finally, the VLSI era has led to the era of ultra-high-density integrated circuits (ULSI), where 64-bit MPUs or hundreds of mega to handheld DRAMs have emerged. Accordingly, interconnect technologies for electrically connecting the different conductive layers constituting the device become more difficult.
동일 웨이퍼상에 모오스 트랜지스터 소자들을 형성한 후에, 소자제조의 마지막 단계로서 콘택형성공정이 서로 다른 도전층들간의 전기적인 연결을 위해서 통상적으로 수행된다. 보다 고집적,고밀도화된 논리 디바이스등의 제조시에 다층배선의 필요상 약 0.4미크론 미터이하의 직경을 가지는 미세콘택이 채용된다. 그러한 경우에, 콘택은 층간절연막을 개재하여 통상 실리사이드층과 내열성 금속층간에 이루어진다. 그런데, 콘택의 형성을 위한 제조공정에 기인하여 콘택부분의 저항이 예측되는 값 이상으로 증가되는 문제가 있다. 따라서, 콘택특성을 양호하게 하기 위해 콘택저항을 줄이는 콘택형성 방법이 본 분야에서 절실히 요구된다.After forming the MOS transistor devices on the same wafer, as a final step in device fabrication, a contact forming process is typically performed for electrical connection between different conductive layers. In the manufacture of more integrated and denser logic devices, microcontacts having a diameter of about 0.4 micron or less are employed for the necessity of multilayer wiring. In such a case, the contact is usually made between the silicide layer and the heat resistant metal layer via the interlayer insulating film. However, there is a problem that the resistance of the contact portion is increased beyond the expected value due to the manufacturing process for forming the contact. Therefore, there is an urgent need in the art for a contact forming method for reducing contact resistance in order to improve contact characteristics.
따라서, 본 발명의 목적은 콘택 저항을 감소시킬 수 있는 콘택제조 방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a contact that can reduce the contact resistance.
본 발명의 다른 목적은 부도체 박막의 개재없이 저저항의 콘택을 형성할 수 있는 반도체 소자의 콘택형성 방법을 제공함에 있다.Another object of the present invention is to provide a method for forming a contact of a semiconductor device capable of forming a low resistance contact without interposing a non-conductive thin film.
본 발명의 또 다른 목적은 실리사이드층과 내열성 금속층간의 콘택특성을 양호하게 할 수 있는 고집적 반도체 소자의 콘택형성 방법을 제공함에 있다.It is still another object of the present invention to provide a method for forming a highly integrated semiconductor device, which can improve contact characteristics between a silicide layer and a heat resistant metal layer.
도 1 내지 도 3은 본 발명의 일 실시예에 따른 반도체 소자의 콘택 형성을 위한 공정순서를 보여주는 단면도들.1 to 3 are cross-sectional views illustrating a process sequence for forming a contact of a semiconductor device according to an embodiment of the present invention.
상기의 목적들을 달성하기 위한 본 발명에 따른 콘택형성 방법은, 콘택을 형성시 생성 가능한 부도체 박막을 제거하기 위해 콘택 개구의 형성직후에 비교적 높은 고주파로써 프리크리닝을 하거나 열적 분해를 하는 단계와, 생성 가능한 부도체 박막의 생성을 방지하기 위해 콘택개구에 충진될 내열금속물질을 도포하기 직전에 반응 방지막을 개구상면에 도포하거나 상기 내열금속물질의 도포시 사용 가스량의 혼합비를 설정된 비율로 유지시키는 단계를 가짐을 특징으로 한다.The contact forming method according to the present invention for achieving the above object comprises the steps of pre-cleaning or thermal decomposition at a relatively high frequency immediately after the formation of the contact opening to remove the non-conducting thin film that can be generated when forming the contact, and In order to prevent the formation of a possible non-conductive thin film, the reaction prevention film is applied to the upper surface of the opening immediately before the application of the heat-resistant metal material to be filled in the contact opening, or the mixing ratio of the amount of gas used in the application of the heat-resistant metal material is maintained at a predetermined ratio. It is characterized by.
상기한 방법에 따르면, 콘택 계면부에는 플루오르 화합물등과 같은 부도체 박막이 존재하지 않아 콘택특성은 양호하게 된다.According to the above method, there is no non-conductive thin film such as a fluorine compound in the contact interface portion, and the contact characteristics are good.
이하 본 발명에 따른 바람직한 실시예가 첨부된 도면을 참조하여 상세히 설명되어질 것이다. 첨부된 도면들내에서 서로 동일한 구성층은 다른 도면내에 있더라도 이해의 편의를 위해서 동일 내지 유사한 참조부호 또는 명칭으로 라벨링된다. 다음의 설명에서는 본 발명의 보다 철저한 이해를 제공하기 위해 특정한 상세들이 예를들어 한정되고 자세하게 설명된다. 그러나, 당해 기술분야에 통상의 지식을 가진 자들에게 있어서는 본 발명이 이러한 상세한 항목들이 없이도 상기한 설명에 의해서만 실시될 수 있을 것이다. 또한, 본 분야에 너무나 잘 알려진 반도체 소자의 제조공정의 기본적 순서 및 제조의 장비등은 본 발명의 요지를 흐리지 않게 하기 위해 상세히 설명되지 않는다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same constituent layers are labeled with the same or similar reference numerals or names for convenience of understanding even if they are in different drawings. In the following description, specific details are set forth by way of example and in detail in order to provide a more thorough understanding of the present invention. However, for those of ordinary skill in the art, the present invention may be practiced only by the above description without these details. In addition, the basic order of the manufacturing process of the semiconductor device so well known in the art, the equipment of manufacture, and the like are not described in detail in order not to obscure the subject matter of the present invention.
먼저, 본 발명에 대한 이해를 더욱 철저히 하기 위해, 본 발명이 창작되기 까지의 과정을 간략히 설명한다. 반도체 논리 디바이스등의 제조분야에서 미세한 콘택형성을 위해 약 0.4미크론 미터이하의 직경을 가지는 콘택개구(또는 콘택 홀)가 티타늄 실리사이드층의 상부를 노출시키기 위해 층간 절연막에 형성된다. 상기 콘택 개구의 형성은 통상의 건식 식각공정으로써 달성된다. 상기 형성된 콘택 개구에 텡스텐등의 금속을 화학기상증착법(CVD)으로 충진하고 그 상부에 알루미늄 등의 금속을 도포함으로써 콘택의 제조는 완료된다. 그런데, 상기 티타늄 실리사이드층과 상기 텡스텐 금속층사이의 콘택저항이 예측되는 값 이상으로 증가되어 전기전도도가 양호하지 못한 현상이 발생되었다. 상기한 현상에 대한 원인을 규명하고자 본 발명자는 심혈을 기울였다. 그 결과로서, 티타늄 실리사이드층과 상기 텡스텐 금속층사이의 계면에 부도체 박막인 TiFx(여기서,x는 자연수)가 존재하는 것이 드디어 관찰되었다. 이는 전자사진 현미경으로써 본 발명자가 발견한 것이다. 바로 이러한 부도체 박막의 생성 때문에 콘택계면부의 저항이 예상외로 증가되었던 것이다. 따라서, 부도체 박막의 생성원인을 밝혀야할 필요성이 있었다. 결과로서, 콘택형성을 위해 건식 식각공정과 텡스텐(W) CVD공정에서 필수적으로 사용되는 가스 예를들면 CF4,CHF3, 또는 WF6의 플로오르(F)성분과 티타늄 실리사이드(TiSi2)의 Ti가 공정의 진행중에 서로 화학적으로 반응되어 TiFx를 생성함을 알게 되었다. 상기 플루오르 화합물 부도체 막은 수십 내지 수백 Å정도로 매우 얇기 때문에 쉽게 발견되기 어렵다. 또한, 그 생성원인도 규명하기에 힘들었다. 그러한 TiFx막은, 콘택 개구의 형성 후에 통상적으로 개구내의 불순물을 제거하기 위해 수행하는 에싱 또는 황산 스트립 공정에 의해서도 쉽게 제거되지 않는다. 그러기에 본 분야에서는 콘택저항이 높은 원인을 쉽게 규명하기 어려웠던 것이다. 그렇지만, 본 발명자는 다행히도 약 200Å의 부도체 박막을 TEM 전자현미경으로 발견하였으며, 마침내 생성원인을 알아낸 것이다.First, in order to further understand the present invention, a brief description of the process until the present invention is made. A contact opening (or contact hole) having a diameter of about 0.4 micron or less is formed in the interlayer insulating film to expose the top of the titanium silicide layer for the manufacture of fine contacts in the manufacturing field of semiconductor logic devices and the like. Formation of the contact opening is accomplished by a conventional dry etching process. The manufacture of the contact is completed by filling the formed contact opening with a metal such as tungsten by chemical vapor deposition (CVD) and applying a metal such as aluminum on top thereof. However, the contact resistance between the titanium silicide layer and the tungsten metal layer was increased to a value higher than expected, resulting in a poor electrical conductivity. The inventors of the present invention have made a great effort to determine the cause of the above phenomenon. As a result, it was finally observed that TiFx, where x is a natural number, of an insulator thin film was present at the interface between the titanium silicide layer and the tungsten metal layer. This is what the inventors have discovered with an electrophotographic microscope. Because of this inductor thin film, the contact interface resistance increased unexpectedly. Therefore, there was a need to identify the cause of the formation of the insulator thin film. As a result, gases used in dry etching and tungsten (W) CVD processes for contact formation, such as the fluorine (F) component of CF4, CHF3, or WF6 and Ti of titanium silicide (TiSi2) It was found that chemical reactions with each other during the formation of TiFx. The fluorine compound insulator film is very thin, on the order of tens to hundreds of micrometers, and is therefore difficult to find. In addition, the cause of the production was also difficult to identify. Such TiFx films are not easily removed by an ashing or sulfuric acid strip process, which is usually performed after removal of the contact openings to remove impurities in the openings. Therefore, in this field, it was difficult to easily determine the cause of high contact resistance. However, the inventors have fortunately discovered a thin film of about 200 microns of insulator thin film by TEM electron microscopy, and finally found the cause of the formation.
이하에서는 부도체 박막의 생성을 방지하거나 생성된 부도체 박막을 제거하는 방법을 보다 쉽게 알 수 있도록 하기 위해, 모오스 트랜지스터의 경우를 예를들어 첨부도면을 참조하여 설명한다.Hereinafter, the MOS transistor will be described with reference to the accompanying drawings, for example, in order to more easily understand a method of preventing the formation of the non-conductor thin film or removing the generated non-conductor thin film.
도 1을 참조하면, 반도체 기판 2상에 드레인 5와 소오스 4 영역을 가지며, 게이트 절연막 6을 통하여 폴리실리콘 재질의 게이트 10를 가지는 하나의 모오스 트랜지스터가 도시된다. 상기 게이트 10의 두께는 약 3000Å정도이다. 상기 게이트 10의 측벽에는 산화막 스페이서 8가 통상의 에치 백공정으로써 형성되며, 소자의 동작특성을 개선하기 위해 상기 게이트 10의 상부와 상기 드레인 5 및 소오스 4 영역의 상부에는 티타늄등의 내열금속 실리사이드 층 12이 형성된다. 엄격히 말해, 상기 게이트 10의 상부에 형성되는 층 12은 티타늄 폴리사이드 층이고, 드레인 5 및 소오스 4 영역의 상부에 형성되는 층 12은 티타늄 실리사이드 층이다. 상기한 도 1에 도시된 바와 같은 구조의 세부적인 제조공정은 본 분야에 통상적으로 널리 알려져 있다.Referring to FIG. 1, one MOS transistor having a drain 5 and a source 4 region on a semiconductor substrate 2 and having a gate 10 made of polysilicon through a gate insulating layer 6 is illustrated. The thickness of the gate 10 is about 3000 kPa. An oxide spacer 8 is formed on the sidewall of the gate 10 by a conventional etch back process, and a heat-resistant metal silicide layer such as titanium is formed on the upper portion of the gate 10 and the drain 5 and source 4 regions to improve the operation characteristics of the device. 12 is formed. Strictly speaking, layer 12 formed on top of gate 10 is a titanium polyside layer and layer 12 formed on top of drain 5 and source 4 regions is a titanium silicide layer. Detailed manufacturing process of the structure as shown in Figure 1 above is commonly known in the art.
도 2를 참조하면, 콘택 개구 21를 형성하는 공정이 나타난다. 다수의 콘택 개구 21의 형성은, 상기 도 1의 구조상부에 더하여 층간 절연막으로서 산화막 14를 전체적으로 약 13500Å정도의 두께로 증착한 후, 사진식각공정을 수행하여 포토레지스트 층 19 하부의 노출된 산화막 14을 반응성 이온 식각(RIE)법등으로써 CHF3 가스 분위기에서 건식 식각함에 의해 달성된다. 따라서, 건식 이방성 식각에 의해 상기 내열금속 실리사이드 층 12의 일부 상부는 상기 콘택 개구 21를 통해 노출된다. 여기서, 상기 콘택 개구 21의 직경은 약 0.4미크론 미터이다. 상기 건식식각의 진행중에 상기 CHF3 가스와 실리사이드 층 12내의 티타늄이 반응하여 상기한 플루오르 화합물인 부도체 박막을 생성할 수 있으므로, 본 실시예에서는 비교적 높은 고주파로써 프리크리닝을 하거나 열적 분해를 하는 공정을 실시한다. 상기 프리크리닝 공정은 예컨대 AMEE(Applied Magnetic Enhenced Etcher)장비를 이용하여 고주파 파워를 약 300-400와트(W)정도로 유지시킨 상태로 수행된다. 상기 프리크리닝공정 수행에 의해 상기 부도체 박막은 식각된다. 또한, 프리크리닝 공정을 수행하지 못할 경우에는 상기 부도체 박막의 제거를 위해 열적분해 공정을 실시할 수 있다. 이 공정은 약 460도씨 내지 560도씨의 온도범위에서 행하는 디가스(degas)공정에 의해 달성된다. 상기 부도체 박막은 400도씨 이하에서 용융되는 막이므로 상기 디가스 공정을 실시할 경우에 기체상태로 휘발된다. 여기서, 상기 부도체 박막의 제거를 위해, 상기 프리크리닝 공정 또는 열적 분해공정을 선택적으로 진행할 수 있지만, 사안의 허용상 두 개의 공정을 연달아 실시하여도 무방함에 주목하여야 한다.Referring to FIG. 2, a process of forming contact openings 21 is shown. The formation of the plurality of contact openings 21 is performed by depositing an oxide film 14 as a total thickness of about 13500 Å as an interlayer insulating film in addition to the upper portion of the structure of FIG. 1, and then performing a photolithography process to expose the exposed oxide film 14 under the photoresist layer 19. Is achieved by dry etching in a CHF3 gas atmosphere, such as by reactive ion etching (RIE). Thus, some top of the heat resistant metal silicide layer 12 is exposed through the contact opening 21 by dry anisotropic etching. Here, the diameter of the contact opening 21 is about 0.4 microns. During the dry etching process, the CHF3 gas and the titanium in the silicide layer 12 may react to form the non-conductive thin film of the fluorine compound. In this embodiment, a pre-cleaning process or a thermal decomposition process is performed at a relatively high frequency. do. The precleaning process is performed by maintaining high frequency power at about 300-400 watts (WEE) using, for example, an Applied Magnetic Enhanced Etcher (AMEE) device. The nonconductive thin film is etched by performing the precleaning process. In addition, when the precleaning process cannot be performed, a thermal decomposition process may be performed to remove the non-conductive thin film. This process is accomplished by a degas process performed in the temperature range of about 460 degrees Celsius to 560 degrees Celsius. The non-conductive thin film is a film that melts at 400 ° C. or lower, and thus volatilizes in a gas state when the degas process is performed. Here, in order to remove the insulator thin film, the precleaning process or the thermal decomposition process may be selectively performed, but it should be noted that two processes may be successively performed in order to allow for the case.
상기한 바와 같이 프리크리닝을 하거나 열적 분해를 하는 공정을 실시 한 후에도 이후의 금속도포공정에서 또 다시 부도체 박막이 콘택의 계면부에 생성될 수 있다. 이를 방지하기 위해, 도 3에서 보여지는 바와같이, 약 100-200Å의 티타늄 막 16과 약 400-700Å의 질화티타늄 막 18이 차례로 증착된다. 여기서, 상기 막들의 증착 공정은 상기 콘택개구 21내에 충진될 내열금속물질 예컨대 텡스텐을 CVD로 도포하기 직전에 수행된다. 상기 질화 티타늄 막 18은 플루오르 이온이 하부의 실리사이드 막 12으로 침투되지 못하게 하는 반응 방지막 역할을 한다. 상기 막 18의 형성후에 비로서 텡스텐 금속을 SiH4와 WF6의 혼합가스분위기에서 CVD공법으로 데포지션한다. 결과로서, 텡스텐 콘택 플러그 20가 상기 콘택 개구 21내에 충진된다. 여기서, 상기 반응 방지막 18에 의해 부도체 박막의 생성이 방지된다. 또한, 상기 혼합 가스의 양은 SiH4을 1로 할 경우에 상기 WF6를 8정도로 하여 약 1:8정도로 유지시켜주는 것이 좋다. 이 또한 상기 부도체 박막의 생성을 방지하기 위해서이다.Even after performing the pre-cleaning or thermal decomposition process as described above, in the subsequent metal coating process, the non-conductive thin film may be formed at the interface portion of the contact again. To prevent this, as shown in FIG. 3, about 100-200 μs of titanium film 16 and about 400-700 μs of titanium nitride film 18 are deposited in sequence. Here, the deposition process of the films is performed immediately before CVD of a heat-resistant metal material such as tungsten to be filled in the contact opening 21. The titanium nitride film 18 serves as a reaction prevention film to prevent fluorine ions from penetrating into the lower silicide film 12. After formation of the film 18, the tungsten metal was deposited by the CVD method in a mixed gas atmosphere of SiH4 and WF6. As a result, the tungsten contact plug 20 is filled in the contact opening 21. Here, the non-conductive thin film is prevented by the reaction prevention film 18. In addition, the amount of the mixed gas is preferably maintained at about 1: 8 with the WF6 of about 8 when SiH4 is 1. This is also to prevent the formation of the insulator thin film.
상기 콘택 플러그 20를 형성한 후, 배선용 금속 예컨대 알루미늄을 증착하여 배선층 22를 형성하면 콘택의 제조공정은 완성된다.After the contact plug 20 is formed, the wiring layer 22 is formed by depositing a wiring metal such as aluminum to complete the manufacturing process of the contact.
상기한 바와 같이, 콘택제조시 콘택 계면부에는 플루오르 화합물 부도체 박막이 제거되거나 방지되어 존재하지 아니하므로 양호한 콘택 특성이 얻어진다.As described above, good contact characteristics are obtained because the fluorine compound insulator thin film is not removed or prevented from being present at the contact interface portion during the manufacture of the contact.
상기한 본 발명은 도면을 중심으로 예를들어 설명되고 한정되었지만, 그 동일한 것은 본 발명의 기술적 사상을 벗어나지 않는 범위내에서 여러가지 변화와 변형이 가능함이 본 분야의 숙련된 자에게 있어 명백할 것이다. 예컨대 상기 실리사이드 층이 티타늄 실리사이드로 형성되었지만, 몰리브덴, 탄탈늄, 텡스텐 등의 또 다른 내열금속으로 사용할 수 있다.Although the above-described invention has been described and limited by way of example with reference to the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. For example, the silicide layer is formed of titanium silicide, but may be used as another heat-resistant metal such as molybdenum, tantalum, and tungsten.
상술한 바와 같이 본 발명에 따르면, 콘택저항을 저감하여 반도체 소자의 동작 신뢰성을 개선하는 효과가 있다.As described above, according to the present invention, there is an effect of reducing the contact resistance to improve the operation reliability of the semiconductor device.
Claims (10)
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| KR1019970051426A KR100251225B1 (en) | 1997-10-07 | 1997-10-07 | Contact forming method for reducing contact resistance in semiconductor device |
| JP10144143A JPH11121622A (en) | 1997-10-07 | 1998-05-26 | Method of forming semiconductor element contact |
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| KR1019970051426A KR100251225B1 (en) | 1997-10-07 | 1997-10-07 | Contact forming method for reducing contact resistance in semiconductor device |
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| KR100477817B1 (en) * | 1997-12-27 | 2005-07-04 | 주식회사 하이닉스반도체 | Semiconductor device manufacturing method |
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| KR101044384B1 (en) | 2004-03-18 | 2011-06-29 | 매그나칩 반도체 유한회사 | Method for forming resistor of semiconductor device |
| US7518196B2 (en) | 2005-02-23 | 2009-04-14 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
| CN102376625B (en) * | 2010-08-11 | 2014-03-19 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN102376686B (en) * | 2010-08-11 | 2013-09-18 | 中国科学院微电子研究所 | Semiconductor device and production method thereof |
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1997
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| KR100477817B1 (en) * | 1997-12-27 | 2005-07-04 | 주식회사 하이닉스반도체 | Semiconductor device manufacturing method |
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