KR20020058430A - Method for fabricating a wire in semiconductor device - Google Patents
Method for fabricating a wire in semiconductor device Download PDFInfo
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- KR20020058430A KR20020058430A KR1020000086535A KR20000086535A KR20020058430A KR 20020058430 A KR20020058430 A KR 20020058430A KR 1020000086535 A KR1020000086535 A KR 1020000086535A KR 20000086535 A KR20000086535 A KR 20000086535A KR 20020058430 A KR20020058430 A KR 20020058430A
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- forming
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title abstract description 18
- 239000010410 layer Substances 0.000 claims abstract description 44
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 40
- 239000010937 tungsten Substances 0.000 claims abstract description 40
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 40
- 239000010936 titanium Substances 0.000 claims abstract description 30
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 27
- 239000011229 interlayer Substances 0.000 claims abstract description 27
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 27
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 8
- 238000005240 physical vapour deposition Methods 0.000 claims abstract description 4
- 230000004888 barrier function Effects 0.000 claims description 20
- 238000009792 diffusion process Methods 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 8
- 229910010282 TiON Inorganic materials 0.000 claims description 5
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 229910052731 fluorine Inorganic materials 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- 238000009832 plasma treatment Methods 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 12
- CCEKAJIANROZEO-UHFFFAOYSA-N sulfluramid Chemical group CCNS(=O)(=O)C(F)(F)C(F)(F)C(F)(F)C(F)(F)C(F)(F)C(F)(F)C(F)(F)C(F)(F)F CCEKAJIANROZEO-UHFFFAOYSA-N 0.000 abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- 229910052782 aluminium Inorganic materials 0.000 abstract description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 8
- 239000000126 substance Substances 0.000 abstract description 3
- 238000007517 polishing process Methods 0.000 abstract description 2
- 239000004411 aluminium Substances 0.000 abstract 2
- 238000005530 etching Methods 0.000 abstract 1
- 125000001153 fluoro group Chemical group F* 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자에 대한 것으로, 특히 콘택홀 상부 에지에서 결함발생을 방지하기에 알맞은 반도체소자의 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for forming a wiring of a semiconductor device suitable for preventing a defect from occurring at an upper edge of a contact hole.
첨부 도면을 참조하여 종래 반도체소자의 배선 형성방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a method of forming a wiring of a conventional semiconductor device will be described below.
도 1a 내지 도 1c는 종래 반도체소자의 배선 형성방법을 나타낸 공정단면도이고, 도 2는 종래 공정단계시 나타난 문제점을 나타낸 구조단면도이다.1A through 1C are cross-sectional views illustrating a method of forming a wiring of a conventional semiconductor device, and FIG.
종래 반도체소자의 배선 형성방법은 도 1a에 도시한 바와 같이 실리콘기판(1)의 일영역상에 하부배선층(2)을 형성하고, 하부배선층(2)을 포함한 실리콘기판(1)상에 층간절연막(3)을 형성한다.In the conventional method of forming a wiring of a semiconductor device, as shown in FIG. 1A, a lower wiring layer 2 is formed on a region of a silicon substrate 1, and an interlayer insulating film is formed on the silicon substrate 1 including the lower wiring layer 2. (3) is formed.
그리고 도 1b에 도시한 바와 같이 사진식각공정으로 층간절연막(3)을 이방성 식각해서 하부배선층(2)의 일부분이 드러나도록 비아홀을 형성한다.As shown in FIG. 1B, the interlayer insulating layer 3 is anisotropically etched by a photolithography process to form a via hole so that a part of the lower wiring layer 2 is exposed.
이어서 비아홀을 포함한 층간절연막(3)상에 베리어 메탈층으로 티타늄막(4)과 티타늄 나이트라이드막(5)을 차례로 증착한다.Subsequently, a titanium film 4 and a titanium nitride film 5 are sequentially deposited on the interlayer insulating film 3 including the via hole as a barrier metal layer.
그리고 도 1c에 도시한 바와 같이 화학 기상 증착(Chemical Vapor Deposition:CVD)법으로 비아홀을 채우도록 텅스텐막(6)을 증착한다.As shown in FIG. 1C, a tungsten film 6 is deposited to fill the via hole by chemical vapor deposition (CVD).
이때 텅스텐막(6)을 증착할 때 소오스 가스로 WF6를 사용하는데 F원자가 하부의 티타늄 나이트라이드막(5)의 결정립계를 통하여 티타늄막(4)으로 확산되어서 비아홀 상부 에지부분에 TiFx성분이 생기는 볼케이노 결함(Volcano defect)을 유발한다.At this time, when depositing the tungsten film 6, WF6 is used as the source gas, and a volcano in which the F atom is diffused into the titanium film 4 through the grain boundary of the titanium nitride film 5 at the bottom to form a TiFx component in the upper edge portion of the via hole. It causes a Volcano defect.
이와 같은 볼케이노 결함에 의해서 도 2에 도시한 바와 같이 비아홀 상부 에지의 티타늄 나이트라이드막(5)이 끊어지는 문제가 발생하고, 또한 비아홀내에는 보이드(Void)가 발생할 수 있다.Due to such volcano defects, the titanium nitride film 5 at the upper edge of the via hole is broken as shown in FIG. 2, and voids may occur in the via hole.
이후에는 도면에 도시되지 않았지만 텅스텐을 평탄화하여 비아홀내에 텅스텐 플러그를 형성하고, 텅스텐 플러그와 접촉하게 층간절연막(3)상에 배선층을 형성한다.Thereafter, although not shown in the drawing, tungsten is planarized to form a tungsten plug in the via hole, and a wiring layer is formed on the interlayer insulating film 3 in contact with the tungsten plug.
상기와 같은 종래 반도체소자의 배선 형성방법은 다음과 같은 문제가 있다.The wiring formation method of the conventional semiconductor device as described above has the following problems.
텅스텐 플러그를 형성할 때 WF6의 소오스 가스중 F원자가 하부의 베리어 메탈층인 티타늄 나이트라이드막의 결정립계를 통하여 티타늄막으로 확산되어서 비아홀 상부 에지에 볼케이노 결함이 발생하여 텅스텐 플러그의 전기적 특성이 열화되고 이에 따라서 제조수율이 떨어지고 배선의 신뢰성이 저하되는 문제가 발생한다.When forming the tungsten plug, F atoms in the source gas of WF6 diffuse into the titanium film through the grain boundary of the titanium nitride film, which is the lower barrier metal layer, resulting in a volcano defect at the upper edge of the via hole, thereby deteriorating the electrical properties of the tungsten plug. The production yield falls and the reliability of wiring decreases.
본 발명은 상기와 같은 문제를 해결하기 위하여 안출한 것으로 특히, 볼케이노 결함발생을 방지하여 배선의 신뢰성을 향상시키고 제조 수율을 높이기에 알맞은 반도체소자의 배선 형성방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for forming a wiring of a semiconductor device suitable for preventing volcano defects from occurring and improving the reliability of the wiring and increasing the manufacturing yield.
도 1a 내지 도 1c는 종래 반도체소자의 배선 형성방법을 나타낸 공정단면도1A to 1C are cross-sectional views illustrating a method of forming a wiring of a conventional semiconductor device.
도 2는 종래 공정단계시 나타난 문제점을 나타낸 구조단면도Figure 2 is a structural cross-sectional view showing a problem appeared in the conventional process step
도 3a 내지 도 3d는 본 발명 제 1 실시예에 따른 반도체소자의 배선 형성방법을 나타낸 공정단면도3A through 3D are cross-sectional views illustrating a method of forming wirings in a semiconductor device in accordance with a first embodiment of the present invention.
도 4a 내지 도 4d는 본 발명 제 2 실시예에 따른 반도체소자의 배선 형성방법을 나타낸 공정단면도4A through 4D are cross-sectional views illustrating a method of forming wirings in a semiconductor device in accordance with a second embodiment of the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21,31 : 실리콘기판 22,32 : 하부배선층21,31: Silicon substrate 22,32: Lower wiring layer
23,33 : 층간절연막 24,34 : 제 1 티타늄막23, 33 interlayer insulating film 24, 34 first titanium film
25,35 : 티타늄 나이트라이드막 26 : 텅스텐막25,35: titanium nitride film 26: tungsten film
27,36 : 텅스텐 플러그 28,37 : 제 2 티타늄막27,36: tungsten plug 28,37: second titanium film
29,38 : 알루미늄 배선29,38: aluminum wiring
상기와 같은 목적을 달성하기 위한 본 발명 반도체소자의 배선 형성방법은 기판상에 콘택홀을 구비한 층간절연막을 형성하는 공정, 상기 콘택홀 및 상기 층간절연막상에 베리어 메탈층을 형성하는 공정, 상기 콘택홀을 포함한 베리어 메탈층상에 플루오르(F) 원자의 확산을 방지하는 확산방지막을 형성하는 공정, 상기 콘택홀내의 상기 확산방지막상에 콘택플러그를 형성하는 공정, 상기 콘택플러그 및 이에 연장된 상기 층간절연막상에 배선층을 형성하는 공정을 포함함을 특징으로 한다.In order to achieve the above object, a method of forming a wiring of a semiconductor device according to the present invention may include forming an interlayer insulating film having contact holes on a substrate, and forming a barrier metal layer on the contact hole and the interlayer insulating film. Forming a diffusion barrier to prevent diffusion of fluorine (F) atoms on the barrier metal layer including the contact hole, forming a contact plug on the diffusion barrier in the contact hole, the contact plug and the interlayer extending therefrom And forming a wiring layer on the insulating film.
첨부 도면을 참조하여 본 발명 반도체소자의 배선 형성방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a wiring forming method of the semiconductor device of the present invention will be described.
도 3a 내지 도 3d는 본 발명 제 1 실시예에 따른 반도체소자의 배선 형성방법을 나타낸 공정단면도 이고, 도 4a 내지 도 4d는 본 발명 제 2 실시예에 따른 반도체소자의 배선 형성방법을 나타낸 공정단면도 이다.3A through 3D are cross-sectional views illustrating a method of forming wirings of a semiconductor device in accordance with a first embodiment of the present invention. to be.
본 발명은 비아홀내에 텅스텐 플러그를 증착할 때 즉, 비아홀을 덮도록 두꺼운 두께를 갖도록 텅스텐을 증착할 때, 사용되는 WF6 가스의 F원자가 하부의 티타늄 나이트라이드막의 결정립계를 통하여 티타늄막(Ti)으로 반응하여서 비아홀 상부 에지에 볼케이노 결함(Volcano defect)이 발생하는 것을 방지하기 위해서 제 1 실시예로 비아홀을 포함한 티타늄 나이트라이드막에 얇은 두께를 갖는 텅스텐막을 1차로 형성해서 WF6가 티타늄 나이트라이드막과 반응해서 결함이 발생하는 현상을 막을 수 있고, 또는 제 2 실시예로 비아홀내에 텅스텐 플러그를 형성하기 전에 O2 플라즈마 처리를 하는 것이다.In the present invention, when depositing a tungsten plug in a via hole, that is, when depositing tungsten to have a thick thickness to cover the via hole, the F atom of the WF6 gas used reacts with the titanium film (Ti) through the grain boundary of the titanium nitride film below. In order to prevent Volcano defects from occurring at the upper edge of the via hole, a thin tungsten film is formed first in the titanium nitride film including the via hole in the first embodiment, and WF6 reacts with the titanium nitride film. The occurrence of defects can be prevented, or in the second embodiment, the O 2 plasma treatment is performed before forming the tungsten plug in the via hole.
먼저 본 발명 제 1 실시예에 따른 반도체소자의 배선 형성방법은 도 3a에 도시한 바와같이 실리콘기판(21)의 일영역상에 하부배선층(22)을 형성하고, 하부배선층(22)을 포함한 실리콘기판(21)상에 층간절연막(23)을 형성한다.First, in the method for forming a semiconductor device wiring according to the first embodiment of the present invention, as shown in FIG. 3A, the lower wiring layer 22 is formed on one region of the silicon substrate 21, and the silicon including the lower wiring layer 22 is formed. An interlayer insulating film 23 is formed on the substrate 21.
그리고 도 3b에 도시한 바와 같이 사진식각공정으로 층간절연막(23)을 이방성 식각해서 하부배선층(22)의 일부분이 드러나도록 비아홀을 형성한다.As shown in FIG. 3B, the interlayer insulating layer 23 is anisotropically etched by a photolithography process to form a via hole so that a portion of the lower wiring layer 22 is exposed.
이어서 비아홀을 포함한 층간절연막(23)상에 베리어 메탈층으로 제 1 티타늄막(24)과 티타늄 나이트라이드막(25)을 차례로 증착한다.Subsequently, the first titanium film 24 and the titanium nitride film 25 are sequentially deposited as a barrier metal layer on the interlayer insulating film 23 including the via holes.
그리고 도 3c에 도시한 바와 같이 물리적 기상 증착(Pysical Vapor Deposition:PVD)법으로 100~500Å의 얇은 두께를 갖도록 텅스텐막(26)을 증착한다.As shown in FIG. 3C, a tungsten film 26 is deposited to have a thin thickness of 100 to 500 kV by physical vapor deposition (PVD).
이때 얇은 두께의 텅스텐막(26)은 차후에 플러그 형성을 위한 텅스텐을 증착할 때 WF6의 소오스 가스중 F원자가 티타늄 나이트라이드막(25)의 결정립계를 통하여 제 1 티타늄막(24)으로 확산되어서 볼케이노 결함(Volcano defect)이 발생하는 것을 방지하는 확산방지막의 역할을 한다.At this time, the thin tungsten film 26 is a volcano defect due to the diffusion of F atoms in the source gas of WF6 into the first titanium film 24 through the grain boundary of the titanium nitride film 25 when depositing tungsten for plug formation. It acts as a diffusion barrier to prevent Volcano defects from occurring.
그리고 도 3d에 도시한 바와 같이 비아홀을 채우도록 전면에 화학기상증착(Chemical Vapor Deposition : CVD)법으로 텅스텐을 증착하고, 에치백이나 화학적 기계적 연마공정으로 층간절연막(23)이 드러나도록 텅스텐과 텅스텐막(26)과 티타늄 나이트라이드막(25)과 제 1 티타늄막(24)을 차례로 제거해서 비아홀 내에만 남게한다.As shown in FIG. 3D, tungsten is deposited on the front surface to fill the via hole by Chemical Vapor Deposition (CVD), and the tungsten and tungsten are exposed so that the interlayer dielectric layer 23 is exposed by an etch back or chemical mechanical polishing process. The film 26, the titanium nitride film 25, and the first titanium film 24 are sequentially removed to remain only in the via holes.
이에 의해서 텅스텐막(26)에 둘러싸인 비아홀내에 텅스텐 플러그(27)가 형성된다.As a result, a tungsten plug 27 is formed in the via hole surrounded by the tungsten film 26.
이후에 전면에 티타늄(Ti)과 알루미늄을 증착하고, 이방성 식각해서 바아홀내의 제 1 티타늄막(24)과 티타늄 나이트라이드막(25)과 텅스텐막(26)과 텅스텐플러그(27)와 접촉하며 비아홀에서 연장된 층간절연막(23)상에 제 2 티타늄막(28)을 형성하고, 제 2 티타늄막(28)상에 알루미늄 배선(29)을 형성한다.Thereafter, titanium (Ti) and aluminum are deposited on the entire surface and anisotropically etched to contact the first titanium film 24, the titanium nitride film 25, the tungsten film 26, and the tungsten plug 27 in the bar hole. The second titanium film 28 is formed on the interlayer insulating film 23 extending from the via hole, and the aluminum wiring 29 is formed on the second titanium film 28.
다음에 본 발명 제 2 실시예에 따른 반도체소자의 배선 형성방법은 도 4a에도시한 바와 같이 실리콘기판(31)의 일영역상에 하부배선층(32)을 형성하고, 하부배선층(32)을 포함한 실리콘기판(31)상에 층간절연막(33)을 형성한다.Next, in the method for forming a semiconductor device wiring according to the second embodiment of the present invention, as shown in FIG. 4A, the lower wiring layer 32 is formed on one region of the silicon substrate 31, and the lower wiring layer 32 is included. An interlayer insulating film 33 is formed on the silicon substrate 31.
그리고 도 4b에 도시한 바와 같이 사진식각공정으로 층간절연막(33)을 이방성 식각해서 하부배선층(32)의 일부분이 드러나도록 비아홀을 형성한다.As shown in FIG. 4B, the interlayer insulating layer 33 is anisotropically etched by a photolithography process to form a via hole so that a portion of the lower wiring layer 32 is exposed.
이어서 비아홀을 포함한 층간절연막(33)상에 베리어 메탈층으로 제 1 티타늄막(34)과 티타늄 나이트라이드막(35)을 차례로 증착한다.Subsequently, the first titanium film 34 and the titanium nitride film 35 are sequentially deposited on the interlayer insulating film 33 including the via hole as a barrier metal layer.
이후에 도 4c에 도시한 바와 같이 O2 플라즈마 처리하여 티타늄 나이트라이드막(35)의 표면을 더 밀집되게하는 TiON막(35a)으로 변환시켜서 차후에 플러그를 형성하기 위해 비아홀에 텅스텐을 증착할 때 소오스 가스인 WF6의 F원자가 하부의 티타늄 나이트라이드막(35)의 결정립계를 통하여 제 1 티타늄막(34)으로 확산되어 TiFx성분의 볼케이노 결함을 형성시키는 것을 방지한다. 즉, TiON막(35a)은 텅스텐 증착 소오스 가스 중 F원자가 제 1 티타늄막(34)으로 확산되어 결함을 일으키는 것을 방지하기 위한 확산방지막 역할을 한다.Subsequently, as shown in FIG. 4C, a source gas is used to convert the surface of the titanium nitride film 35 into a TiON film 35a which makes the surface of the titanium nitride film 35 more dense, thereby depositing tungsten in the via hole to form a plug. The F atoms of phosphorus WF6 are prevented from diffusing into the first titanium film 34 through the grain boundaries of the underlying titanium nitride film 35 to form a volcano defect of the TiFx component. That is, the TiON film 35a serves as a diffusion barrier for preventing the F atoms in the tungsten deposition source gas from diffusing into the first titanium film 34.
그리고 도 4d에 도시한 바와 같이 비아홀을 채우도록 전면에 화학기상증착(Chemical Vapor Deposition : CVD)법으로 텅스텐을 증착하고, 에치백이나 화학적 기계적 연마공정으로 층간절연막(33)이 드러나도록 텅스텐과 TiON막(35a)과 티타늄 나이트라이드막(35)과 제 1 티타늄막(34)을 차례로 제거해서 비아홀 내에만 남게한다.As shown in FIG. 4D, tungsten is deposited on the front surface to fill the via hole by Chemical Vapor Deposition (CVD), and the tungsten and TiON are exposed to the interlayer insulating layer 33 by etch back or chemical mechanical polishing. The film 35a, the titanium nitride film 35, and the first titanium film 34 are sequentially removed to remain only in the via hole.
이에 의해서 비아홀내에 텅스텐 플러그(36)가 형성된다.As a result, a tungsten plug 36 is formed in the via hole.
이후에 전면에 티타늄(Ti)과 알루미늄을 증착하고, 이방성 식각해서 바아홀내의 제 1 티타늄막(34)과 티타늄 나이트라이드막(35)과 TiON막(35a)과 텅스텐플러그(36)와 접촉하며 비아홀에서 연장된 층간절연막(33)상에 제 2 티타늄막(37)을 형성하고, 제 2 티타늄막(37)상에 알루미늄 배선(38)을 형성한다.Thereafter, titanium (Ti) and aluminum are deposited on the entire surface, and anisotropically etched to contact the first titanium film 34, the titanium nitride film 35, the TiON film 35a, and the tungsten plug 36 in the bar hole. A second titanium film 37 is formed on the interlayer insulating film 33 extending from the via hole, and the aluminum wiring 38 is formed on the second titanium film 37.
상기의 공정은 하부배선층과 상부의 알루미늄 배선(38) 사이의 비아홀내에 텅스텐 플러그를 형성하는 것 뿐만아니라, 소오스/드레인영역에 콘택 플러그를 형성한 후 비트라인과 같은 배선을 형성하는데도 적용이 가능하다.The above process is applicable not only to forming a tungsten plug in a via hole between the lower wiring layer and the upper aluminum wiring 38, but also to forming a contact such as a bit line after forming a contact plug in a source / drain region. .
상기와 같은 본 발명 반도체소자의 배선 형성방법은 다음과 같은 효과가 있다.The wiring forming method of the semiconductor device of the present invention as described above has the following effects.
비아홀내에 텅스텐플러그를 형성하기 전에 텅스텐 증착 소오스가스인 WF6의 F가 티타늄과 반응하지 못하도록 반응방지막을 형성하므로써, 비아홀 상부 에지에서 볼케이노 결함이 발생하는 것을 방지할 수있다.By forming a reaction prevention film to prevent the F of the tungsten vapor deposition source gas WF6 from reacting with titanium before forming the tungsten plug in the via hole, it is possible to prevent a volcano defect from occurring at the upper edge of the via hole.
이에 따라서 배선 특성의 저하를 막고 제조수율 및 동작 특성의 신뢰성을 확보할 수 있다.As a result, deterioration in wiring characteristics can be prevented, and the reliability of manufacturing yield and operating characteristics can be ensured.
Claims (7)
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| KR1020000086535A KR20020058430A (en) | 2000-12-30 | 2000-12-30 | Method for fabricating a wire in semiconductor device |
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| KR1020000086535A KR20020058430A (en) | 2000-12-30 | 2000-12-30 | Method for fabricating a wire in semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030056155A (en) * | 2001-12-27 | 2003-07-04 | 아남반도체 주식회사 | Fabrication method of semiconductor device |
| KR100761467B1 (en) * | 2006-06-28 | 2007-09-27 | 삼성전자주식회사 | Metal interconnection and method for forming the same |
| KR100770533B1 (en) * | 2006-08-30 | 2007-10-25 | 동부일렉트로닉스 주식회사 | Semiconductor device and method for manufacturing the semiconductor device |
-
2000
- 2000-12-30 KR KR1020000086535A patent/KR20020058430A/en not_active Application Discontinuation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030056155A (en) * | 2001-12-27 | 2003-07-04 | 아남반도체 주식회사 | Fabrication method of semiconductor device |
| KR100761467B1 (en) * | 2006-06-28 | 2007-09-27 | 삼성전자주식회사 | Metal interconnection and method for forming the same |
| US8124524B2 (en) | 2006-06-28 | 2012-02-28 | Samsung Electronics Co., Ltd. | Methods of forming metal interconnection structures |
| KR100770533B1 (en) * | 2006-08-30 | 2007-10-25 | 동부일렉트로닉스 주식회사 | Semiconductor device and method for manufacturing the semiconductor device |
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