KR20030056155A - Fabrication method of semiconductor device - Google Patents

Fabrication method of semiconductor device Download PDF

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KR20030056155A
KR20030056155A KR1020010086322A KR20010086322A KR20030056155A KR 20030056155 A KR20030056155 A KR 20030056155A KR 1020010086322 A KR1020010086322 A KR 1020010086322A KR 20010086322 A KR20010086322 A KR 20010086322A KR 20030056155 A KR20030056155 A KR 20030056155A
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fluorine
wafer
oxide layer
oxide film
semiconductor device
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KR1020010086322A
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Korean (ko)
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조경수
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아남반도체 주식회사
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Publication of KR20030056155A publication Critical patent/KR20030056155A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
    • H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02131—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of preventing the delamination of a metal line by using a fluorine anti-diffusing layer. CONSTITUTION: An oxide layer(4) containing fluorine is formed at the upper portion of a semiconductor structure, wherein the semiconductor structure includes a lower metal line(3). A fluorine anti-diffusing layer made of the first, second, and third anti-diffusing layer(5,6,7) is formed on the oxide layer under predetermined condition. After depositing an upper oxide layer(8) on the entire surface of the resultant structure, a planarization is carried out on the resultant structure. A via hole is then formed by selectively etching the upper oxide layer, fluorine anti-diffusing layer, the oxide layer for exposing the lower metal line.

Description

반도체 소자 제조 방법 {Fabrication method of semiconductor device}Fabrication method of semiconductor device

본 발명은 반도체 소자 제조 방법에 관한 것으로, 더욱 상세하게는 금속 배선층 상부에 불소 함유 산화막을 사용하여 절연체층을 형성하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of forming an insulator layer by using a fluorine-containing oxide film on a metal wiring layer.

반도체 소자가 점차 고집적화, 다층화됨에 따라 중요한 기술의 하나로 다층 배선 기술이 등장하게 되었는데, 이와 같은 다층 배선 기술은 금속 배선층과 절연막층을 회로 소자가 형성된 반도체 기판 상부에 교대로 형성하며, 절연막에 의해 분리된 금속 배선층 사이를 비아를 통해 전기적으로 접속함으로써 회로 동작이 이루어지도록 하는 것이다.As semiconductor devices have been increasingly integrated and multilayered, multilayer wiring technology has emerged as one of the important technologies. The multilayer wiring technology alternately forms a metal wiring layer and an insulating film layer on the semiconductor substrate on which the circuit elements are formed, and is separated by an insulating film. The circuit operation is performed by electrically connecting the interconnected metal wiring layers through vias.

최근 금속 배선층 상에 형성하는 절연체층으로서 낮은 유전상수를 갖는 불소 함유 산화막을 선호하고 있다. 그러나, 불소 함유 산화막에서는 불소가 상부로 이동하여 금속과 산화막 사이의 계면에 축적됨으로써 열공정 진행시 금속배선을 들뜨게 하는 현상인 디라미네이션(delamination)을 유발하는 문제점이 있었다.Recently, a fluorine-containing oxide film having a low dielectric constant is preferred as an insulator layer formed on a metal wiring layer. However, in the fluorine-containing oxide film, fluorine moves upwards and accumulates at the interface between the metal and the oxide film, thereby causing delamination, which is a phenomenon of lifting metal wiring during the thermal process.

본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 금속 배선이 들뜨는 현상인 디라미네이션을 방지하는 데 있다.The present invention has been made to solve the above problems, and an object thereof is to prevent delamination, which is a phenomenon in which metal wiring is lifted up.

도 1은 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.1 is a cross-sectional view showing a semiconductor device manufacturing method according to the present invention.

상기한 바와 같은 목적을 달성하기 위하여, 본 발명에 따른 반도체 소자 제조 방법은, 하부 금속 배선을 포함한 반도체 구조물 상부에 불소 함유 산화막을 형성하는 단계; 불소 함유 산화막이 형성된 웨이퍼를 수소, 산소 및 질소 분위기 중의 어느 한 분위기의 플라즈마 상태에 노출시켜 불소 확산 방지막을 형성하는 단계; 불소 확산 방지막 상부에 상부 산화막을 증착하고 평탄화하는 단계; 상부 산화막과 불소 확산 방지막, 불소 함유 산화막을 선택적으로 식각하여 하부 금속 배선의 일부가 드러나도록 비아를 형성하는 단계를 포함하여 이루어진다.In order to achieve the above object, the semiconductor device manufacturing method according to the present invention comprises the steps of: forming a fluorine-containing oxide film on top of the semiconductor structure including the lower metal wiring; Exposing the wafer on which the fluorine-containing oxide film is formed to a plasma state of one of hydrogen, oxygen, and nitrogen atmospheres to form a fluorine diffusion prevention film; Depositing and planarizing an upper oxide layer on the fluorine diffusion barrier layer; And selectively etching the upper oxide film, the fluorine diffusion prevention film, and the fluorine-containing oxide film to form a via to expose a portion of the lower metal wiring.

이 때, 수소, 산소 및 질소 분위기 중 둘 이상의 플라즈마 상태에 웨이퍼를 각각 노출시켜 불소 확산 방지막을 두 층 또는 세 층으로 형성할 수도 있다.In this case, the fluorine diffusion barrier may be formed in two or three layers by exposing the wafer to two or more plasma states of hydrogen, oxygen, and nitrogen atmospheres, respectively.

또한, 플라즈마 상태에 웨이퍼를 노출시킬 때에는, 웨이퍼의 온도를 500℃ 이내로 하고 10 분 이내의 시간 동안 노출시키는 것이 바람직하다.In addition, when exposing a wafer to a plasma state, it is preferable to make the temperature of a wafer within 500 degreeC, and to expose for 10 minutes or less.

그리고, 불소 확산 방지막을 형성한 후에는 열처리하는 것이 바람직하며, 그 열처리는 500℃ 미만의 온도로 하며, 일반 열처리 장치에서는 1시간 이내의 시간 동안, 퍼니스에서는 6시간 이내의 시간 동안 하는 것이 바람직하다.After the formation of the fluorine diffusion prevention film, heat treatment is preferably performed. The heat treatment is preferably performed at a temperature of less than 500 ° C., for a time of less than 1 hour in a general heat treatment apparatus, and for a time of less than 6 hours in a furnace. .

이하, 본 발명에 따른 반도체 소자 제조 방법에 대해 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail.

본 발명에서는 불소 함유 산화막으로부터 불소가 상부로 이동하여 금속과 산화막의 계면에 축적되는 것을 방지하기 위해, 웨이퍼를 수소, 산소 및 질소 분위기의 플라즈마 상태에 노출시켜 불소 함유 산화막의 상부에 불소 확산 방지막을 형성하며, 이로써 불소의 이동을 억제한다.In the present invention, in order to prevent fluorine from moving upward from the fluorine-containing oxide film and accumulating at the interface between the metal and the oxide film, the wafer is exposed to a plasma state in a hydrogen, oxygen, and nitrogen atmosphere to provide a fluorine diffusion prevention film on the fluorine-containing oxide film. It suppresses the movement of fluorine.

이하, 실시예를 통해 본 발명을 더욱 상세히 설명한다.Hereinafter, the present invention will be described in more detail with reference to Examples.

도 1은 본 발명에 따라 제조된 반도체 소자를 도시한 단면도이다.1 is a cross-sectional view showing a semiconductor device manufactured according to the present invention.

먼저, 도 1에 도시된 바와 같이, 반도체 기판(1)의 구조물(미도시), 즉 개별 소자가 형성된 반도체 기판 또는 하부 금속 배선층 상부에 산화막 등으로 이루어진 하부절연막(2)을 형성하고, 하부절연막(2) 상에 금속배선막을 형성하고 패터닝하여 하부 금속 배선(3)을 형성한다.First, as shown in FIG. 1, a lower insulating film 2 made of an oxide film or the like is formed on a structure (not shown) of the semiconductor substrate 1, that is, on a semiconductor substrate or a lower metal wiring layer on which individual elements are formed, and then a lower insulating film. A metal wiring film is formed and patterned on (2) to form the lower metal wiring 3.

다음, 하부 금속 배선(3)을 포함한 상부 전면에 불소 함유 산화막(4)을 증착한다.Next, a fluorine-containing oxide film 4 is deposited on the entire upper surface including the lower metal wiring 3.

다음, 불소 함유 산화막(4)이 형성된 웨이퍼를 수소 분위기의 플라즈마 상태에 노출시켜 불소 함유 산화막(4) 상부에 SiOF-H 구조의 제1 불소 확산 방지막(5)을 형성한다.Next, the wafer on which the fluorine-containing oxide film 4 is formed is exposed to a plasma state in a hydrogen atmosphere to form a first fluorine diffusion prevention film 5 of SiOF-H structure on the fluorine-containing oxide film 4.

다음, 웨이퍼를 산소 분위기의 플라즈마 상태에 노출시켜 제1 불소 확산 방지막(5) 상부에 SiOx 구조의 제2 불소 확산 방지막(6)을 형성한 후, 질소 분위기의 플라즈마 상태에 노출시켜 제2 불소 확산 방지막(6) 상부에 SiOxNy 구조의 제3 불소 확산 방지막(7)을 형성한다.Next, the wafer is exposed to a plasma state in an oxygen atmosphere to form a second fluorine diffusion barrier 6 having an SiOx structure on the first fluorine diffusion barrier 5, and then exposed to a plasma state in a nitrogen atmosphere to diffuse the second fluorine. A third fluorine diffusion barrier 7 having a SiO x N y structure is formed on the barrier 6.

상기한 바와 같이, 본 발명의 실시예에서는 수소, 산소 및 질소 분위기의 플라즈마 상태 각각에 웨이퍼를 노출시켜 불소 확산 방지막을 세 층으로 형성하였지만, 이에 한정될 필요는 없으며, 수소, 산소 및 질소 중의 하나 이상의 분위기 플라즈마 상태에 노출시켜 불소 확산 방지막을 한 층 또는 두 층으로 형성할 수도 있다.As described above, in the exemplary embodiment of the present invention, the fluorine diffusion barrier is formed in three layers by exposing the wafer to plasma states of hydrogen, oxygen, and nitrogen atmospheres, but the present invention is not limited thereto. The fluorine diffusion barrier film may be formed in one or two layers by exposure to the above atmospheric plasma state.

플라즈마 상태에 웨이퍼를 노출할 때에는, 웨이퍼의 온도를 500℃ 이내로 하고 10 분 이내의 시간 동안 노출시키는 것이 바람직하다.When exposing the wafer to a plasma state, it is preferable to keep the temperature of the wafer within 500 ° C. and expose it for a time within 10 minutes.

또한, 플라즈마 상태에 웨이퍼를 노출시켜 불소 확산 방지막을 형성한 후에는 열처리할 수 있다. 열처리할 때에는 500℃ 미만의 온도에서 1시간 이내의 시간동안 하며, 열처리를 퍼니스 내에서 수행할 경우에는 6시간 이내의 시간동안 할 수도 있다Further, after the wafer is exposed to the plasma state to form the fluorine diffusion preventing film, heat treatment may be performed. When the heat treatment is performed for less than 1 hour at a temperature of less than 500 ℃, if the heat treatment is carried out in the furnace may be for up to 6 hours.

다음, 제3 불소 확산 방지막(7) 상부에 일반적인 절연막으로 상부 산화막(8)을 형성하고 화학기계적 연마하여 상부 산화막(8)의 상면을 평탄화한다.Next, an upper oxide film 8 is formed on the third fluorine diffusion barrier 7 as a general insulating film and chemically mechanically polished to planarize the top surface of the upper oxide film 8.

이후에는, 통상적인 공정을 통해 평탄화된 상부 산화막(8)의 상부에 형성된 상부 금속 배선(9)과 하부 금속 배선(3)을 비아(미도시)를 통해 연결한다.Thereafter, the upper metal wiring 9 and the lower metal wiring 3 formed on the planarized upper oxide film 8 are connected through vias (not shown) through a conventional process.

상술한 바와 같이, 본 발명에서는 금속 배선 상에 불소 함유 산화막을 형성할 때 불소 함유 산화막이 형성된 웨이퍼를 수소, 산소 및 질소 분위기의 플라즈마에 노출시켜 불소 확산 방지막을 형성함으로써, 불소가 상부 구조로 이동하는 것을 억제하여 금속 배선의 들뜸현상인 디라미네이션을 방지하는 효과가 있다.As described above, in the present invention, when the fluorine-containing oxide film is formed on the metal wiring, the wafer on which the fluorine-containing oxide film is formed is exposed to plasma in hydrogen, oxygen, and nitrogen atmospheres to form a fluorine diffusion prevention film, whereby fluorine moves to the upper structure. It is effective to prevent the delamination, which is a phenomenon of lifting of the metal wiring, by suppressing it.

따라서, 디라미네이션에 기인한 소자의 불량발생률 감소를 방지하여 수율을 향상시키는 효과가 있다.Therefore, there is an effect of improving the yield by preventing the reduction of the defective rate of the device due to the delamination.

Claims (5)

하부 금속 배선을 포함한 반도체 구조물 상부에 불소 함유 산화막을 형성하는 단계;Forming a fluorine-containing oxide film on the semiconductor structure including the lower metal wirings; 상기 불소 함유 산화막이 형성된 웨이퍼를 수소, 산소 및 질소 분위기 중의 어느 한 분위기의 플라즈마 상태에 노출시켜 불소 확산 방지막을 형성하는 단계;Exposing the wafer on which the fluorine-containing oxide film is formed to a plasma state of any one of hydrogen, oxygen, and nitrogen atmospheres to form a fluorine diffusion prevention film; 상기 불소 확산 방지막 상부에 상부 산화막을 증착하고 평탄화하는 단계;Depositing and planarizing an upper oxide layer on the fluorine diffusion barrier layer; 상기 상부 산화막과 불소 확산 방지막, 불소 함유 산화막을 선택적으로 식각하여 상기 하부 금속 배선의 일부가 드러나도록 비아를 형성하는 단계를 포함하는 반도체 소자 제조 방법.And selectively etching the upper oxide layer, the fluorine diffusion barrier layer, and the fluorine-containing oxide layer to form vias to expose a portion of the lower metal interconnection. 제 1 항에 있어서, 상기 수소, 산소 및 질소 분위기 중 둘 이상의 플라즈마 상태에 상기 웨이퍼를 각각 노출시켜 상기 불소 확산 방지막을 두 층 또는 세 층으로 형성하는 반도체 소자 제조 방법.The method of claim 1, wherein the wafer is exposed to two or more plasma states of hydrogen, oxygen, and nitrogen to form the fluorine diffusion barrier in two or three layers. 제 1 항 또는 제 2 항에 있어서, 상기 플라즈마 상태에 상기 웨이퍼를 노출시킬 때에는, 상기 웨이퍼의 온도를 500℃ 이내로 하고 10 분 이내의 시간 동안 노출시키는 반도체 소자 제조 방법.The semiconductor device manufacturing method according to claim 1 or 2, wherein when exposing the wafer to the plasma state, the temperature of the wafer is set to within 500 ° C and exposed for a time of less than 10 minutes. 제 1 항 또는 제 2 항에 있어서, 상기 불소 확산 방지막을 형성한 후에 열처리하는 반도체 소자 제조 방법.The semiconductor device manufacturing method according to claim 1 or 2, wherein the heat treatment is performed after the fluorine diffusion prevention film is formed. 제 1 항에 있어서, 상기 열처리는 500℃ 미만의 온도로 하며, 일반 열처리 장치에서는 1시간 이내의 시간 동안, 퍼니스에서는 6시간 이내의 시간 동안 하는 것을 특징으로 하는 반도체 소자 제조 방법.The method of claim 1, wherein the heat treatment is performed at a temperature of less than 500 ° C., for a time of less than 1 hour in a general heat treatment apparatus, and for a time of less than 6 hours in a furnace.
KR1020010086322A 2001-12-27 2001-12-27 Fabrication method of semiconductor device KR20030056155A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1056009A (en) * 1996-06-03 1998-02-24 Nec Corp Semiconductor device and manufacture thereof
JP2000012539A (en) * 1998-06-17 2000-01-14 Nec Corp Manufacture of semiconductor device
KR20000002928A (en) * 1998-06-24 2000-01-15 윤종용 Metal wiring structure of semiconductor device and production method thereof
KR20020058430A (en) * 2000-12-30 2002-07-12 박종섭 Method for fabricating a wire in semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1056009A (en) * 1996-06-03 1998-02-24 Nec Corp Semiconductor device and manufacture thereof
JP2000012539A (en) * 1998-06-17 2000-01-14 Nec Corp Manufacture of semiconductor device
KR20000002928A (en) * 1998-06-24 2000-01-15 윤종용 Metal wiring structure of semiconductor device and production method thereof
KR20020058430A (en) * 2000-12-30 2002-07-12 박종섭 Method for fabricating a wire in semiconductor device

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