KR100202199B1 - Planarization method of metal thin film of semiconductor device - Google Patents
Planarization method of metal thin film of semiconductor device Download PDFInfo
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- KR100202199B1 KR100202199B1 KR1019910019799A KR910019799A KR100202199B1 KR 100202199 B1 KR100202199 B1 KR 100202199B1 KR 1019910019799 A KR1019910019799 A KR 1019910019799A KR 910019799 A KR910019799 A KR 910019799A KR 100202199 B1 KR100202199 B1 KR 100202199B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
Abstract
본 발명은 반도체 소자의 금속박막 평탄화 방법에 관한 것으로, 콘택홈 또는 비아홈에서 금속박막의 스탭커버리지를 향상시키기 위하여, 콘택홈 또는 비아홈 상부에 금속박막을 형성한다음, 마스크 패턴 공정으로 금속박막 패턴을 형성하는 단계와, 상기 금속박막의 표면이 대기중에 노출됨에 따라 형성되는 금속 산화막을 제거한다음, 동일 장치내에서 예정된 높은 온도에서 열처리하여 금속박막의 상부면을 플로우(Flow)시켜 금속박막의 단자를 완화시키는 단계로 이루어지는 기술이다.The present invention relates to a method of planarizing a metal thin film of a semiconductor device, in order to improve the step coverage of the metal thin film in the contact grooves or via grooves, to form a metal thin film on the contact grooves or via grooves, the metal thin film by a mask pattern process Forming a pattern, removing the metal oxide film formed as the surface of the metal thin film is exposed to the atmosphere, and then heat-treating the upper surface of the metal thin film by heat treatment at a predetermined high temperature in the same apparatus. It is a technique that consists of relaxing the terminal.
Description
제1도 내지 제5도는 본 발명에 의해 반도체 소자의 콘택홈에서 금속박막을 평탄화하는 단계를 도시한 단면도.1 to 5 are cross-sectional views illustrating the step of planarizing a metal thin film in a contact groove of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 도전층 2 : 절연층1: conductive layer 2: insulating layer
3 : 제 1 금속박막 4 : 제 2 금속박막3: first metal thin film 4: second metal thin film
5 : 제 3 금속박막 6 : 금속산화막5: third metal thin film 6: metal oxide film
10 : 콘택홈10: Contact Home
본 발명은 고집적 반도체 소자의 금속박막 평탄화 방법에 관한 것으로, 특히 콘택(contact)홈 또는 비아(Via)홈 부분에서 금속박막의 스탭커브리지를 향상시킬 수 있는 반도체 소자의 금속박막 평탄화 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of planarizing a metal thin film of a highly integrated semiconductor device, and more particularly, to a method of planarizing a metal thin film of a semiconductor device capable of improving a step bridge of a metal thin film in a contact groove or a via groove. .
반도체 소자 제조기술의 발달로 집적도가 증가함에 따라서 콘택홈과 비아홈 부분에서의 경사비(Aspect Ratio)가 증가하게 되며, 종래의 일반적인 스퍼터링(sputtering) 방법으로 금속박막 증착시는 콘택과 비아에서의 금속박막 예를들어 알루미늄 합금의 스탭커버리지가 나빠져서 소자의 신뢰성을 저하시킨다.As the degree of integration increases due to the development of semiconductor device manufacturing technology, the aspect ratio of the contact grooves and the via grooves increases, and in the case of depositing a metal thin film using a conventional general sputtering method, The step coverage of the metal thin film, for example, aluminum alloy, is deteriorated, which lowers the reliability of the device.
또한 알루미늄합금 증착시 저온에서 일정두께의 알루미늄합금 증착후 연속적으로 고온에서 나머지 두께만큼을 증착하는 2단계(Two-Step) 방법이나, 저온에서 원하는 만큼의 두께를 증착하고 연속적으로 고온에서 열처리하는 방법을 사용하는 경우는 콘택과 비아부분에서 알루미늄 합금의 평탄화가 가능하나 알루미늄합금 박막의 표면이 거칠어져서 노광(Photo-masking) 작업시 금속배선의 정확한 패턴 형성(Patterning)을 어렵게하는 단점이 있다.In addition, the two-step method of depositing the remaining thickness at a high temperature continuously after the deposition of a certain thickness of the aluminum alloy at low temperature during the deposition of aluminum alloy, or the method of depositing the desired thickness at low temperature and continuously heat treatment at high temperature In the case of using, the aluminum alloy can be planarized in the contacts and vias, but the surface of the aluminum alloy thin film becomes rough, which makes it difficult to accurately pattern the metal wiring during photo-masking.
따라서 본 발명은 종래의 고온 스퍼터링 방법으로 알루미늄합금을 증착할 때 알루미늄 합금박막의 표면이 거칠어져서 노광(Photo-masking) 작업을 어렵게 하는 단점을 해결할 수 있는 반도체 소자의 금속박막 평탄화 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention provides a method of planarizing a metal thin film of a semiconductor device that can solve the disadvantage that the surface of the aluminum alloy film becomes rough when the aluminum alloy is deposited by a conventional high temperature sputtering method, thereby making photo-masking difficult. There is a purpose.
즉, 본 발명은 일반적으로 널리 쓰이고 있는 저온 스퍼터링 방법으로 금속박막을 증착하고 노광 및 식각(Etch) 공정을 거쳐서 금속배선의 패턴형성(Patterning)을 완료한다. 이때 대기중의 산소와 반응하여 알루미늄합금 박막의 표면에는 금속산화막층이 성장한다. 알루미늄합금의 표면이 금속산화막층으로 형성된 경우는 고온에서 열처리를 하여도 알루미늄 합금의 확산(Diffusion) 효과를 기대하기가 어려우므로 스퍼터링 장치내에서 일차적으로 금속산화막을 제거한후, 대기중에 노출시키지 않은 상태에서 연속적으로 450℃ 이상의 고온에서 열처리를 하여 알루미늄 합금이 콘택홈 또는 비아홈 부분에서 플로우(Flow) 되도록 하여 금속박막의 스탭커버리지를 증가시킨다.That is, the present invention deposits a metal thin film by a low temperature sputtering method, which is widely used, and completes patterning of metal wiring through an exposure and etching process. At this time, the metal oxide layer grows on the surface of the aluminum alloy thin film in response to oxygen in the atmosphere. If the surface of the aluminum alloy is formed of a metal oxide layer, it is difficult to expect the diffusion effect of the aluminum alloy even after heat treatment at a high temperature, so that the metal oxide film is first removed in the sputtering apparatus and not exposed to the atmosphere. Heat treatment at a high temperature of more than 450 ℃ continuously in the aluminum alloy to flow (Flow) in the contact groove or via groove portion to increase the step coverage of the metal thin film.
본 발명에 의하면 콘택홈 또는 비아홈에서 금속박막의 스탭커버리지를 향상시키기 위하여, 콘택홈 또는 비아홈 상부에 금속박막을 형성한 다음, 마스크 패턴 공정으로 금속박막 패턴을 형성하는 단계와, 상기 금속박막의 표면이 대기중에 노출됨에 따라 형성되는 금속산화막을 제거한다음, 동일장치내에서 예정된 온도에서 열처리하여 금속박막의 상부면을 플로우(flow) 시켜 금속박막의 단차를 완화시키는 단계로 이루어지는 것을 특징으로 한다.According to the present invention, in order to improve the step coverage of the metal thin film in the contact groove or the via groove, forming a metal thin film on the contact groove or via groove, and then forming a metal thin film pattern by a mask pattern process, the metal thin film Removing the metal oxide film formed as the surface of the film is exposed to the atmosphere, and then heat-treating at a predetermined temperature in the same apparatus to flow the upper surface of the metal thin film to reduce the step of the metal thin film. .
이하, 첨부된 도면을 참고하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제1도 내지 제5도는 본 발명의 실시예에 의해 콘택에서 금속박막의 평탄화를 실시하는 단계를 도시한 단면도이다.1 to 5 are cross-sectional views illustrating the step of planarizing the metal thin film in the contact according to the embodiment of the present invention.
제1도는 실리콘 기판(도시안됨) 상부에 도전층(1)(또는 절연층) 상부에 절연층(2) 예를들어 산화막을 형성한 다음, 마스크 패턴 공정으로 절연층(2)의 예정된 부분을 제거하여 콘택홈(10) 또는 비아홈을 형성한 상태의 단면도이다.1 shows an insulating layer 2, for example, an oxide film formed on the conductive layer 1 (or an insulating layer) on a silicon substrate (not shown), and then a predetermined portion of the insulating layer 2 is removed by a mask pattern process. It is sectional drawing of the state which removed and formed the contact groove 10 or the via groove.
제2도는 상기 콘택홈(10)을 포함하는 전체구조 상부에 제 1 금속박막(3), 제 2 금속박막(4) 예를들어 알루미늄 합금 및 제 3 금속박막(5)을 순차적으로 적충한 상태의 단면도이다. 여기서 제 2 금속박막(4)은 콘택홈(10)의 측벽 및 저부에서 얇게 형성되지만 절연층(2) 상부면에는 두껍게 형성됨을 알수 있다.2 is a state in which the first metal thin film 3, the second metal thin film 4, for example, an aluminum alloy and the third metal thin film 5 are sequentially stacked on the entire structure including the contact groove 10. FIG. It is a cross section of. Here, the second metal thin film 4 is thinly formed on the sidewalls and the bottom of the contact groove 10, but it can be seen that the second metal thin film 4 is thickly formed on the upper surface of the insulating layer 2.
제3도는 마스크 패턴 공정으로 예정된 부분의 금속산화막(6), 제 3 금속박막(5), 제 2 금속박막(4) 및 제 1 금속박막(3)을 제거하여 금속박막 패턴을 형성한 상태의 단면도이다. 여기서 주지할 것은 제2도의 제 3 금속박막(5)을 형성한 후에 대기중에 제 3 금속박막(5)이 노출될 때 제 3 금속박막(5)과 대기중의 산소와 반응하여 표면에 금속산화막층(6)이 형성된다는 점이다.3 shows a metal thin film pattern formed by removing the metal oxide film 6, the third metal thin film 5, the second metal thin film 4, and the first metal thin film 3 of the portion scheduled by the mask pattern process. It is a cross section. Note that after forming the third metal thin film 5 of FIG. 2, when the third metal thin film 5 is exposed to the atmosphere, the metal oxide film reacts with the third metal thin film 5 and oxygen in the air. Layer 6 is formed.
제4도는 스퍼터링 장치내에서 금속산화막(6)과 제 3 금속박막(5)을 평면식각(Plana Etch)하여 제거한 상태의 단면도이다. 여기서 제 3 금속박막(5)이 형성되지 않을 경우에는 금속산화막(6)만 제거하면 된다.4 is a cross-sectional view of the metal oxide film 6 and the third metal thin film 5 in a sputtering apparatus removed by planar etching. When the third metal thin film 5 is not formed here, only the metal oxide film 6 needs to be removed.
제5도는 제4도의 동일 스퍼터링 장치내에서 연속적으로 450℃ 이상의 고온에서 열처리하여 제 2 금속박막(4)을 플로우시켜 콘택홈(10)상부에서 제 2 금속박막(4)의 단차를 완화시켜 스탭커버리지를 향상시킨 것을 도시한 단면도이다.5 is a second heat treatment at a high temperature of 450 ° C. or higher in the same sputtering apparatus of FIG. 4 to flow the second metal thin film 4 to relax the step of the second metal thin film 4 on the contact groove 10. It is sectional drawing which shows the improvement of coverage.
본 발명의 또다른 실시예로서 제 2 금속박막(4) 상, 하부에 제 3금속박막(5)과 제 1 금속박막(3)을 형성하는 방법 대신에 절연층(2) 상부에 제 2 금속박막(4)만 콘택홈(10) 상부에 형성할 수도 있다.As another embodiment of the present invention, instead of forming the third metal thin film 5 and the first metal thin film 3 on and under the second metal thin film 4, the second metal on the insulating layer 2. Only the thin film 4 may be formed on the contact groove 10.
또한, 제 3 금속박막(5)을 형성하지 않고 절연층(2) 상부에 제 1 금속박막(3)과 제 2 금속박막(4)만 형성하는 경우에도 본 발명을 적용할 수 있다.In addition, the present invention can be applied to the case where only the first metal thin film 3 and the second metal thin film 4 are formed on the insulating layer 2 without forming the third metal thin film 5.
상기한 본 발명의 기술을 이용하는 경우 콘택에서 금속박막(알루미늄 합금)의 스탭커버리지를 향상시킬 수 있고, 금속박막의 결정립 크기(Grain Size) 증가로 인하여 금속배선이 끊어지는 현상인 일렉트로마이그레이션(Electromigration)을 억제하여 소자의 신뢰성을 향상시킬 수 있다.In the case of using the technique of the present invention described above, it is possible to improve the step coverage of the metal thin film (aluminum alloy) in the contact, and the phenomenon of breaking the metal wiring due to the increase in grain size of the metal thin film (Electromigration) By suppressing this, the reliability of the device can be improved.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910019799A KR100202199B1 (en) | 1991-11-08 | 1991-11-08 | Planarization method of metal thin film of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019910019799A KR100202199B1 (en) | 1991-11-08 | 1991-11-08 | Planarization method of metal thin film of semiconductor device |
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| KR930011278A KR930011278A (en) | 1993-06-24 |
| KR100202199B1 true KR100202199B1 (en) | 1999-07-01 |
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| KR1019910019799A KR100202199B1 (en) | 1991-11-08 | 1991-11-08 | Planarization method of metal thin film of semiconductor device |
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