KR20040093565A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR20040093565A KR20040093565A KR1020030027481A KR20030027481A KR20040093565A KR 20040093565 A KR20040093565 A KR 20040093565A KR 1020030027481 A KR1020030027481 A KR 1020030027481A KR 20030027481 A KR20030027481 A KR 20030027481A KR 20040093565 A KR20040093565 A KR 20040093565A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 고집적화에 따른 구리배선들간의 신호지연(RC-delay) 및 신호간섭(Crosstalk) 현상을 방지하기 위한 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for preventing signal delay (RC-delay) and signal interference (Crosstalk) between the copper wirings due to high integration.
반도체 소자의 고집적화가 진행됨에 따라 금속배선들간의 간격도 점차 감소되고 있다. 그런데, 금속배선들간의 간격이 줄어들게 되면, 한 쌍의 금속배선과 그들 사이의 층간절연막이 마치 캐패시터처럼 작용하게 되고, 이로 인해, 금속배선에서의 신호지연(RC-Delay) 및 이웃하는 금속배선들간의 신호간섭(Crosstalk) 현상이 발생하게 된다.As the integration of semiconductor devices proceeds, the spacing between metal wirings is gradually decreasing. However, when the spacing between the metal wires is reduced, the pair of metal wires and the interlayer insulating film therebetween act as a capacitor, and thus, the signal delay (RC-Delay) and the adjacent metal wires in the metal wires are caused. Crosstalk phenomenon occurs.
여기서, 이러한 금속배선의 캐패시터화를 방지하기 위한 방법으로서는 금속배선의 자체 저항을 낮추거나, 층간절연막으로서 유전율이 낮은 물질을 적용하는 방법을 들 수 있다. 그런데, 전자의 방법은 금속배선의 두께를 증가시켜야 하기 때문에 금속막의 증착 공정과 이에 대한 식각 공정의 신뢰성을 확보할 수 없다는 또 다른 문제가 유발된다.Here, as a method for preventing the formation of such a metal wiring, a method of lowering the self resistance of the metal wiring or applying a material having a low dielectric constant as an interlayer insulating film may be used. However, since the former method has to increase the thickness of the metal wiring, another problem arises that the reliability of the metal film deposition process and the etching process thereof cannot be secured.
따라서, 고집적화에 따른 금속배선에서의 신호지연 및 신호간섭 현상의 방지하기 위한 최근의 기술은 후자의 방법, 즉, 유전율(ε)이 3.5∼4.4인 실리콘산화막 대신에 그 보다 상대적으로 낮은 유전율을 갖는 저유전율의 층간절연 물질을 적용하는 방향으로 진행되고 있다. 일 예로, 다공질 저유전율 절연막을 구리배선간 절연막으로 적용하는 집적 공정이 제안되었다.Therefore, the recent technique for preventing signal delay and signal interference in metal wiring due to high integration has a relatively low dielectric constant instead of the latter method, that is, silicon oxide film having a dielectric constant? Of 3.5 to 4.4. Progress is being made in applying low dielectric constant interlayer insulating materials. As an example, an integrated process has been proposed in which a porous low dielectric constant insulating film is used as an inter-copper wiring insulating film.
그러나, 상기 다공질 저유전율 절연막을 구리배선간 절연막으로 적용함에 있어서는 다음과 같은 문제점이 있다.However, there are the following problems in applying the porous low dielectric constant insulating film as an inter-copper wiring insulating film.
첫째, 상기 다공질 저유전율 절연막은 실리콘산화막에 비해 상대적으로 낮은 기계적 강도를 갖기 때문에 후속 CMP(Chemical Mechanical Polishing) 공정이나 패키징(packaging) 공정에서 배선 구조가 무너지는 현상이 발생되는 등의 배선 신뢰성에 문제를 안고 있다.First, since the porous low dielectric constant insulating film has a lower mechanical strength than the silicon oxide film, there is a problem in the wiring reliability such as the collapse of the wiring structure in a subsequent CMP (Chemical Mechanical Polishing) process or a packaging process. Is holding.
둘째, 상기 다공질 저유전율 절연막은 금속배선들간 절연막으로 통상 이용되는 실리콘산화막에 비해 열전도도가 1/4 정도 수준 이므로, 초고속 로직(logic) 소자의 동작중에 발생하는 열을 외부로 방출시키지 못하게 되며, 이로 인해, 배선 온도가 증가됨으로써 전자이동(electromigration)을 발생시키게 된다.Second, the porous low dielectric constant insulating film has a thermal conductivity of about 1/4 of the silicon oxide film commonly used as an insulating film between metal wires, and thus prevents heat from being generated during operation of the ultra-high speed logic device to the outside. As a result, the wiring temperature is increased, which causes electromigration.
결국, 종래에는 고집적화에 따른 구리배선에서의 신호지연 및 신호간섭 현상을 방지함에 그 어려움이 있다.As a result, in the related art, there is a difficulty in preventing signal delay and signal interference in copper wiring due to high integration.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 고집적화에 따른 구리배선에서의 신호지연 및 신호간섭 현상을 방지할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing signal delay and signal interference in copper wiring due to high integration.
또한, 본 발명은 구리배선에서의 신호지연 및 신호간섭 현상을 방지함으로써 배선 신뢰성은 물론 제조수율을 확보할 수 있는 반도체 소자의 제조방법을 제공함에 그 다른 목적이 있다.In addition, another object of the present invention is to provide a method of manufacturing a semiconductor device capable of ensuring wiring reliability as well as manufacturing yield by preventing signal delay and signal interference in copper wiring.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도.1A to 1D are cross-sectional views illustrating processes for manufacturing a semiconductor device in accordance with an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 : 반도체 기판 2 : 하지층1 semiconductor substrate 2 base layer
3 : 실리콘산화막 4a : 제1구리배선3: silicon oxide film 4a: first copper wiring
4b : 제2구리배선 5 : 감광막 패턴4b: second copper interconnection 5: photosensitive film pattern
6 : 홈 7 : 제1USG막6: groove 7: first USG film
8 : 제2USG막 9 : 캡핑막8: second USG film 9: capping film
AG : 에어 갭AG: Air Gap
상기와 같은 목적을 달성하기 위하여, 본 발명은, 소정의 하지층이 형성되고 상기 하지층을 덮도록 실리콘산화막이 형성된 반도체 기판을 제공하는 단계; 상기 실리콘산화막의 소정 부분에 제1폭을 가지면서 제1간격으로 이격 배치되는 수 개의 제1구리배선과 상기 제1폭 보다 작은 제2폭을 가지면서 제1간격 보다 작은 제2간격으로 이격 배치되는 수 개의 제2구리배선을 형성하는 단계; 상기 제1 및 제2구리배선들을 포함한 실리콘산화막 상에 신호지연 및 신호간섭에 취약한 지역인 제2구리배선들 및 그들 사이의 실리콘산화막을 노출시키는 감광막 패턴을 형성하는 단계; 상기 노출된 실리콘산화막 부분을 식각하는 단계; 상기 감광막 패턴을 제거하는 단계; 상기 제2구리배선들 사이에 에어 갭이 형성되도록 기판 결과물 상에 스텝 커버리지 특성이 불량한 PVD 방식으로 제1USG막을 증착하는 단계; 상기 제1USG막 상에 CVD 방식으로 제2USG막을 증착하는 단계; 및 상기 제2USG막 상에 캡핑막을 증착하는 단계를 포함하는 반도체 소자의 제조방법을 제공한다.In order to achieve the above object, the present invention provides a semiconductor substrate having a silicon oxide film formed so that a predetermined base layer is formed and covers the base layer; A plurality of first copper wires spaced at a first interval while having a first width in a predetermined portion of the silicon oxide film and spaced at a second interval smaller than a first interval with a second width smaller than the first width Forming a plurality of second copper wirings; Forming a photoresist pattern on the silicon oxide layer including the first and second copper interconnections to expose the second copper interconnections, which are vulnerable to signal delay and signal interference, and a silicon oxide layer therebetween; Etching the exposed portion of the silicon oxide film; Removing the photoresist pattern; Depositing a first USG film on a substrate resultant in a PVD method having poor step coverage characteristics such that an air gap is formed between the second copper interconnections; Depositing a second USG film on the first USG film by CVD; And depositing a capping film on the second USG film.
여기서, 상기 노출된 실리콘산화막 부분을 식각하는 단계는 구리배선에 대해 식각 선택비가 높은 반응 이온 식각(Reaction Ion Etching) 공정으로 수행한다.The etching of the exposed portion of the silicon oxide layer may be performed by a reaction ion etching process having a high etching selectivity with respect to the copper wiring.
상기 제1USG막의 증착은 스퍼터링(sputtering) 또는 전자 빔 기화(Electron Beam Evaporation) 공정으로 수행한다.The deposition of the first USG film is performed by sputtering or electron beam evaporation.
본 발명의 방법은 상기 제2USG막을 증착하는 단계 후, 그리고, 상기 캡핑막을 증착하는 단계 전, 상기 제2USG막의 표면을 CMP 공정으로 평탄화시키는 단계를 더 포함한다.The method further comprises planarizing the surface of the second USG film after the deposition of the second USG film and before the deposition of the capping film by a CMP process.
본 발명에 따르면, 신호지연 및 신호간섭에 취약한 지역의 실리콘산화막을 제거한 후, 이 지역의 구리배선들 사이에 에어 갭을 갖도록 절연막을 형성하고, 그리고나서, 캡핑막을 형성해 줌으로써, 배선 구조의 기계적 강도를 확보하면서 구리배선의 신호지연 및 신호간섭 현상을 효과적으로 줄일 수 있다.According to the present invention, after removing the silicon oxide film in a region vulnerable to signal delay and signal interference, an insulating film is formed to have an air gap between the copper wirings in this region, and then a capping film is formed, thereby providing mechanical strength of the wiring structure. It can effectively reduce signal delay and signal interference phenomenon of copper wiring.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도이다.1A to 1D are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 트랜지스터(도시안됨)를 포함한 소정의 하지층(2)이 형성되고, 이 하지층을 덮도록 층간절연막으로서 통상의 실리콘산화막(3)이 형성된 반도체 기판(1)을 마련한다. 그런다음, 공지의 다마신(damascene) 공정에 따라 상기 실리콘산화막(3)의 소정 부분에 수 개의 제1 및 제2구리배선(4a, 4b)을 형성한다.Referring to FIG. 1A, a predetermined base layer 2 including a transistor (not shown) is formed, and a semiconductor substrate 1 having a normal silicon oxide film 3 formed thereon as an interlayer insulating film is formed so as to cover the base layer. . Then, several first and second copper wirings 4a and 4b are formed in a predetermined portion of the silicon oxide film 3 according to a known damascene process.
여기서, 상기 제1구리배선들(4a)은 제1폭을 가지며, 제1간격으로 이격 배치된다. 상기 제2구리배선들(4b)은 제1폭 보다 작은 제2폭을 가지며, 제1간격 보다 작은 제2간격으로 이격 배치된다.Here, the first copper wirings 4a have a first width and are spaced apart from each other at first intervals. The second copper wirings 4b have a second width smaller than the first width and are spaced apart from the second interval smaller than the first interval.
도 1b를 참조하면, 제1 및 제2구리배선(4a, 4b)을 포함한 실리콘산화막(3) 상에 감광막을 도포한 후, 이를 노광 및 현상해서 소자 동작시에 신호지연 및 신호간섭에 취약한 지역, 즉, 배선 사이가 좁고 배선 길이가 긴 지역에 해당하는 제2구리배선 형성 지역을 노출시키는 감광막 패턴(5)을 형성한다.Referring to FIG. 1B, a photosensitive film is coated on the silicon oxide film 3 including the first and second copper wirings 4a and 4b, and then exposed and developed to a region vulnerable to signal delay and signal interference during device operation. That is, the photosensitive film pattern 5 which exposes the 2nd copper wiring formation area | region which corresponds to the area | region where a wiring is narrow and a long wiring length is formed.
그런다음, 상기 감광막 패턴(5)을 식각 마스크로 이용해서 노출된 제2구리배선들(4b) 사이의 실리콘산화막 부분을 식각하고, 이를 통해, 제2구리배선(4b)을 포함한 그들 사이의 하지층 부분을 노출시키는 홈(6)을 형성한다.Then, the silicon oxide film portion between the exposed second copper interconnections 4b is etched using the photoresist pattern 5 as an etch mask, and thus, the lower portion therebetween including the second copper interconnections 4b. A groove 6 is formed which exposes the layer part.
여기서, 상기 실리콘산화막(3)의 식각은 제2구리배선(4b)의 손상이 최대한 억제되도록 구리배선에 대해 식각 선택비(Etch selectivity)가 높은 반응 이온 식각(Reaction Ion Etching) 공정으로 수행함이 바람직하다.Here, the etching of the silicon oxide film 3 is preferably performed by a reaction ion etching process with high etching selectivity with respect to the copper wiring so that the damage of the second copper wiring 4b can be suppressed to the maximum. Do.
도 1c를 참조하면, 감광막 패턴을 제거한 상태에서, 기판 결과물 상에 스텝커버리지(step coverage) 특성이 불량한 PVD(Physical Vapor Deposition) 방식, 예컨데, 스퍼터링(sputtering) 또는 전자 빔 기화(Electron Beam Evaporation) 공정으로 제1USG막(7)을 증착한다. 이때, 상기 PVD 방식에 의한 제1USG막(7)은 스텝 커버리지 특성이 불량한 것과 관련해서 제2구리배선들(4b) 사이에서 에어 갭(Air Gap : AG)을 형성하게 된다. 그런다음, 상기 제2구리배선들(4b) 사이에 에어 갭(AG)을 갖도록 증착된 제1USG막(7) 상에 CVD(Chemical Vapor Deposition) 방식으로 제2USG막(8)을 증착한다.Referring to FIG. 1C, in a state in which a photoresist pattern is removed, a physical vapor deposition (PVD) method having poor step coverage characteristics on a substrate resultant, for example, a sputtering or electron beam evaporation process The first USG film 7 is deposited. At this time, the first USG film 7 according to the PVD method forms an air gap (AG) between the second copper wirings 4b in connection with poor step coverage characteristics. Then, a second USG film 8 is deposited on the first USG film 7 deposited to have an air gap AG between the second copper wirings 4b by a chemical vapor deposition (CVD) method.
여기서, 상기 에어 갭(AG)을 포함한 제1USG막(7)에서의 평균 유전율(Keff)은 다음의 식 1로 표현될 수 있다.Here, the average dielectric constant K eff of the first USG film 7 including the air gap AG may be expressed by Equation 1 below.
Keff= Kair× Aair+ Koxide×(1-Aair) ----------------------- (식 1)K eff = K air × A air + K oxide × (1-A air ) ----------------------- (Equation 1)
(Kair=1, Koxide≒4.0, Aair=에어 갭의 면적비)(K air = 1, K oxide ≒ 4.0, A air = area ratio of air gap)
따라서, 상기 에어 갭이 배선 단면적의 70%를 차지한다고 가정하면, 평균 유전율(Keff)은 하기와 같이 얻어진다.Therefore, assuming that the air gap occupies 70% of the wiring cross-sectional area, the average dielectric constant K eff is obtained as follows.
Keff= 1 × 0.7 + 4.0 × (1-0.7) = 1.9K eff = 1 × 0.7 + 4.0 × (1-0.7) = 1.9
도 1d를 참조하면, 제2USG막(8) 상에 질화막 또는 산화막으로 이루어진 캡핑막(9)을 증착하여 구리배선 구조를 완성한다. 여기서, 상기 캡핑막(9)은 제1 및 제2USG막(7, 8)을 포함한 전체 두께가 소망하는 층간절연막의 두께가 되도록 하는 두께로 증착한다. 보다 정확하게, 상기 제2USG막(8)은 후속에서 형성될 캡핑막(9)의 두께를 제외한 제1USG막(7)을 포함한 두께가 소망하는 층간절연막의 두께가 되도록 하는 두께로 증착한다.Referring to FIG. 1D, a capping film 9 made of a nitride film or an oxide film is deposited on the second USG film 8 to complete a copper wiring structure. Here, the capping film 9 is deposited to a thickness such that the overall thickness including the first and second USG films 7 and 8 becomes the thickness of the desired interlayer insulating film. More precisely, the second USG film 8 is deposited to a thickness such that the thickness including the first USG film 7 excluding the thickness of the capping film 9 to be subsequently formed becomes the thickness of the desired interlayer insulating film.
한편, 캡핑막(9)을 증착하기 전, 예컨데, 공지의 CMP(Chemical Mechanical Polishing) 공정을 이용해서 제2USG막(8)의 표면을 평탄화시킴이 바람직하다.On the other hand, before depositing the capping film 9, it is preferable to planarize the surface of the second USG film 8 using, for example, a known chemical mechanical polishing (CMP) process.
이후, 공지의 후속 공정을 진행하여 반도체 소자의 제조를 완성한다.Thereafter, known subsequent steps are carried out to complete the manufacture of the semiconductor device.
전술한 바와 같은 본 발명의 방법에 따르면, 신호지연 및 신호간섭에 취약한 지역에서의 구리배선들 사이에 에어 갭을 갖는 절연막을 형성해주기 때문에 상기 구리배선에서의 신호지연 및 신호간섭 현상을 최대한 줄일 수 있다.According to the method of the present invention as described above, by forming an insulating film having an air gap between the copper wiring in the area vulnerable to signal delay and signal interference, the signal delay and signal interference phenomenon in the copper wiring can be minimized. have.
또한, USG막의 형성 후에는 산화막 또는 질화막으로 이루어진 캡핑막을 형성해 주기 때문에 이러한 캡핑막에 의해 CMP 공정 및 패키징 공정에서 요구되는 기계적 강도를 확보할 수 있으며, 그래서, 구리배선 신뢰성을 확보할 수 있다.In addition, since the capping film made of the oxide film or the nitride film is formed after the formation of the USG film, the capping film can ensure the mechanical strength required in the CMP process and the packaging process, thereby ensuring the copper wiring reliability.
결국, 본 발명의 방법은 에어 갭의 형성 및 캡핑막의 형성을 통해 매우 용이하게 구리배선의 신뢰성을 확보할 수 있다.As a result, the method of the present invention can ensure the reliability of the copper wiring very easily through the formation of the air gap and the formation of the capping film.
이상에서와 같이, 본 발명은 신호지연 및 신호간섭에 취약한 지역, 즉, 배선 사이가 좁고 배선 길이가 긴 지역에 해당하는 제2구리배선 형성 지역의 실리콘산화막을 제거한 후에 제2구리배선들 사이에 에어 갭을 갖도록 PVD 방식으로 USG막을 형성하며, 또한, USG막 상에는 캡핑막을 형성해 줌으로써, 배선 구조의 기계적 강도를 확보하면서 구리배선의 신호지연 및 신호간섭 현상을 효과적으로 줄일 수 있으며, 그래서, 구리배선의 신뢰성 및 소자 제조수율을 향상시킬 수 있다.As described above, the present invention removes the silicon oxide film of the second copper wiring forming region corresponding to the region vulnerable to signal delay and signal interference, that is, the region between the wiring and the wiring length is long, and then between the second copper wiring. By forming a USG film by PVD method to have an air gap, and by forming a capping film on the USG film, it is possible to effectively reduce signal delay and signal interference phenomenon of copper wiring while securing mechanical strength of the wiring structure. Reliability and device manufacturing yield can be improved.
기타, 본 발명은 그 요지가 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100778867B1 (en) * | 2006-07-24 | 2007-11-22 | 동부일렉트로닉스 주식회사 | Manufacturing method of a semiconductor device with a low-k dielectric layer |
| KR20150073595A (en) * | 2013-12-23 | 2015-07-01 | 삼성전자주식회사 | Wiring structure in a semiconductor device and method for forming the same |
| WO2015112300A1 (en) * | 2014-01-27 | 2015-07-30 | Applied Materials, Inc. | Air gaps between copper lines |
| US9171781B2 (en) | 2013-02-13 | 2015-10-27 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of fabricating the same |
| WO2018125089A1 (en) * | 2016-12-28 | 2018-07-05 | Intel Corporation | Grating layer with variable pitch formed using directed self-assembly of multiblock copolymers |
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2003
- 2003-04-30 KR KR1020030027481A patent/KR20040093565A/en not_active Application Discontinuation
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100778867B1 (en) * | 2006-07-24 | 2007-11-22 | 동부일렉트로닉스 주식회사 | Manufacturing method of a semiconductor device with a low-k dielectric layer |
| US9171781B2 (en) | 2013-02-13 | 2015-10-27 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of fabricating the same |
| KR20150073595A (en) * | 2013-12-23 | 2015-07-01 | 삼성전자주식회사 | Wiring structure in a semiconductor device and method for forming the same |
| WO2015112300A1 (en) * | 2014-01-27 | 2015-07-30 | Applied Materials, Inc. | Air gaps between copper lines |
| US9396989B2 (en) | 2014-01-27 | 2016-07-19 | Applied Materials, Inc. | Air gaps between copper lines |
| WO2018125089A1 (en) * | 2016-12-28 | 2018-07-05 | Intel Corporation | Grating layer with variable pitch formed using directed self-assembly of multiblock copolymers |
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