KR20040053455A - Method for manufacturing inter metal dielectrics in semiconductor device - Google Patents
Method for manufacturing inter metal dielectrics in semiconductor device Download PDFInfo
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- KR20040053455A KR20040053455A KR1020020080009A KR20020080009A KR20040053455A KR 20040053455 A KR20040053455 A KR 20040053455A KR 1020020080009 A KR1020020080009 A KR 1020020080009A KR 20020080009 A KR20020080009 A KR 20020080009A KR 20040053455 A KR20040053455 A KR 20040053455A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 36
- 239000002184 metal Substances 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title description 3
- 239000003989 dielectric material Substances 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 17
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 13
- 239000010937 tungsten Substances 0.000 claims abstract description 13
- 238000005498 polishing Methods 0.000 claims abstract description 3
- 238000010438 heat treatment Methods 0.000 claims description 7
- 230000007547 defect Effects 0.000 abstract description 25
- 239000000126 substance Substances 0.000 abstract description 11
- 230000003321 amplification Effects 0.000 abstract description 3
- 239000011521 glass Substances 0.000 abstract description 3
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052739 hydrogen Inorganic materials 0.000 abstract description 2
- 239000001257 hydrogen Substances 0.000 abstract description 2
- 238000004151 rapid thermal annealing Methods 0.000 abstract 1
- 238000007517 polishing process Methods 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000003795 desorption Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 125000000962 organic group Chemical group 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02134—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/1435—Random access memory [RAM]
- H01L2924/1437—Static random-access memory [SRAM]
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Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 보다 구체적으로는 에스램(SRAM) 반도체 소자의 금속 배선 형성 시, IMD(Inter Metal Dielectrics)용 절연막에 발생되는 볼록이성 결함을 제거할 수 있는 반도체 소자의 IMD용 절연막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor device capable of removing convexity defects generated in an insulating film for inter metal dielectrics (IMD) when forming a metal wire of an SRAM semiconductor device. A method for forming an insulating film for an IMD is disclosed.
최근 금속 배선으로 텅스텐 금속막을 주로 사용하고 있다. 상기 텅스텐 금속막은 알루미늄막과 달리 미세 회로에서 정확하게 패터닝하는 것이 어렵기 때문에, 다마신(damascene) 공정을 주로 사용하며, 상기 다마신 공정을 진행하기 위해서는 후속으로 화학적 기계적 연마 공정이 수반된다.Recently, tungsten metal films are mainly used for metal wiring. Unlike the aluminum film, since the tungsten metal film is difficult to accurately pattern in a fine circuit, a damascene process is mainly used, and a chemical mechanical polishing process is subsequently performed to proceed with the damascene process.
도 1a 내지 도 1b는 종래 기술에 따른 반도체 소자의 IMD용 절연막 형성 방법을 설명하기 위한 공정단면도이다.1A to 1B are cross-sectional views illustrating a method of forming an insulating film for an IMD of a semiconductor device according to the prior art.
종래 기술에 따른 반도체 소자의 IMD용 절연막 형성 방법은, 도 1a에 도시된 바와 같이, 반도체기판(1) 상에 절연막(2)을 형성한 다음, 포토리쏘그라피 공정에 의해 상기 절연막(2)을 선택 식각하여 기판의 일부분을 노출시키는 각각의 콘택(3)을 형성한다. 이어, 상기 결과의 기판 전면에 텅스텐 금속막(4)을 형성한다.In the method for forming an insulating film for IMD of a semiconductor device according to the related art, as shown in FIG. 1A, an insulating film 2 is formed on a semiconductor substrate 1, and then the insulating film 2 is formed by a photolithography process. Selective etching forms each contact 3 that exposes a portion of the substrate. Next, a tungsten metal film 4 is formed on the entire surface of the resultant substrate.
그런 다음, 도 1b에 도시된 바와 같이, 상기 텅스텐 금속막에 화학적 기계적 연마 공정을 진행하여 각각의 콘택(3)을 매립시키는 다마신 구조의 금속 배선(4a)을 형성한다.Then, as shown in FIG. 1B, a chemical mechanical polishing process is performed on the tungsten metal film to form a metal wiring 4a having a damascene structure to fill each contact 3.
이 후, 도면에 도시되지 않았지만, 금속 배선을 포함한 기판 전면에 식각정지막으로서 실리콘 질화막을 형성한 다음, 상기 실리콘 질화막 위에 금속 배선과 후속의 상부 금속 배선 사이를 절연시키기 위한 IMD용 절연막을 형성한다. 이때, 상기 IMD용 절연막으로는 화학기상증착 공정(Chemical Vapor Deposition)에 의해 형성된 TEOS막, 실리콘 성분이 풍부한 옥사이드(Silicon Rich Oxide:SROx)막 또는USG(Undoped Silicon Glass)막이 사용된다.Thereafter, although not shown in the figure, a silicon nitride film is formed as an etch stop film on the entire surface of the substrate including the metal wiring, and then an insulating film for IMD is formed on the silicon nitride film to insulate between the metal wiring and the subsequent upper metal wiring. . In this case, a TEOS film formed by a chemical vapor deposition process, a silicon rich oxide (SROx) film, or a USG (Undoped Silicon Glass) film is used as the IMD insulating film.
도 2는 종래 기술의 문제점을 설명하기 위한 공정단면도이다.Figure 2 is a process cross-sectional view for explaining the problem of the prior art.
또한, 도 3 및 도 4는 미세 결함의 평면을 보인 SEM사진이고, 도 5 및 도 6은 화학적 기계적 연마 공정 진행 후에 금속 배선 표면에 발생된 미세 결함을 보인 SEM사진이다.3 and 4 are SEM photographs showing the plane of the micro defects, and FIGS. 5 and 6 are SEM photographs showing the micro defects generated on the surface of the metal wiring after the chemical mechanical polishing process.
한편, 도 7 및 도 8은 금속 배선 표면의 미세 결함들이 IMD용 절연막 형성 후 증폭된 볼록이성 결함의 평면도 및 단면도이다.7 and 8 are plan views and cross-sectional views of convexity defects in which fine defects on the surface of metal wirings are amplified after the insulation film for IMD is formed.
그러나, 종래의 기술에서는, 도 2에 도시된 바와 같이, 상기 텅스텐 금속막에 화학적 기계적 연마 공정을 진행함으로써, 금속 배선 및 절연막 위에 미세한 결함(5)이 발생된다.(도 3, 4, 5 및 6 참조) 이러한 미세 결함은 금속 배선에서는 페일(fail)을 유발하지는 않지만, 실리콘 질화막(6) 및 IMD용 절연막(7)에 의해 증폭된다.However, in the prior art, as shown in Fig. 2, by performing a chemical mechanical polishing process on the tungsten metal film, minute defects 5 are generated on the metal wiring and the insulating film. (Figs. 3, 4, 5 and 6) These fine defects do not cause a fail in the metal wiring, but are amplified by the silicon nitride film 6 and the insulating film 7 for the IMD.
한편, 상기 IMD용 절연막의 재질인 TEOS막, SROx막 또는 USG막은 화학기상증착 공정에 의해 형성되며, 상기 막들은 하부막에 존재하는 미세 결함을 더욱 크게 증폭시키는 경향이 있으며, 도 7 및 도 8에 도시된 바와 같이, 상기 증폭된 결함, 즉 볼록이성 결함(8)들은 후속의 상부 금속배선 형성 공정에서 브릿지(bridge)를 유발하여 소자의 페일(fail)이 발생되는 문제점이 있었다.Meanwhile, the TEOS film, the SROx film, or the USG film, which is a material of the IMD insulating film, is formed by a chemical vapor deposition process, and the films tend to further amplify the microscopic defects present in the lower film. FIGS. 7 and 8 As shown in FIG. 5, the amplified defects, that is, the convex heterogeneous defects 8, cause a bridge in a subsequent upper metallization forming process, causing a device to fail.
이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 화학적 기계적 연마 공정 후 발생된 미세 결함을 증폭시키지 않고 IMD용 절연막 표면을 평탄화시킬 수 있는 반도체 소자의 IMD용 절연막 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, and provides a method for forming an insulating film for IMD of a semiconductor device that can planarize the surface of the insulating film for IMD without amplifying the microscopic defects generated after the chemical mechanical polishing process. There is a purpose.
도 1a 내지 도 1b는 종래 기술에 따른 반도체 소자의 IMD용 절연막 형성 방법을 설명하기 위한 공정단면도.1A to 1B are cross-sectional views illustrating a method of forming an insulating film for an IMD of a semiconductor device according to the prior art;
도 2는 종래 기술의 문제점을 설명하기 위한 공정단면도.Figure 2 is a process cross-sectional view for explaining the problem of the prior art.
도 3 및 도 4는 미세 결함의 평면을 보인 SEM사진.3 and 4 are SEM pictures showing the plane of the microscopic defects.
도 5 및 도 6은 화학적 기계적 연마 공정 진행 후에 금속 배선 표면에 발생된 미세 결함을 보인 SEM사진.5 and 6 are SEM photographs showing the microscopic defects generated on the surface of the metal wiring after the chemical mechanical polishing process.
도 7 및 도 8은 금속 배선 표면의 미세 결함들이 IMD용 절연막 형성 후 증폭된 볼록이성 결함의 평면도 및 단면도.7 and 8 are plan and cross-sectional views of convexity defects in which fine defects on the surface of a metal wiring are amplified after formation of an insulating film for IMD.
도 9a 내지 도 9d는 본 발명에 따른 반도체 소자의 IMD용 절연막 형성 방법을 설명하기 위한 공정단면도이다.9A to 9D are cross-sectional views illustrating a method for forming an insulating film for an IMD of a semiconductor device according to the present invention.
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 IMD용 절연막 형성 방법은 반도체 기판 상에 기판의 일부분을 노출시키는 콘택을 가진 절연막을 형성하는 단계와, 절연막을 포함한 기판 전면에 텅스텐 금속막을 형성하는 단계와, 텅스텐 금속막을 화학적 기계적 연마하여 콘택을 매립시키는 금속 배선을 형성하는 단계와, 금속 배선을 포함한 기판 전면에 HSQ막을 형성하는 단계와, 결과물에 열처리를 실시하는 단계를 포함한 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method for forming an insulating film for IMD of a semiconductor device, the method including forming an insulating film having a contact exposing a portion of the substrate on a semiconductor substrate, and forming a tungsten metal film on the entire surface of the substrate including the insulating film. And forming a metal wiring to fill the contact by chemical mechanical polishing of the tungsten metal film, forming an HSQ film on the entire surface of the substrate including the metal wiring, and subjecting the resultant to heat treatment.
상기 HSQ막은 SOG방식으로 형성하는 것이 바람직하다.The HSQ film is preferably formed by SOG.
상기 열처리는 400℃ 이상의 온도에서 RTA 처리하거나, 퍼니스를 이용하여 300℃ 이상의 온도에서 진행하는 것이 바람직하다.The heat treatment is preferably RTA treatment at a temperature of 400 ℃ or more, or proceed at a temperature of 300 ℃ or more using a furnace.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 9a 내지 도 9d는 본 발명에 따른 반도체 소자의 IMD용 절연막 형성 방법을 설명하기 위한 공정단면도이다.9A to 9D are cross-sectional views illustrating a method for forming an insulating film for an IMD of a semiconductor device according to the present invention.
본 발명의 일실시예에 따른 반도체 소자의 IMD용 절연막 형성 방법은, 도 9a에 도시된 바와 같이, 반도체기판(10) 상에 옥사이드 계열의 절연막(11)을 형성한 다음, 포토리쏘그라피 공정에 의해 상기 절연막을 식각하여 기판의 일부분을 노출시키는 각각의 콘택(12)을 형성한다. 이어, 상기 콘택(12)을 포함한 기판 전면에스퍼터링(sputtering) 공정에 의해 텅스텐 금속막(13)을 형성한다.In the method for forming an insulating film for IMD of a semiconductor device according to an embodiment of the present invention, as shown in FIG. 9A, an oxide-based insulating film 11 is formed on a semiconductor substrate 10 and then subjected to a photolithography process. The insulating film is etched to form respective contacts 12 exposing a portion of the substrate. Subsequently, a tungsten metal film 13 is formed on the entire surface of the substrate including the contact 12 by a sputtering process.
그런 다음, 도 9b에 도시된 바와 같이, 상기 텅스텐 금속막에 화학적 기계적 연마 공정을 진행하여 각각의 콘택(12)을 매립시키는 금속 배선(13a)을 형성한다. 이때, 상기 화학적 기계적 연마 공정 진행 시, 금속 배선(13a) 및 절연막(11) 표면에는 미세 결함(14)이 발생된다.Then, as shown in FIG. 9B, a chemical mechanical polishing process is performed on the tungsten metal film to form metal wirings 13a for filling each contact 12. At this time, during the chemical mechanical polishing process, fine defects 14 are generated on the surfaces of the metal lines 13a and the insulating layer 11.
이 후, 도 9c에 도시된 바와 같이, 상기 미세 결함(14)을 포함한 기판 전면에 실리콘 질화막(15)을 형성한다. 이때, 상기 실리콘 질화막(15) 형성에 의해 상기 미세 결함(14)은 더욱 크게 증폭된다.Thereafter, as shown in FIG. 9C, the silicon nitride film 15 is formed on the entire surface of the substrate including the micro defect 14. At this time, the fine defect 14 is amplified even more by the formation of the silicon nitride film 15.
이어, 도 9d에 도시된 바와 같이, 상기 실리콘 질화막(15) 위에 IMD용 절연막(16)을 형성한다. 이때, 상기 IMD용 절연막(16)은 HSQ(Hydrogen SilsQuioxane)막을 사용하며, 상기 HSQ막은 SOG(Spin On Glass)방식으로 도포한다. 상기 SOG방식으로 도포된 HSQ막은 표면을 평탄하게 덮는 특성이 있다. 따라서, 본 발명에서는 이러한 특성을 가진 HSQ막을 이용하여 미세 결함(14)을 증폭시키지 않고 평탄하게 덮을 수 있다.Next, as shown in FIG. 9D, an insulating film for IMD 16 is formed on the silicon nitride film 15. In this case, the IMD insulating layer 16 uses a HSQ (Hydrogen SilsQuioxane) film, and the HSQ film is applied by a spin on glass (SOG) method. The HSQ film coated by the SOG method has a property of covering the surface evenly. Therefore, in the present invention, the HSQ film having such characteristics can be used to cover the microdefects 14 without amplification.
그런 다음, 상기 구조에 열처리(미도시)를 실시함으로서, 상기 HSQ막 내의 유기(organic)기의 분해 및 탈착을 유발시켜 표면을 더욱 평탄화한다. 이때, 상기 열처리는 400℃ 이상의 온도에서 RTA 처리하거나, 퍼니스(furnace)를 이용하여 300℃ 이상의 온도에서 진행한다.Then, heat treatment (not shown) is performed on the structure, thereby causing decomposition and desorption of organic groups in the HSQ film to further flatten the surface. At this time, the heat treatment is RTA treatment at a temperature of 400 ℃ or more, or proceed at a temperature of 300 ℃ or more using a furnace (furnace).
이 후, 도면에는 도시되지 않았지만, 포토리쏘그라피 공정에 의해 상기 IMD용 절연막 및 실리콘 질화막을 식각하여 금속 배선과 연결되는 상부 금속 배선을형성한다.Thereafter, although not shown in the drawing, the IMD insulating film and the silicon nitride film are etched by the photolithography process to form an upper metal wiring connected to the metal wiring.
본 발명에 따르면, 화학적 기계적 연마 공정에 의해 금속 배선 표면에 미세 결함이 발생된 경우, IMD용 절연막으로 스텝커버리지가 우수한 SOG방식의 HSQ막을 사용함으로써, 상기 미세 결함이 증폭되지 않고 표면을 평탄화할 수 있다.According to the present invention, when fine defects are generated on the surface of a metal wiring by a chemical mechanical polishing process, by using an SOG type HSQ film having excellent step coverage as an insulating film for IMD, the surface can be flattened without amplification of the fine defects. have.
이상에서와 같이, 본 발명은 IMD용 절연막으로 SOG방식의 HSQ막을 사용함으로써, 금속 배선 표면에 미세 결함이 발생되더라도 상기 미세 결함을 증폭시키지 않고 IMD 절연막 표면을 평탄화할 수 있다.As described above, the present invention can use the SOG type HSQ film as the insulating film for IMD, so that even if a small defect occurs on the surface of the metal wiring, the surface of the IMD insulating film can be flattened without amplifying the small defect.
따라서, 본 발명은 미세 결함을 증폭되지 않음에 따라, 후속의 상부 금속배선 형성 공정에서 브릿지 발생을 방지할 수 있으며, 신뢰성 있는 반도체 소자를 제조할 수 있다.Therefore, since the present invention does not amplify the fine defects, it is possible to prevent the occurrence of bridges in the subsequent upper metallization forming process, and to manufacture a reliable semiconductor device.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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