JPH09213796A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a dielectric constant making use of an organic insulating film by a method wherein an insulating film is embedded among a plurality of first metal wiring patterns formed with an inorganic insulating film and a second metal wiring pattern is embedded in a via hole reaching these first metal wiring patterns. SOLUTION: A plurality of Al films 12 are formed on a substrate 11, and a silicon oxide film 13 is formed on the Al film 12. The silicon oxide film 13 and the Al film 12 are selectively etched away, and a wiring pattern of a first wiring layer 18 is formed. The wiring pattern is coated with a silicon oxide film 14 on the entire face. Continuously, an insulating film 15 including organic compounds is formed so that the plurality of Al films 12 are embedded in the silicon oxide film 14. Further, the insulating film 15 is removed, a silicon oxide film 16 is formed on the entire face, and after embedding of a via hole is performed with a metal material, Al films 17 are deposited and a second wiring layer is formed. Accordingly, a dielectric constant can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a multi-layer wiring structure having a small wiring capacitance and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, an increase in signal delay due to miniaturization of semiconductor devices has been an obstacle in increasing the operating speed. In order to reduce the signal delay, it is essential to reduce the resistance of the wiring material and the dielectric constant of the interlayer insulating film. Among the above two items, regarding the reduction of the resistance of the wiring material, the adoption of a low resistance material such as Cu is considered,
Regarding the lowering of the dielectric constant of one interlayer insulating film, organic SOG is used.
Adoption of low-dielectric constant materials such as organic polymers is under consideration.

Conventionally, when a material containing an organic component such as organic SOG is used as an interlayer insulating film, an etch back method is used. As described above, the conventional method of manufacturing a semiconductor device using the etch back method is used. The process will be described with reference to FIG.

First, as shown in FIG. 2A, after forming a wiring pattern 22 on a substrate 21, a silicon oxide film 23 is formed by a plasma CVD method. Next, as shown in FIG. 2B, an organic SOG chemical solution is spin-coated on the silicon oxide film 23 and then cured by heat treatment to form an organic SO film.
The G film 24 is obtained. Further, as shown in FIG. 2C, after etching the organic SOG film 24 until the silicon oxide film 23 on the wiring pattern 22 is exposed, plasma CVD is performed.
A silicon oxide film 25 is formed by the method. Finally Figure 2
As shown in (D), after forming a via hole and filling the via hole with a metal material as necessary,
The second wiring pattern 26 is formed.

[0005]

However, in the conventional method, the organic SOG film on the wiring pattern is etched back in order to prevent via poisoning that occurs when the organic SOG film is exposed during the formation of via holes. Therefore, the above problems will be described below with reference to FIG. FIG. 3A shows a state in which the wiring pattern 32 is formed on the substrate 31, and the organic SOG film 33 is further formed on the substrate 31 on which the wiring pattern 32 is formed. After that, as shown in FIG.
The organic SOG film 3 on 2 is etched to form the via hole 3
4 is formed. However, when the organic SOG film 33 is etched, a product generated from the organic SOG film and adversely affecting the device adheres to the sidewall of the via hole. However, since the silicon oxide film formed by the CVD method or the like does not contain an organic component, the above-mentioned harmful substances are not generated.

Therefore, after forming the organic SOG film on the substrate on which the wiring pattern is formed as shown in FIG. 2 described above, etching is performed until the wiring pattern is once exposed, and silicon is further formed thereon by the CVD method. That is, it becomes necessary to form an oxide film.

However, as described above, the organic SOG
The film is once etched back and the silicon oxide film is CVD again.
When formed by the method, the organic SOG film is buried in a portion lower than the wiring, but a portion higher than the wiring becomes a silicon oxide film. In order to reduce the wiring capacitance, it is desirable to use an insulating material containing an organic component such as organic SOG having a dielectric constant lower than that of a silicon oxide film as much as possible within the range where via poison does not occur. An insulating material containing an organic component can be embedded only in a region lower than the wiring, which is an obstacle to reducing the wiring capacitance.

Therefore, the present invention provides a semiconductor device capable of reducing the dielectric constant by using an organic SOG film as much as possible within the range where via poison does not occur during etching for forming a via hole. It is intended to be provided.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems. In the interlayer insulating film for separating the first metal wiring pattern and the second metal wiring pattern on the first metal wiring pattern, the first metal is formed. By using an insulating material containing an organic component also in a region higher than the wiring of a wiring pattern, a semiconductor device having a small wiring capacitance and a method for manufacturing the same are provided.

Specifically, an inorganic insulating film (specifically, a silicon oxide film formed by a CVD method or the like) on the metal wiring layer.
And a step of forming a groove by etching a portion of the inorganic insulating film between the wiring patterns, and an insulating material containing an organic component in the groove (specifically, organic S
OG film) and a step of etching the inorganic insulating film on the wiring pattern to form a via hole, the semiconductor having no via poison and a wiring capacitance smaller than that in the case of using a conventional etchback method. A device can be formed.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor device and a method of manufacturing the same according to an embodiment of the present invention will be described below with reference to the drawings.

First, as shown in FIG. 1A, an Al film 12 having a film thickness of 800 nm, for example, is formed as a first wiring layer on a substrate 11 on which multi-layer wiring is formed, and the Al film 12 is further formed.
A silicon oxide film 13 having a film thickness of 1 μm, for example, is formed on the above by the plasma CVD method.

Next, as shown in FIG. 1B, the silicon oxide film 13 and the Al film 12 are selectively removed by etching using a normal lithography process and a dry etching process, and the wiring of the first wiring layer 18 is formed. Form a pattern. After the wiring pattern is formed, a silicon oxide film 14 (this silicon oxide film 14 is a typical dense film) is formed on the entire surface by plasma CVD to a thickness of about 50 nm to cover the entire surface. This is an organic SOG film (non-dense film)
It is formed in order to prevent the diffusion of the metal that is the material of the wiring pattern into the wiring.

Subsequently, as shown in FIG. 1C, organic SO
After spin coating the G chemical solution on the substrate at 3000 rpm for 20 sec, heat treatment is performed on a hot plate at 200 ° C. for 3 minutes, and further heat treatment is performed at 400 ° C. for 30 minutes in an electric furnace in a nitrogen atmosphere to form the organic SOG film 15. Form. As described above, the reason why the heat treatment is performed in two steps is that if the heat treatment is performed at a high temperature at one time, the organic SOG film contracts significantly.

Since the organic SOG film used here is for reducing the wiring capacitance, an organic polymer having a low dielectric constant may be used instead of the organic SOG. As the insulating material containing an organic component, for example, an organic SOG film containing methylsilsesquioxane as a main component (relative permittivity of about 3.0), a fluorine-based organic polymer (relative permittivity of about 2.2), etc. Is mentioned as a desirable one.

Further, as shown in FIG. 1D, the organic SOG film 1 on the silicon oxide film 13 is formed by the chemical mechanical polishing method.
After removing 5 and exposing the silicon oxide film 14, a silicon oxide film 16 is formed on the entire surface by plasma CVD.
It is formed to a thickness of about 0 nm.

Finally, as shown in FIG. 1E, after a via hole is formed by using a normal lithography process and a dry etching process, the resist mask used for patterning the via hole is ashed in oxygen plasma. To remove. Further, after filling the via hole with a metal material, an Al film 1 having a thickness of 800 nm is formed.
7 is deposited to form a second wiring layer.

As described above, according to the present invention, since the silicon oxide film is formed in advance in the region where the via hole is formed on the wiring, the via poison does not occur during the formation of the via hole. It is not necessary to etch the organic SOG film to be formed to the area where the wiring pattern is exposed. Therefore, it is possible to form the organic SOG film without forming the diagonally upper portion of the wiring pattern between the wiring patterns by the silicon oxide film formed by the CVD method or the like.

[0019]

According to the present invention, in the interlayer insulating film for separating the first metal wiring pattern and the second metal wiring pattern above it, not only the region lower than the wiring of the first metal wiring pattern, By using the organic insulating film 15 having a low dielectric constant even in a region higher than the wiring, the wiring capacitance can be reduced as compared with the semiconductor device formed by the conventional etchback. Moreover, since the wiring pattern is composed of only the silicon oxide films 13, 14 and 16 which are inorganic insulating materials, the organic insulating film 15 having a low dielectric constant is not exposed on the sidewall of the via hole when the via hole is formed. Therefore, there is no occurrence of via poison due to the ashing treatment in oxygen plasma.

Further, in the semiconductor device having the structure described in claim 2 of the present invention, the metal wiring has the silicon oxide films 13, 14,
It is covered with 16. Since the silicon oxide film covering the metal wiring serves as a skeleton that supports the metal wiring, even when an organic polymer having a low glass transition point is used as the organic insulating film 15, the metal wiring is less likely to be displaced due to the softening of the organic polymer. It is possible to suppress a decrease in yield when forming the multilayer wiring.

[Brief description of drawings]

FIG. 1 is a sectional view of a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor device manufacturing process using a conventional etchback method.

FIG. 3 is a sectional view of a conventional semiconductor device manufacturing process.

[Explanation of symbols]

 11 substrate 12 Al film 13 silicon oxide film 14 silicon oxide film 15 organic SOG film 16 silicon oxide film 17 Al film 21 substrate 22 wiring pattern 23 silicon oxide film 24 organic SOG film 25 silicon oxide film 26 wiring pattern 31 substrate 32 wiring pattern 33 Organic SOG film 34 via hole

Claims (3)

[Claims] 1. A plurality of first metal wiring patterns formed on a substrate, an inorganic insulating film formed to cover the first metal wiring patterns, and the inorganic insulating film are formed. A semiconductor having an insulating film containing an organic component embedded between a plurality of the first metal wiring patterns and a second metal wiring pattern embedded in a via hole reaching the first metal wiring pattern. apparatus. 2. The semiconductor device according to claim 1, wherein the first metal wiring pattern is covered with an inorganic insulating film. 3. A step of sequentially forming a first metal wiring layer and an inorganic insulating film on a substrate, and a step of selectively etching a portion of the inorganic insulating film other than a wiring pattern to form a groove portion. And a step of embedding an insulating material containing an organic component in the groove, and a step of etching the inorganic insulating film on the wiring pattern to form a via hole and then forming a second metal wiring pattern in the via hole. And a method for manufacturing a semiconductor device having the same.