KR100243284B1 - Method for forming contact hole of semiconductor device - Google Patents

Method for forming contact hole of semiconductor device Download PDF

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KR100243284B1
KR100243284B1 KR1019970006238A KR19970006238A KR100243284B1 KR 100243284 B1 KR100243284 B1 KR 100243284B1 KR 1019970006238 A KR1019970006238 A KR 1019970006238A KR 19970006238 A KR19970006238 A KR 19970006238A KR 100243284 B1 KR100243284 B1 KR 100243284B1
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forming
contact hole
insulating film
photoresist pattern
film
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KR19980069258A (en
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구주선
황병근
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윤종용
삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers

Abstract

반도체 기판상에 하부 금속 패턴을 형성하고, 상기 하부 금속 패턴상에 저유전 폴리머를 증착하여 층간 절연막을 형성하고, 상기 층간 절연막상에 캡핑 절연막을 형성하고, 상기 캡핑 절연막상에 포토레지스트 패턴을 형성하고, 상기 포토레지스트 패턴을 식각 마스크로 하고 상기 하부 금속 패턴을 식각 저지층으로 하여 상기 층간 절연막과 상기 제1 캡핑 절연막을 차례로 식각함으로써 콘택홀을 형성하고, 상기 포토레지스트 패턴 상에 상기 콘택홀의 측벽을 덮도록 연장되는 절연 물질의 보호막을 증착하고, 상기 보호막을 이방성 식각하여 상기 포토레지스트 패턴 상을 노출하고, 상기 콘택홀의 측벽을 이루는 상기 유기 폴리머를 차폐하여 보호하는 스페이서(spacer)를 형성한 후, 상기 포토레지스트 패턴을 제거하는 것을 특징으로 하는 반도체 장치의 콘택홀 형성 방법이 개시되며, 본 발명에 따르면 양호한 내측면 프로파일(profile)을 갖는 콘택홀을 얻을 수 있으므로 후속 공정에서 보이드(void)의 발생을 억제하여 신뢰성 높은 반도체 소자를 제조할 수 있다.A lower metal pattern is formed on the semiconductor substrate, a low dielectric polymer is deposited on the lower metal pattern to form an interlayer insulating film, a capping insulating film is formed on the interlayer insulating film, and a photoresist pattern is formed on the capping insulating film. And forming a contact hole by sequentially etching the interlayer insulating layer and the first capping insulating layer using the photoresist pattern as an etch mask and the lower metal pattern as an etch stop layer, and a sidewall of the contact hole is formed on the photoresist pattern. Depositing a protective film of an insulating material extending to cover anisotropically, anisotropically etching the protective film to expose the photoresist pattern, and forming a spacer to shield and protect the organic polymer forming a sidewall of the contact hole. And removing the photoresist pattern. And the forming method disclosed contact hole, it is possible according to the present invention can be obtained for the contact holes with a good inner surface of the profile (profile) to suppress the generation of voids (void) in a subsequent process to manufacture a highly reliable semiconductor device.

Description

반도체 장치의 콘택홀 형성 방법{Method for forming contact hole of semiconductor device}Method for forming contact hole of semiconductor device

본 발명은 반도체 장치의 콘택홀 형성 방법에 관한 것으로, 특히 균일한 내측면 프로파일을 갖는 반도체 장치의 콘택홀 형성 방법에 관한 것이다.The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly to a method for forming a contact hole in a semiconductor device having a uniform inner side profile.

최근에는, 고집적 반도체 소자 및 고속 반도체 소자에 적합한 공정 기술로서 다층 금속 배선 기술이 널리 사용되고 있다. 다층 금속 배선을 형성하는 경우에는 하지막의 평탄도가 좋아야 후속 공정을 원활히 진행할 수 있다. 만약, 하지막의 표면이 불균일하거나 표면 상태가 불량한 경우에는 그 상부에 적층되는 금속층에 균열이 발생되어 후속 공정에서 결함을 유발하게 된다. 따라서 다층 금속 배선 공정에는 상부 금속층을 적층하기 전에 하지막의 표면을 평탄화하는 것이 중요하며, 이를 위해서는 평탄도 특성이 우수한 물질로 층간 절연막을 형성할 필요가 있다.Recently, multilayer metal wiring technology has been widely used as a process technology suitable for highly integrated semiconductor devices and high-speed semiconductor devices. In the case of forming the multi-layered metal wiring, the flatness of the underlying film must be good so that the subsequent process can be performed smoothly. If the surface of the base film is uneven or the surface state is poor, cracks are generated in the metal layer stacked thereon, which causes defects in subsequent processes. Therefore, in the multilayer metal wiring process, it is important to planarize the surface of the underlying film before laminating the upper metal layer, and for this purpose, it is necessary to form an interlayer insulating film with a material having excellent flatness characteristics.

또, 고집적 반도체 장치에서는 금속 라인간의 간격이 좁아짐에 따라 기생 용량이 증대되고 이로 인해 신호 전달이 느려지거나 잡음이 발생하게 되므로, 이를 방지하기 위해서는 층간 절연막의 유전율이 낮아야 한다.In addition, in the highly integrated semiconductor device, as the spacing between metal lines is narrowed, parasitic capacitance is increased, resulting in slow signal transmission or noise. Therefore, in order to prevent this, the dielectric constant of the interlayer insulating film must be low.

현재, 이러한 특성을 갖는 물질로서 저유전 유기계 폴리머가 각광받고 있다. 저유전 유기계 폴리머는 우수한 평탄도 특성을 갖는 동시에 낮은 유전 상수를 가지므로, 후속 공정에서 보이드의 발생을 억제하고 금속 라인간의 기생 용량도 최소화 할 수 있다.Currently, low dielectric organic polymers are in the spotlight as materials having such characteristics. The low dielectric organic polymer has excellent flatness characteristics and a low dielectric constant, thereby suppressing generation of voids in subsequent processes and minimizing parasitic capacitance between metal lines.

그런데, 포토레지스트를 식각 마스크로 하여 층간 절연막을 식각하는 경우에는 포토레지트의 제거시에 층간 절연막의 구성 물질인 저유전 유기계 폴리머도 동시에 손상되는 문제가 있다. 즉, 포토레지스트 제거 공정은 대부분 플라즈마 산소 가스를 이용하여 수행되는데 이때, 저유전 유기계 폴리머는 플라즈마 산소 가스와 반응하여 이산화탄소(CO2) 가스를 발생하면서 손상된다.However, when the interlayer insulating film is etched by using the photoresist as an etching mask, the low dielectric organic polymer, which is a constituent material of the interlayer insulating film, is also damaged at the time of removing the photoresist. That is, the photoresist removal process is mostly performed using plasma oxygen gas, wherein the low dielectric organic polymer is damaged while generating carbon dioxide (CO 2 ) gas by reacting with the plasma oxygen gas.

도 1a 내지 도 1e는 종래의 콘택홀 형성 방법을 도시하는 단면도들이다.1A to 1E are cross-sectional views illustrating a conventional method for forming a contact hole.

도 1a는 반도체 기판(1)상에 하부 금속 패턴(2)과 제1 캡핑 절연막(3)이 형성된 결과를 도시한다.FIG. 1A illustrates a result of the lower metal pattern 2 and the first capping insulating layer 3 formed on the semiconductor substrate 1.

먼저, 반도체 기판(1)상에 하부 금속 패턴(2)을 형성한다. 다음에, 상기 결과물 전면에 실리콘 산화막으로 제1 캡핑 절연막(3)을 형성한다.First, the lower metal pattern 2 is formed on the semiconductor substrate 1. Next, a first capping insulating film 3 is formed on the entire surface of the resultant with a silicon oxide film.

도 1b는 층간 절연막(5)이 형성된 결과를 도시한다.1B shows the result of the formation of the interlayer insulating film 5.

상기 층간 절연막(5)은 플레어(flare) 또는 benzocyclobutene(이하, BCB라 함)과 같은 저유전 폴리머를 스핀 코팅(spin coating) 및 화학 기상 증착 방법 중 어느 하나의 방법을 이용하여 형성한다.The interlayer insulating film 5 is formed of a low dielectric polymer such as flare or benzocyclobutene (hereinafter referred to as BCB) using any one of spin coating and chemical vapor deposition.

도 1c는 상기 결과물상에 제2 캡핑 절연막(7)과 포토레지스트 패턴(9)을 형성한 결과를 도시한다.FIG. 1C illustrates a result of forming the second capping insulating layer 7 and the photoresist pattern 9 on the resultant product.

먼저, 층간 절연막(5) 전면에 실리콘 산화막으로 제2 캡핑 절연막(7)을 증착한다.이어서 상기 제2 층간 절연막(5) 전면에 포토레지스트를 도포하고 콘택홀이 형성될 위치만이 개구되도록 패터닝하여 포토레지스트 패턴(9)을 형성한다.First, a second capping insulating film 7 is deposited on the entire surface of the interlayer insulating film 5 with a silicon oxide film. Then, a photoresist is applied on the entire surface of the second interlayer insulating film 5 and patterned so that only a position where a contact hole is to be formed is opened. The photoresist pattern 9 is formed.

도 1d는 콘택홀(10)을 형성한 결과를 도시한다.1D illustrates a result of forming the contact hole 10.

상기 포토레지스트 패턴(9)을 식각 마스크로 하여 상기 제2 캡핑 절연막(7), 층간 절연막(5) 및 제1 캡핑 절연막(3)을 차례로 식각하여 상기 하부 금속 패턴(2)의 소정 영역을 노출시키는 콘택홀(10)을 형성한다. 이때, 상기 콘택홀의 내측면에는 저유전 폴리머로 이루어진 상기 층간 절연막(5)이 노출된다.The second capping insulating layer 7, the interlayer insulating layer 5, and the first capping insulating layer 3 are sequentially etched using the photoresist pattern 9 as an etching mask to expose a predetermined region of the lower metal pattern 2. Contact holes 10 are formed. In this case, the interlayer insulating layer 5 made of a low dielectric polymer is exposed on the inner surface of the contact hole.

도 1e는 포토레지스트 패턴(9)을 제거한 결과를 도시한다.1E shows the result of removing the photoresist pattern 9.

플라즈마 산소 가스를 이용하여 상기 포토레지스트 패턴(9)을 제거한다. 이때, 상기 콘택홀(10)의 내측면에 노출된 저유전 폴리머는 플라즈마 산소 가스와 반응하여 이산화탄소(CO2)를 생성하면서 손상된다. 이로 인해, 상기 콘택홀(10)의 내측면 프로파일은 불균일해지고 후속 공정에서 보이드가 발생되므로 반도체 장치의 신뢰성이 저하된다.The photoresist pattern 9 is removed using plasma oxygen gas. At this time, the low dielectric polymer exposed to the inner surface of the contact hole 10 is damaged while reacting with plasma oxygen gas to produce carbon dioxide (CO 2 ). As a result, the inner surface profile of the contact hole 10 becomes uneven and voids are generated in a subsequent process, thereby reducing the reliability of the semiconductor device.

본 발명의 기술적 과제는 균일한 내측면 프로파일을 갖는 반도체 장치의 콘택홀 형성 방법을 제공하는 것이다.An object of the present invention is to provide a method for forming a contact hole in a semiconductor device having a uniform inner side profile.

도 1a 내지 도 1e는 종래의 반도체 장치 콘택홀 형성 방법을 설명하기 위한 단면도들이다.1A to 1E are cross-sectional views illustrating a conventional method for forming a contact hole in a semiconductor device.

도 2a 내지 도 2g는 본 발명의 일 실시예에 따른 반도체 장치의 콘택홀 형성 방법을 설명하기 위한 단면도들이다.2A to 2G are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention.

본 발명의 기술적 과제를 달성하기 위해서 반도체 기판상에 하부 금속 패턴을 형성하고, 상기 하부 금속 패턴상에 저유전 폴리머를 증착하여 층간 절연막을 형성하고, 상기 층간 절연막상에 캡핑 절연막을 형성하고, 상기 캡핑 절연막상에 포토레지스트 패턴을 형성하고, 상기 포토레지스트 패턴을 식각 마스크로 하여 상기 층간 절연막과 상기 캡핑 절연막을 차례로 식각함으로써 콘택홀을 형성하고, 상기 포토레지스트 패턴 상에 상기 콘택홀의 측벽을 덮도록 연장되는 절연 물질의 보호막을 증착하고, 상기 보호막을 이방성 식각하여 상기 포토레지스트 패턴 상을 노출하고, 상기 콘택홀의 측벽을 이루는 상기 유기 폴리머를 차폐하여 보호하는 스페이서(spacer)를 형성한 후, 상기 포토레지스트 패턴을 제거하는 것을 특징으로 하는 반도체 장치의 콘택홀 형성 방법이 제공된다.In order to achieve the technical object of the present invention, a lower metal pattern is formed on a semiconductor substrate, a low dielectric polymer is deposited on the lower metal pattern to form an interlayer insulating film, a capping insulating film is formed on the interlayer insulating film, and Forming a photoresist pattern on the capping insulating layer, forming a contact hole by sequentially etching the interlayer insulating layer and the capping insulating layer using the photoresist pattern as an etching mask, and covering the sidewall of the contact hole on the photoresist pattern; Depositing a protective film of an insulating material that is extended, anisotropically etching the protective film to expose the photoresist pattern, and forming a spacer to shield and protect the organic polymer forming the sidewall of the contact hole, and then The cone of the semiconductor device characterized by removing the resist pattern The forming hole method is provided.

이하, 첨부 도면을 참조하여 본 발명의 실시예를 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명에서는 콘택홀의 내측면에 스페이서를 형성함으로써 저유전 폴리머로 이루어진 콘택홀의 내측면이 포토레지스트의 제거 공정시에 노출되지 않도록 하여 손상을 방지한다.In the present invention, by forming a spacer on the inner surface of the contact hole, the inner surface of the contact hole made of the low dielectric polymer is not exposed during the removal process of the photoresist, thereby preventing damage.

도 2a 내지 도 2g는 본 발명의 일 실시예에 따른 반도체 장치의 콘택홀 형성 방법을 설명하기 위하여 도시한 단면도들이다.2A to 2G are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to an embodiment of the present invention.

도 2a는 반도체 기판(11)상에 하부 금속 패턴(12)과 제1 캡핑 절연막(13)을 차례로 형성하는 단계를 도시한다.FIG. 2A illustrates a step of sequentially forming the lower metal pattern 12 and the first capping insulating layer 13 on the semiconductor substrate 11.

먼저, 반도체 기판(11)상에 하부 금속 패턴(12)을 형성한다. 상기 하부 금속 패턴(12)은 불순물이 도핑된 폴리실리콘, 알루미늄, 티타늄, 질화 티타늄(TiN), 텅스텐, 텅스텐 실리사이드 또는 티타늄 실리사이드로 형성할 수 있다.First, the lower metal pattern 12 is formed on the semiconductor substrate 11. The lower metal pattern 12 may be formed of polysilicon, aluminum, titanium, titanium nitride (TiN), tungsten, tungsten silicide or titanium silicide doped with impurities.

이어서, 상기 결과물 전면에 실리콘 산화막 또는 실리콘 질화막을 증착하여 제1 캡핑 절연막(13)을 형성한다. 상기 제1 캡핑 절연막(13)은 상기 하부 금속 패턴(12)과 후속 공정에서 형성되는 층간 절연막(15)의 접촉 특성을 향상시키기 위한 것으로서, 접촉 특성이 문제되지 않는 경우에는 상기 제 1 캡핑 절연막(13) 형성 공정은 생략할 수 있다.Subsequently, a silicon oxide film or a silicon nitride film is deposited on the entire surface of the resultant to form a first capping insulating layer 13. The first capping insulating layer 13 is to improve contact characteristics between the lower metal pattern 12 and the interlayer insulating layer 15 formed in a subsequent process. When the contact characteristics are not a problem, the first capping insulating layer 13 13) The formation step can be omitted.

도 2b는 층간 절연막(15)을 형성한 결과를 도시한다.2B shows the result of forming the interlayer insulating film 15.

상기 제1 캡핑 절연막(13)상에 저유전 폴리머, 특히 유기계 폴리머로 층간 절연막(15)을 형성하는데, 예를 들어 플레어(flare) 또는 benzocyclobutene(이하, BCB라 함)을 스핀 코팅(spin coating) 및 화학 기상 증착 방법 중 어느 하나의 방법을 이용한다.An interlayer insulating film 15 is formed on the first capping insulating layer 13 by using a low dielectric polymer, particularly an organic polymer. For example, a flare or benzocyclobutene (hereinafter referred to as BCB) is spin coated. And a chemical vapor deposition method.

상기 저유전 폴리머는 우수한 평탄도 특성을 가지므로 후속 공정이 원활히 진행될 수 있으며, 동시에 낮은 유전율을 가지므로 기생 용량을 감소시킬 수 있다.Since the low dielectric polymer has excellent flatness characteristics, subsequent processes may be performed smoothly, and at the same time, since the low dielectric constant has a low dielectric constant, parasitic capacitance may be reduced.

도 2c는 제2 캡핑 절연막(17) 및 포토레지스트 패턴(19)을 형성한 결과를 도시한다.2C illustrates a result of forming the second capping insulating layer 17 and the photoresist pattern 19.

상기 층간 절연막(15)의 상부에 실리콘 산화막으로 이루어진 제2 캡핑 절연막(17)을 형성한다. 상기 제2 캡핑 절연막(17)은 저유전 폴리머로 이루어진 상기 층간 절연막(15)의 상부가 후속되는 포토레지스트 형성 공정에서 산소와 반응하여 손상되는 것을 방지하기 위한 것이다.A second capping insulating layer 17 made of a silicon oxide layer is formed on the interlayer insulating layer 15. The second capping insulating layer 17 is to prevent the upper portion of the interlayer insulating layer 15 made of a low dielectric polymer from being damaged by reacting with oxygen in a subsequent photoresist forming process.

이어서, 상기 제2 캡핑 절연막(17) 전면에 포토레지스트를 도포한 후, 콘택홀(20)이 형성될 부분이 개구되도록 식각하여 포토레지스트 패턴(19)을 형성한다.Subsequently, after the photoresist is coated on the entire surface of the second capping insulating layer 17, the photoresist pattern 19 is formed by etching the opening to form the contact hole 20.

도 2d는 콘택홀(20)이 형성된 결과를 도시한다.2D shows the result of the contact hole 20 being formed.

상기 포토레지스트 패턴(19)을 식각 마스크로 하고 상기 하부 금속 패턴(12)을 식각 저지층으로 하여 상기 제2 캡핑 절연막(17), 상기 층간 절연막(15) 및 상기 제1 캡핑 절연막(13)을 차례로 패터닝한다. 그 결과, 상기 하부 금속 패턴(12)의 소정 부위를 노출시키는 콘택홀(20)이 형성된다. 이때, 상기 콘택홀(20)의 내측면에는 저유전 폴리머로 이루어진 층간 절연막(15)이 노출된다.The second capping insulating layer 17, the interlayer insulating layer 15, and the first capping insulating layer 13 are formed by using the photoresist pattern 19 as an etch mask and the lower metal pattern 12 as an etch stop layer. Pattern them in turn. As a result, a contact hole 20 exposing a predetermined portion of the lower metal pattern 12 is formed. In this case, the interlayer insulating layer 15 made of a low dielectric polymer is exposed on the inner surface of the contact hole 20.

도 2e는 보호막(21)이 형성된 결과를 도시한다.2E shows the result of the protective film 21 being formed.

상기 결과물의 전면에 실리콘 산화막 또는 실리콘 질화막을 증착하여 보호막(21)을 형성한다. 이때, 상기 보호막(21)은 상기 포토레지스트 패턴(19)이 연소되지 않을 정도의 온도 예컨대, 약 200℃ 이하의 저온에서 화학 기상 증착법으로 형성하는 것이 바람직하다.The protective film 21 is formed by depositing a silicon oxide film or a silicon nitride film on the entire surface of the resultant product. In this case, the protective film 21 is preferably formed by a chemical vapor deposition method at a temperature such that the photoresist pattern 19 does not burn, for example, at a low temperature of about 200 ° C. or less.

도 2f는 스페이서(21a)를 형성한 결과를 도시한다.2F shows the result of the formation of the spacer 21a.

상기 하부 금속 패턴(12)과 상기 포토레지스트 패턴(19)을 식각 저지층으로 하여 상기 보호막(21)을 이방성 식각하면, 상기 포토레지스트 패턴(19)의 상측 표면은 노출되고, 상기 콘택홀(20)의 내측면에는 스페이서(21a)가 형성된다. 상기 스페이서(21a)는 상기 콘택홀(20)의 내측면에 존재하는 저유전 폴리머가 외부와 접촉되는 것을 차단하여 보호하는 역할을 한다.When the protective layer 21 is anisotropically etched using the lower metal pattern 12 and the photoresist pattern 19 as an etch stop layer, an upper surface of the photoresist pattern 19 is exposed and the contact hole 20 is exposed. The spacer 21a is formed on the inner side of the. The spacer 21a serves to block and protect the low dielectric polymer present on the inner surface of the contact hole 20 from contacting the outside.

도 2g는 상기 포토레지스트 패턴(19)을 제거한 결과를 도시한다.2G shows the result of removing the photoresist pattern 19.

플라즈마 산소 가스를 이용하여 상기 포토레지스트 패턴(19)을 제거한다. 이때, 상기 콘택홀(20)의 내측면은 상기 스페이서(21a)에 의해 플라즈마 산소와의 접촉이 차단되므로 상기 포토레지스트 제거 공정시에 손상되지 않는다. 즉, 플라즈마 산소 등에 취약한 저유전 유기계 폴리머가 스페이서(21a)에 의해서 플라즈마 산소로부터 보호된다.The photoresist pattern 19 is removed using plasma oxygen gas. In this case, the inner surface of the contact hole 20 is not damaged during the photoresist removal process because the contact with the plasma oxygen is blocked by the spacer 21a. That is, the low dielectric organic polymer vulnerable to plasma oxygen or the like is protected from the plasma oxygen by the spacer 21a.

이어서, 도시되지는 않았으나, 상기 결과물상에 상부 금속을 증착하여 다층 금속 배선 공정을 수행할 수 있다.Subsequently, although not shown, a multilayer metallization process may be performed by depositing an upper metal on the resultant.

따라서, 양호한 내측면 프로파일(profile)을 갖는 콘택홀을 얻을 수 있으며, 후속 공정에서 보이드(void)의 발생이 억제되어 신뢰성 높은 반도체 소자를 제조할 수 있다.Therefore, a contact hole having a good inner side profile can be obtained, and the generation of voids can be suppressed in a subsequent step, whereby a highly reliable semiconductor device can be manufactured.

이상, 본 발명은 이에 한정되지 않으며, 본 발명의 기술적 사상의 범위내에서 당해 분야에서 통상의 지식을 가진 자에 의하여 다양하게 변형될 수 있다.As described above, the present invention is not limited thereto and may be variously modified by those skilled in the art within the scope of the technical idea of the present invention.

Claims (6)

(a)반도체 기판상에 하부 금속 패턴을 형성하는 단계;(a) forming a lower metal pattern on the semiconductor substrate; (b)상기 하부 금속 패턴상에 저유전 유기계 폴리머를 증착하여 층간 절연막을 형성하는 단계;(b) depositing a low dielectric organic polymer on the lower metal pattern to form an interlayer insulating film; (c)상기 층간 절연막상에 제1 캡핑 절연막을 형성하는 단계;(c) forming a first capping insulating film on the interlayer insulating film; (d)상기 제1 캡핑 절연막상에 포토레지스트 패턴을 형성하는 단계;(d) forming a photoresist pattern on the first capping insulating film; (e)상기 포토레지스트 패턴을 식각 마스크로 하고 상기 하부 금속 패턴을 식각 저지층으로 하여, 상기 층간 절연막과 상기 제1 캡핑 절연막을 차례로 식각함으로써 콘택홀을 형성하는 단계;(e) forming a contact hole by sequentially etching the interlayer insulating film and the first capping insulating film by using the photoresist pattern as an etch mask and the lower metal pattern as an etch stop layer; (f)상기 포토레지스트 패턴 상에 상기 콘택홀의 측벽을 덮도록 연장되는 절연 물질의 보호막을 증착하는 단계;(f) depositing a protective film of an insulating material extending on the photoresist pattern to cover sidewalls of the contact hole; (g)상기 보호막을 이방성 식각하여 상기 포토레지스트 패턴 상을 노출하고, 상기 콘택홀의 측벽을 이루는 상기 유기 폴리머를 차폐하여 보호하는 스페이서(spacer)를 형성하는 단계; 및(g) anisotropically etching the passivation layer to expose the photoresist pattern, and forming a spacer to shield and protect the organic polymer forming the sidewalls of the contact hole; And (h)상기 포토레지스트 패턴을 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 콘택홀 형성 방법.and (h) removing the photoresist pattern. 제1항에 있어서, 상기 (a)단계의 하부 금속 패턴은 불순물이 도핑된 폴리실리콘, 알루미늄, 티타늄, 질화 티타늄(TiN), 텅스텐, 텅스텐 실리사이드 및 티타늄 실리사이드로 이루어진 군으로부터 선택된 적어도 하나 이상으로 형성되는 것을 특징으로 하는 반도체 장치의 콘택홀 형성 방법.The method of claim 1, wherein the lower metal pattern of step (a) is formed of at least one selected from the group consisting of doped polysilicon, aluminum, titanium, titanium nitride (TiN), tungsten, tungsten silicide and titanium silicide And forming a contact hole in the semiconductor device. 제1항에 있어서, 상기 (c)단계의 제1 캡핑 절연막은 실리콘 산화막으로 형성되는 것을 특징으로 하는 반도체 장치의 콘택홀 형성 방법.The method of claim 1, wherein the first capping insulating film of step (c) is formed of a silicon oxide film. 제1항에 있어서, 상기 (f)단계의 보호막은 실리콘 산화막 및 실리콘 질화막으로 이루어진 군으로부터 선택된 적어도 하나 이상으로 형성되는 것을 특징으로 하는 반도체 장치의 콘택홀 형성 방법.The method of claim 1, wherein the protective film of step (f) is formed of at least one selected from the group consisting of a silicon oxide film and a silicon nitride film. 제1항에 있어서, 상기 (a)와 (b)단계 사이에 제2 캡핑 절연막을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 장치의 콘택홀 형성 방법.The method of claim 1, further comprising forming a second capping insulating film between the steps (a) and (b). 제5항에 있어서, 상기 제2 캡핑 절연막은 실리콘 산화막 및 실리콘 질화막으로 이루어진 군으로부터 선택된 적어도 하나 이상으로 형성되는 것을 특징으로 하는 반도체 장치의 콘택홀 형성 방법.The method of claim 5, wherein the second capping insulating layer is formed of at least one selected from the group consisting of a silicon oxide film and a silicon nitride film.
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JPH0669154A (en) * 1992-08-20 1994-03-11 Ricoh Co Ltd Through hole structure and its manufacture
KR960002486A (en) * 1994-06-15 1996-01-26 김주용 Method of forming multiple metal layers in semiconductor devices

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KR101033174B1 (en) * 2005-12-30 2011-05-11 아주대학교산학협력단 Glass micromachining using multi-step wet etching process
KR100784105B1 (en) * 2006-12-13 2007-12-10 주식회사 하이닉스반도체 Method of manufacturing a semiconductor device
US9978777B2 (en) 2016-01-11 2018-05-22 Samsung Display Co., Ltd. Display device including thin film transistor array panel and manufacturing method thereof

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