KR100813415B1 - Fabrication method of semiconductor device - Google Patents

Fabrication method of semiconductor device Download PDF

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KR100813415B1
KR100813415B1 KR1020010079096A KR20010079096A KR100813415B1 KR 100813415 B1 KR100813415 B1 KR 100813415B1 KR 1020010079096 A KR1020010079096 A KR 1020010079096A KR 20010079096 A KR20010079096 A KR 20010079096A KR 100813415 B1 KR100813415 B1 KR 100813415B1
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fluorine
oxide film
film
metal wiring
diffusion barrier
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KR20030049026A (en
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조경수
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

반도체 소자 제조 방법에 관한 것으로, 그 목적은 금속 배선이 들뜨는 현상인 디라미네이션을 방지하는 데 있다. 이를 위해 본 발명에서는, 하부 금속 배선을 포함한 반도체 구조물 상부에 불소 함유 산화막한 후 그 상부에 실리콘산화막을 증착하고 평탄화하는 단계; 실리콘산화막 상부에 불소 확산 방지막을 형성하는 단계; 불소 확산 방지막과 실리콘산화막, 불소 함유 산화막을 선택적으로 식각하여 하부 금속 배선의 일부가 드러나도록 비아를 형성하는 단계를 순차적으로 수행한다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and an object thereof is to prevent delamination, which is a phenomenon in which metal wiring is lifted up. To this end, the present invention comprises the steps of depositing and planarizing a silicon oxide film on top of the fluorine-containing oxide film on the semiconductor structure including the lower metal wiring; Forming a fluorine diffusion barrier on the silicon oxide layer; The fluorine diffusion prevention film, the silicon oxide film, and the fluorine-containing oxide film are selectively etched to sequentially form vias so that a part of the lower metal wiring is exposed.

불소, 디라미네이션, 실리콘질화막 Fluorine, Delamination, Silicon Nitride

Description

반도체 소자 제조 방법 {Fabrication method of semiconductor device}Fabrication method of semiconductor device

도 1a 및 1b는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

본 발명은 반도체 소자 제조 방법에 관한 것으로, 더욱 상세하게는 금속 배선층 상부에 불소 함유 산화막을 사용하여 절연체층을 형성하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of forming an insulator layer by using a fluorine-containing oxide film on a metal wiring layer.

반도체 소자가 점차 고집적화, 다층화됨에 따라 중요한 기술의 하나로 다층 배선 기술이 등장하게 되었는데, 이와 같은 다층 배선 기술은 금속 배선층과 절연막층을 회로 소자가 형성된 반도체 기판 상부에 교대로 형성하며, 절연막에 의해 분리된 금속 배선층 사이를 비아를 통해 전기적으로 접속함으로써 회로 동작이 이루어지도록 하는 것이다.As semiconductor devices have been increasingly integrated and multilayered, multilayer wiring has emerged as one of the important technologies. The multilayer wiring technology alternately forms a metal wiring layer and an insulating film layer on the semiconductor substrate on which the circuit elements are formed, and is separated by an insulating film. The circuit operation is performed by electrically connecting the interconnected metal wiring layers through vias.

최근 금속 배선층 상에 형성하는 절연체층으로서 낮은 유전상수를 갖는 불소 함유 산화막을 선호하고 있다.Recently, a fluorine-containing oxide film having a low dielectric constant is preferred as an insulator layer formed on a metal wiring layer.

그러나, 불소 함유 산화막에서는 불소가 상부로 이동하여 금속과 산화막 사이의 계면에 축적됨으로써 열공정 진행시 금속배선을 들뜨게 하는 현상인 디라미네 이션(delamination)을 유발하는 문제점이 있었다.However, in the fluorine-containing oxide film, fluorine moves upwards and accumulates at the interface between the metal and the oxide film, causing a delamination, which is a phenomenon of lifting the metal wiring during the thermal process.

본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 금속 배선이 들뜨는 현상인 디라미네이션을 방지하는 데 있다.The present invention has been made to solve the above problems, and an object thereof is to prevent delamination, which is a phenomenon in which metal wiring is lifted up.

상기한 바와 같은 목적을 달성하기 위하여, 본 발명에 따른 반도체 소자 제조 방법은, 하부 금속 배선을 포함한 반도체 구조물 상부에 불소 함유 산화막한 후 그 상부에 실리콘산화막을 증착하고 평탄화하는 단계; 실리콘산화막 상부에 불소 확산 방지막을 형성하는 단계; 불소 확산 방지막과 실리콘산화막, 불소 함유 산화막을 선택적으로 식각하여 하부 금속 배선의 일부가 드러나도록 비아를 형성하는 단계를 포함하여 이루어진다. In order to achieve the object as described above, the semiconductor device manufacturing method according to the present invention comprises the steps of depositing and planarizing a silicon oxide film on the fluorine-containing oxide film on top of the semiconductor structure including the lower metal wiring; Forming a fluorine diffusion barrier on the silicon oxide layer; And selectively etching the fluorine diffusion preventing film, the silicon oxide film, and the fluorine-containing oxide film to form a via to expose a portion of the lower metal wiring.

이 때, 불소 확산 방지막은 실리콘질화막, SiC 및 SiON 중의 어느 하나 이상으로 적층하여 형성하며, 1000Å 미만의 두께로 형성하는 것이 바람직하다.At this time, the fluorine diffusion prevention film is formed by laminating with any one or more of silicon nitride film, SiC, and SiON, and is preferably formed with a thickness of less than 1000 GPa.

또한, 불소 확산 방지막을 형성하기 전, 형성한 후, 또는 형성 전 후에, 열처리하는 것이 바람직하며, 열처리는 200℃ 내지 500℃의 온도로, 퍼니스 내에서 10분 이상동안 하는 것이 바람직하다.In addition, before or after the formation of the fluorine diffusion prevention film, or after the formation, it is preferable to perform heat treatment, and the heat treatment is preferably performed at a temperature of 200 ° C to 500 ° C for at least 10 minutes in the furnace.

이하, 본 발명에 따른 반도체 소자 제조 방법에 대해 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail.

본 발명에서는 불소 함유 산화막으로부터 불소가 상부로 이동하여 금속과 산화막의 계면에 축적되는 것을 방지하기 위해, 불소 함유 산화막의 상부에 실리콘질화막층, SiC층, 및 SiON층 중의 어느 하나 이상을 형성하며, 이로써 불소의 이동을 억제한다.In the present invention, in order to prevent fluorine from moving upward from the fluorine-containing oxide film and accumulating at the interface between the metal and the oxide film, at least one of a silicon nitride film layer, an SiC layer, and a SiON layer is formed on the fluorine-containing oxide film. This suppresses the movement of fluorine.

이하, 실시예를 통해 본 발명을 더욱 상세히 설명한다.Hereinafter, the present invention will be described in more detail with reference to Examples.

도 1a 내지 1b는 본 발명에 따라 제조된 반도체 소자를 도시한 단면도이다.1A to 1B are cross-sectional views illustrating a semiconductor device manufactured according to the present invention.

먼저, 도 1a에 도시된 바와 같이, 반도체 기판(1)의 구조물(미도시), 즉 개별 소자가 형성된 반도체 기판 또는 하부 금속 배선층 상부에 산화막 등으로 이루어진 하부절연막(2)을 형성하고, 하부절연막(2) 상에 금속배선막을 형성하고 패터닝하여 하부 금속 배선(3)을 형성한다. First, as shown in FIG. 1A, a lower insulating film 2 made of an oxide film or the like is formed on a structure (not shown) of the semiconductor substrate 1, that is, on a semiconductor substrate on which individual elements are formed or on a lower metal wiring layer. A metal wiring film is formed and patterned on (2) to form the lower metal wiring 3.

다음, 하부 금속 배선(3)을 포함한 상부 전면에 불소 함유 산화막(4)을 증착하고, 그 상부에 일반적인 절연막(5)을 증착한 후, 화학기계적 연마하여 절연막(5)의 상면을 평탄화한다. 절연막(5)은 통상적인 실리콘산화막(SiOx)으로 형성하는 것이 바람직하다.Next, a fluorine-containing oxide film 4 is deposited on the entire upper surface including the lower metal wiring 3, a general insulating film 5 is deposited thereon, and then chemically polished to planarize the top surface of the insulating film 5. The insulating film 5 is preferably formed of a conventional silicon oxide film (SiOx).

이어서, 절연막(5) 상에 불소 확산 방지막으로 실리콘질화막(6)을 증착하고, 그 상부에 감광막을 도포하고 노광 현상하여 비아로 예정된 영역의 상부에 해당하는 감광막을 제거함으로써 감광막 패턴(7)을 형성한다. 실리콘질화막(6) 대신에 불소 확산 방지막으로 SiC 또는 SiON을 형성할 수도 있고, 또는 이들 중 하나 이상을 적층할 수도 있다. 이 때, 실리콘질화막, SiC, 및 SiON 중의 어느 하나 이상으로 적층되는 불소 확산 방지막은 1000Å 미만의 두께가 되도록 하는 것이 바람직하다.Subsequently, a silicon nitride film 6 is deposited on the insulating film 5 with a fluorine diffusion preventing film, a photoresist film is applied on the upper portion thereof, and an exposure development is performed to remove the photoresist film corresponding to the upper portion of the region intended as a via. Form. Instead of the silicon nitride film 6, SiC or SiON may be formed by a fluorine diffusion preventing film, or one or more of them may be laminated. At this time, it is preferable that the fluorine diffusion prevention film laminated | stacked by any one or more of a silicon nitride film, SiC, and SiON is set to thickness less than 1000 kPa.

또한, 불소 확산 방지막으로 실리콘질화막, SiC, 및 SiON 중의 어느 하나 이상을 적층하기 전이나, 적층한 후, 또는 적층 전과 후 모두, 열처리할 수 있다. 열처리할 때에는 200 내지 500℃의 온도로 하며, 열처리를 퍼니스 내에서 수행할 경우에는 10분 이상동안 할 수도 있다In addition, the fluorine diffusion prevention film can be subjected to heat treatment before or after laminating any one or more of the silicon nitride film, SiC, and SiON. When the heat treatment is carried out at a temperature of 200 to 500 ℃, if the heat treatment is carried out in the furnace may be for 10 minutes or more.

다음, 도 1b에 도시된 바와 같이, 감광막 패턴(7)을 마스크로 이용하여 노출된 불소 확산 방지막인 실리콘질화막(6) 및 그 하부의 절연막(5)과 불소 함유 산화막(4)을 건식식각하여 비아홀(100)을 형성한다.Next, as shown in FIG. 1B, the silicon nitride film 6, the insulating film 5 and the fluorine-containing oxide film 4, which are exposed fluorine diffusion films using the photosensitive film pattern 7 as a mask, is dry-etched. The via hole 100 is formed.

이어서, 비아홀(100)의 내벽을 포함한 상부 전면에 베리어 메탈(8)을 형성하고, 베리어 메탈(8) 상에 비아홀(100)을 충분히 충진시키도록 금속 배선(9)을 형성한 후, 금속 배선(9) 상에 반사방지막(10)을 형성한다.Subsequently, the barrier metal 8 is formed on the upper front surface including the inner wall of the via hole 100, and the metal wiring 9 is formed on the barrier metal 8 to sufficiently fill the via hole 100. An antireflection film 10 is formed on (9).

다음, 통상적인 사진식각공정에 의해 반사방지막(10), 금속 배선(9) 및 베리어 메탈(8)을 선택적으로 식각하여 이웃하는 금속 배선과 분리되도록 한다.Next, the anti-reflection film 10, the metal wiring 9 and the barrier metal 8 are selectively etched by a conventional photolithography process so as to be separated from the neighboring metal wiring.

상술한 바와 같이, 본 발명에서는 금속 배선 상에 불소 함유 산화막을 형성할 때 불소 함유 산화막의 상부에 불소 확산 방지막으로 실리콘질화막, SiC, SiON 등을 형성하며, 이로써 불소가 상부 구조로 이동하는 것을 억제하여 금속 배선의 들뜸현상인 디라미네이션을 방지하는 효과가 있다.As described above, in the present invention, when forming a fluorine-containing oxide film on the metal wiring, a silicon nitride film, SiC, SiON, etc. are formed on the fluorine-containing oxide film as a fluorine diffusion preventing film, thereby suppressing fluorine from moving to the upper structure. Therefore, there is an effect of preventing the delamination which is a floating phenomenon of metal wiring.

따라서, 디라미네이션에 기인한 소자의 불량발생률 감소를 방지하여 수율을 향상시키는 효과가 있다.Therefore, there is an effect of improving the yield by preventing the reduction of the defective rate of the device due to the delamination.

Claims (5)

하부 금속 배선을 포함한 반도체 구조물 상부에 불소 함유 산화막을 형성한 후 그 상부에 실리콘산화막을 증착하고 평탄화하는 단계;Forming a fluorine-containing oxide film on the semiconductor structure including the lower metal interconnection, and then depositing and planarizing a silicon oxide film on the fluorine-containing oxide film; 상기 실리콘산화막 상부에 불소 확산 방지막을 형성하는 단계;Forming a fluorine diffusion barrier on the silicon oxide layer; 상기 불소 확산 방지막과 실리콘산화막, 불소 함유 산화막을 선택적으로 식각하여 상기 하부 금속 배선의 일부가 드러나도록 비아를 형성하는 단계;Selectively etching the fluorine diffusion barrier layer, the silicon oxide layer, and the fluorine-containing oxide layer to form a via to expose a portion of the lower metal interconnection; 상기 비아의 내벽 및 불소 확산 방지막 상에 배리어 메탈을 형성하는 단계; 및Forming a barrier metal on the inner wall of the via and the fluorine diffusion barrier layer; And 상기 비아 및 배리어 메탈 상에 금속 배선을 형성하는 단계를 포함하는 반도체 소자 제조 방법.Forming a metal wiring on the via and the barrier metal. 제 1 항에 있어서, 상기 불소 확산 방지막은 1000Å 미만의 두께로 형성하는 것을 특징으로 하는 반도체 소자 제조 방법.The method of claim 1, wherein the fluorine diffusion barrier is formed to a thickness of less than 1000 GPa. 제 1 항에 있어서, 상기 불소 확산 방지막은 실리콘질화막, SiC 및 SiON 중의 어느 하나 이상으로 적층하여 형성하는 것을 특징으로 하는 반도체 소자 제조 방법.The method of claim 1, wherein the fluorine diffusion barrier is formed by stacking at least one of silicon nitride, SiC, and SiON. 제 1 항에 있어서, 상기 불소 확산 방지막을 형성하기 전, 형성한 후, 또는 형성 전 후에, 열처리하는 것을 특징으로 하는 반도체 소자 제조 방법.The method of manufacturing a semiconductor device according to claim 1, wherein heat treatment is performed before, after, or before formation of the fluorine diffusion barrier. 제 4 항에 있어서, 상기 열처리는 200℃ 내지 500℃의 온도로 하는 것을 특징으로 하는 반도체 소자 제조 방법.The method of claim 4, wherein the heat treatment is performed at a temperature of 200 ° C. to 500 ° C. 6.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990023749A (en) * 1997-08-22 1999-03-25 가네꼬 히사시 Semiconductor device and manufacturing method
KR100295380B1 (en) * 1997-04-02 2001-08-07 가네꼬 히사시 Semiconductor device capable of having amorphous carbon fluoride film of low dielectric constant as interlayer insulation material and method of manufacturing the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100295380B1 (en) * 1997-04-02 2001-08-07 가네꼬 히사시 Semiconductor device capable of having amorphous carbon fluoride film of low dielectric constant as interlayer insulation material and method of manufacturing the same
KR19990023749A (en) * 1997-08-22 1999-03-25 가네꼬 히사시 Semiconductor device and manufacturing method

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