KR20070115353A - Method of forming a pattern in semiconductor device and method of forming a cell pattern in non-volatile memory using the same - Google Patents

Abstract

A method for forming a pattern of a semiconductor device and a method for forming a cell pattern of a non volatile memory using the same, are provided to prevent an insulating layer, a tunnel oxide layer and a dielectric from being damaged by forming a first and a second buffer layers to surround a circuit pattern. An insulating layer(104) including a first oxide and a conductive layer are formed on a substrate(100) sequentially. A mask pattern including a second oxide is formed on the conductive layer. A preliminary pattern is formed by patterning the mask pattern. A first buffer layer(116) is formed on the preliminary pattern. A space type second buffer layer(120) is formed on the first buffer layer. The first buffer layer and the mask pattern are removed. A pattern structure is formed by removing the second buffer layer.

Description

Method of forming a pattern in semiconductor device and method of forming a cell pattern in non-volatile memory using the same}

1 to 8 are schematic cross-sectional views illustrating a method of forming a gate electrode according to an exemplary embodiment of the present invention.

9 through 16 are schematic cross-sectional views illustrating a method of forming a cell pattern of a nonvolatile memory according to another exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 102 device isolation region

104: gate insulating film 106: conductive film

108: conductive film pattern 110: second mask pattern

112: preliminary gate electrode 116: first buffer film

118: preliminary second buffer film 120: second buffer film

The present invention relates to a method of manufacturing a pattern and a cell pattern forming method of a nonvolatile memory using the same. More specifically, the present invention relates to a method for manufacturing a semiconductor device that performs patterning of a circuit pattern using a mask pattern containing an oxide.

In a rapidly developing information society, a high-integration device having a high data transfer rate is required to process a large amount of information more quickly. In order to manufacture highly integrated semiconductor devices, design rules of semiconductor devices are rapidly decreasing. Therefore, semiconductor devices require more fine patterns.

In the microcircuit process, the most basic technique is a photographic technique, and photolithography using light is commonly used. However, such photolithography cannot be easily applied to the formation of line and space patterns of 100 nm or less.

As described above, an oxide film is used as a mask pattern during the patterning process of 100 nm or less. However, thereafter, a problem arises in that the portion of the circuit pattern, which is made of oxide, is also removed while removing the mask pattern.

When the transistor is formed, for example, the gate oxide film and the conductive film are sequentially formed on the semiconductor substrate. A conductive pattern is formed by forming a mask pattern made of an oxide on the conductive layer and patterning the conductive layer using the mask pattern as an etching mask.

In this case, when the conductive pattern is polysilicon, an impurity is injected into the polysilicon, or when a metal silicide pattern is formed on the polysilicon, the mask pattern formed on the conductive pattern is removed. Should be.

However, at this time, since the mask pattern is made of an oxide, there is a problem that the gate oxide film is removed together while removing the mask pattern.

As another example, even when forming a flash memory, the tunnel oxide film and the dielectric film may be removed or damaged together while removing the mask pattern made of the oxide.

One object of the present invention for solving the above problems is to provide a pattern forming method using a mask pattern made of oxide.

Another object of the present invention for solving the above problems is to provide a cell pattern forming method of a nonvolatile memory using the pattern forming method.

According to an aspect of the present invention for achieving the above object, in the method for forming a pattern, an insulating film and a conductive film including a first oxide are sequentially formed on a substrate. A mask pattern including a second oxide is formed on the conductive film. The conductive layer is patterned using the mask pattern as an etch mask to form a preliminary pattern in which a mask pattern, an insulating layer pattern, and a conductive layer pattern are stacked. A first buffer film is formed on the surface of the preliminary pattern. A space type second buffer layer having an etch selectivity with the first buffer layer is formed on the first buffer layer formed on the sidewall of the preliminary pattern. The first buffer layer and the mask pattern formed on the mask pattern are removed. The second buffer layer is removed to form a pattern structure in which the insulating layer pattern and the conductive layer pattern are stacked.

The first buffer layer may include an oxide and the second buffer layer may include a nitride. The method of forming the pattern may further include removing the first buffer layer. The second buffer layer may be formed by continuously forming a preliminary second buffer layer on the first buffer layer, and then anisotropically etching the preliminary second buffer layer. The preliminary second buffer layer may be formed thicker than the first buffer layer.

According to an aspect of the present invention for achieving the above another object, in the cell pattern forming method of a nonvolatile memory, a dielectric film including a tunnel oxide film, a floating gate pattern, a second oxide comprising a first oxide on a semiconductor substrate And a conductive film for a control gate are sequentially formed. A mask pattern including a third oxide is formed on the second conductive film. The conductive layer, the dielectric layer, and the floating gate pattern are patterned using the mask pattern as an etching mask to form a preliminary cell pattern. A first buffer film is continuously formed on the surface of the preliminary cell pattern. A spacer type second buffer layer having a selective etching ratio with the first buffer layer is formed on the first buffer layer formed on the sidewall of the preliminary cell pattern. The first buffer layer formed on the mask pattern and the mask pattern are removed. The second buffer layer is removed.

The first buffer layer may include an oxide and the second buffer layer may include a nitride.

According to the present invention as described above, the oxide formed in the pattern can be protected by forming the first buffer film and the second buffer film to protect the pattern while removing the mask pattern including the oxide.

Hereinafter, a method of forming a pattern according to a preferred embodiment of the present invention will be described in detail.

1 to 8 are schematic cross-sectional views illustrating a method of forming a gate electrode according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the semiconductor substrate 100 is divided into an active region and an isolation region by performing a shallow trench device isolation process.

In more detail, first, a pad oxide film (not shown) and a silicon nitride film (not shown) are sequentially formed on the semiconductor substrate 100. The pad oxide layer may be formed by a thermal oxidation process, and the silicon nitride layer may be formed by a low pressure chemical vapor deposition process.

A first photoresist pattern (not shown) is formed to selectively expose the silicon nitride film. A portion of the substrate 100 exposed by the first photoresist pattern becomes a field region, and a portion of the substrate 100 masked by the first photoresist pattern becomes an active region.

Subsequently, the silicon nitride layer and the pad oxide layer are sequentially etched using the first photoresist pattern as an etch mask to form a first mask pattern (not shown) including the silicon nitride layer pattern and the pad oxide layer pattern. In this case, the first mask pattern is formed in the active region. After forming the first mask pattern, the first photoresist pattern is removed by an ashing process or a strip process.

Subsequently, the exposed semiconductor substrate 100 is etched using the first mask pattern as an etching mask to form a trench. Subsequently, silicon having excellent gap filling characteristics such as Undoped Silicate Glass (USG), O ₃ -TEOS USG (O ₃ -Tetra Ethyl Ortho Silicate Undoped Silicate Glass), or High Density Plasma (HDP) oxide film to fill the trench An oxide film is formed by a chemical vapor deposition (CVD) method. Subsequently, the silicon oxide layer is polished to expose the surface of the semiconductor substrate 100 by an etch back or chemical mechanical polishing process to form an insulating layer pattern in the trench.

As a result, the semiconductor substrate is divided into a field region and an active region where the insulating layer pattern 102 is formed.

Referring to FIG. 2, a gate insulating film 104 is formed on the substrate 100 on which the insulating film pattern is formed. The gate insulating film 104 is a silicon oxide film, which is thinly formed on the semiconductor substrate 100 by a thermal oxidation process.

Subsequently, a gate electrode conductive film 106 is formed on the gate insulating film 104.

The conductive layer 106 may be a polysilicon layer. In more detail, the polysilicon is a polysilicon layer doped with a high concentration of impurities by a doping process such as a diffusion process, an ion implantation process, or an in-situ doping process.

In some cases, the conductive layer 106 may have a laminated structure of a polysilicon layer and a metal layer. However, in this embodiment, the conductive film 106 made of a polysilicon layer is used. In more detail, a polysilicon layer doped with N-type impurities may be used as the polysilicon layer. However, the doping impurity is not limited.

Referring to FIG. 3, a mask film (not shown) including an oxide is formed on the conductive film 106. The mask film is formed by a plasma enhanced chemical vapor deposition method, and examples of the mask film include silicon oxide (SiO ₂ ).

Subsequently, a second photoresist pattern (not shown) is formed on the mask film to partially expose the mask film. The mask layer is etched using the second photoresist pattern as an etch mask to form a second mask pattern 110.

After forming the second mask pattern 110, the second photoresist pattern is removed by an ashing and stripping process.

Subsequently, the conductive film 106 is etched using the second mask pattern 110 as an etch mask to form the preliminary gate electrode 112 having the conductive film pattern 108 and the second mask pattern 110 stacked thereon. Form.

Here, patterning the conductive layer 106 using the second mask pattern 110 including silicon oxide as an etch mask may reduce the aspect ratio of the etch mask than when using the photoresist pattern as the etch mask. This is because a fine pattern can be realized by using a thin etching mask.

Referring to FIG. 4, a first buffer layer 116 is continuously formed along the surface of the preliminary gate electrode 112.

The first buffer layer 116 has a shape covering the surface of the preliminary gate electrode. Therefore, the gate insulating film 104 may be prevented from being etched by the etching process of the second mask pattern 110. This will be described later in detail.

In this case, the first buffer layer 116 includes an oxide, and examples of the first buffer layer 116 include a medium temperature oxide film, a room temperature oxide film, and the like.

In addition, the first buffer layer 116 is formed to a first thickness along the surface of the preliminary gate electrode 112, and the first thickness is as thin as several tens of micrometers.

Referring to FIG. 5, a preliminary second buffer layer 118 having an etch selectivity with respect to the first buffer layer 116 is formed along the surface of the first buffer layer 116.

The preliminary second buffer layer 118 should have an etching selectivity with respect to the first buffer layer 116 with respect to the same etching solution. In more detail, the preliminary second buffer layer 118 is hardly etched while the first buffer layer 116 is etched in the same etching solution. Therefore, when the first buffer layer 116 includes an oxide, the preliminary second buffer layer 118 includes nitride. An example of the second buffer layer 120 may be a silicon nitride layer.

In addition, the EBI second buffer layer has a second thickness thicker than the first thickness. Here, the second thickness is a few hundred millimeters thick.

Referring to FIG. 6, the preliminary anisotropic etching of the preliminary second buffer layer 118 is performed to form a spacer-type second buffer layer 120 on the first buffer layer 116 formed on the sidewall of the preliminary gate electrode 112. do.

In more detail, only the preliminary second buffer layer 118 formed horizontally with the semiconductor substrate 100 by performing the front anisotropic etching is selectively etched, and the preliminary second formed on the sidewall of the preliminary gate electrode 112. The buffer film 118 is left without being etched. Accordingly, the spacer type second buffer layer 120 is formed on the first buffer layer 116 formed on the sidewall of the preliminary gate electrode 112.

In this case, the first buffer layer 116 formed on the upper surface of the preliminary gate electrode 112 may be exposed during the entire surface etching process. This is because in the isotropic etching or the anisotropic etching of the first buffer layer 116 and the second mask pattern 110 later, a part of the first buffer layer 116 is exposed to be removed.

Referring to FIG. 7, the first buffer layer 116 and the second mask pattern 110 formed on the second mask pattern 110 are removed.

The first buffer layer 116 and the second mask pattern 110 may be removed by isotropic or anisotropic etching.

In more detail, a method of removing the first buffer layer 116 and the second mask pattern 110 by isotropic etching is described first. First, the first buffer layer 116 formed on the preliminary conductive layer electrode 112 is removed. Etch using hydrofluoric acid diluent. As a result, the first buffer layer 116 formed on the preliminary conductive layer electrode 112 is removed to expose the upper surface of the second mask pattern 110 under the first buffer layer 116. Here, the first buffer layer 116 formed on the gate insulating layer 104 may be removed, but the first buffer layer 116 formed on the sidewall of the preliminary gate electrode 112 may have a second buffer layer 120. Masked by and not removed.

Subsequently, the exposed second mask pattern 110 is removed using a hydrofluoric acid diluent to expose the top surface of the conductive layer pattern 108. The gate insulating layer 102 formed under the first buffer layer 116 may be partially removed while the second mask pattern 110 is removed. As a result, the gate electrode 124 including the gate insulating layer pattern and the conductive layer pattern 108 is formed on the semiconductor substrate 100.

Here, even if the second mask pattern 110 made of oxide is completely removed, since the damage is not applied to the gate insulating film pattern 122 made of oxide under the gate electrode 124, the function of the gate electrode 124 is performed. Can be maintained normally.

In addition, the surface of the conductive film pattern 108 is exposed by completely removing the second mask pattern 110. Therefore, an impurity implantation process or a metal silicidation process may be performed.

Referring to FIG. 8, the second buffer layer 120 is etched.

The second buffer layer 120 is removed by isotropic etching. In more detail, since the second buffer layer 120 includes nitride, the second buffer layer 120 may be removed by performing wet etching using phosphoric acid as an etching solution. At this time, since the remaining first buffer layer 116 is made of an oxide, it is hardly etched. In addition, the gate insulating layer pattern 122 formed under the conductive layer pattern 108 is hardly etched.

Subsequently, a process of removing the first buffer layer 116 remaining on the sidewall of the conductive layer pattern 108 may be further performed. The first buffer layer 116 may be removed using a hydrofluoric acid diluent. Alternatively, the first buffer layer 116 is an oxide so that it can be naturally cleaned during the subsequent cleaning of the resultant.

Although not shown in detail, impurities may be implanted into the gate electrode 124 in some cases. In more detail, when the conductive film pattern 108 of the gate electrode 124 is formed of a polysilicon layer, impurities may be implanted into the polysilicon layer having a surface exposed to form a PMOS or NMOS transistor. .

That is, in the case where the conductive film pattern 108 using the polysilicon layer doped with the N-type impurity is formed as in this embodiment, the P-type impurity is selectively doped on the upper surface of the polysilicon layer which will function as a PMOS transistor. do. Through the above process, gate electrodes suitable for PMOS and NMOS transistors can be formed in respective regions of the semiconductor substrate.

In this case, impurities are also injected into the lower portion of the semiconductor substrate 100 exposed to the side of the gate electrode 124 while the impurities are implanted, and the regions in which the impurities are implanted serve as source / drain regions.

In addition, when the conductive layer pattern 108 of the gate electrode 124 is formed of a polysilicon layer, a metal silicidation process may be performed on the polysilicon layer.

As described above, since the second mask pattern 110 is completely removed on the conductive film pattern 108 and the upper surface of the conductive film pattern 108 is exposed, impurity is injected into the gate electrode 124. Process and metal silicidation process can be performed.

Hereinafter, a method of forming a cell pattern of a nonvolatile memory according to a preferred embodiment of the present invention will be described in detail.

9 through 16 are schematic cross-sectional views illustrating a method of forming a cell pattern of a nonvolatile memory according to another exemplary embodiment of the present invention.

Referring to FIG. 9, an insulation film pattern (not shown) is formed on the semiconductor substrate 200 by performing the same process as described with reference to FIG. 1. As a result, the semiconductor substrate 200 is divided into a field region and an active region.

Subsequently, a thermal oxidation process, a chemical vapor deposition process, or an atomic layer deposition process is performed on the semiconductor substrate 200 to form the tunnel oxide film 202.

A first conductive film (not shown) for floating gate is formed on the tunnel oxide film 202. Examples of the first conductive film include a doped polysilicon film or a metal film. The first conductive layer is selectively etched to form a first conductive layer pattern 204 extending in the first direction.

A dielectric film (not shown) is formed along the first conductive film pattern 204. Examples of the dielectric film may include an oxide nitride oxide (ONO) film or a metal oxide film. That is, the dielectric film includes an oxide.

A second conductive film (not shown) for a control gate is formed on the dielectric film. In this case, the second conductive layer is formed to completely fill the gap between the first conductive layer pattern 204. Examples of the second conductive film may include a doped polysilicon film, a metal film, and a composite film in which a polysilicon film and a metal silicide film are stacked.

A mask film 208 made of oxide is formed on the second conductive film. The oxide is formed by a plasma enhanced chemical vapor deposition method, and examples of the mask layer 208 include silicon oxide (SiO 2), silicon oxynitride (SiON), and the like.

On the mask film 208, a photoresist pattern (not shown) for partially exposing the mask film 208 is formed. The photoresist pattern extends in a second direction perpendicular to the first direction.

Referring to FIG. 10, the mask layer 208 is etched using the photoresist pattern as an etch mask to form a mask pattern 210. Thus, the mask pattern 210 extends in the second direction. After the mask pattern 210 is formed, the photoresist pattern is removed by an ashing or strip process.

Referring to FIG. 11, the second conductive layer, the dielectric layer, and the first conductive layer pattern 204 are sequentially etched using the mask pattern 210 as an etching mask to control the gate 216 and the dielectric layer pattern 214. And forming floating gate 212.

As a result, a preliminary cell pattern 220 in which the floating gate 212, the dielectric layer pattern 214, the control gate 216, and the mask pattern 210 are stacked is formed on the tunnel oxide layer 202. In this case, the tunnel oxide layer 202, the dielectric layer, and the mask pattern 210 may include an oxide and may be etched together by the same etching solution.

Here, patterning the conductive layer using the mask pattern 210 including silicon oxide as an etch mask may reduce the aspect ratio of the etch mask than using the photoresist pattern as the etch mask. This is because fine pattern realization is possible by using.

Referring to FIG. 12, the first buffer layer 222 is continuously formed along the surface of the mask pattern 210. The first buffer layer 222 may prevent the dielectric layer pattern 214 and the tunnel oxide layer 202 from being etched by an etching process of the mask pattern 210.

The first buffer layer 222 may include an oxide, and examples of the first buffer layer 222 include a medium temperature oxide film, a room temperature oxide film, and the like. In addition, the first buffer layer 222 has a first thickness, and the first thickness is a few tens of microseconds.

Referring to FIG. 13, a preliminary second buffer layer 224 is continuously formed on the first buffer layer 222. The second buffer layer prevents the dielectric layer pattern 214 and the tunnel oxide layer 202 from being etched by an etching process of the mask pattern 210.

In this case, the preliminary second buffer layer 224 is formed using a material having an etching selectivity with respect to the first buffer layer 222. That is, while the first buffer layer 222 is etched with respect to the same etching solution, the second buffer layer has a hardly etched characteristic. Therefore, when the first buffer layer 222 includes an oxide, the second buffer layer includes nitride. Examples of the second buffer layer may include silicon nitride.

In addition, the preliminary second buffer layer 224 has a second thickness thicker than the first thickness. In this case, the second thickness is a few hundred millimeters thick.

Referring to FIG. 14, the preliminary second buffer layer 224 is anisotropically etched to form a spacer type second buffer layer 226 on the first buffer layer 222 formed on the sidewall of the cell pattern.

In more detail, only the preliminary second buffer layer 224 formed horizontally with the semiconductor substrate 200 by performing the front anisotropic etching is selectively etched, and the preliminary second formed on the sidewall of the preliminary cell pattern 220. The buffer layer 224 is left without being etched. Therefore, a spacer type second buffer layer 226 is formed on the first buffer layer 222 formed on the sidewall of the preliminary cell pattern 220.

In this case, the first buffer layer 222 formed on the upper surface of the preliminary cell pattern 220 may be exposed during the entire surface etching process. This is because in the isotropic etching or the anisotropic etching of the first buffer layer 222 and the mask pattern 210 later, a part of the first buffer layer 222 is exposed to be removed.

Referring to FIG. 15, the first buffer layer 222 and the mask pattern 210 formed on the mask pattern 210 are etched.

In more detail, a method of removing the first buffer layer 222 and the mask pattern 210 by isotropic etching will be described.

First, the exposed first buffer layer 222 is removed using a hydrofluoric acid diluent. In this case, the first buffer layer 222 formed on the tunnel oxide layer 202 is also removed. Subsequently, the surface of the mask pattern 210 formed under the first buffer layer 222 is exposed, and the exposed mask pattern 210 is removed by the hydrofluoric acid diluent.

Here, during the isotropic etching process, the second buffer layer 226 is formed of a nitride layer and is hardly etched, and thus the first buffer layer 222 and the preliminary cover covered by the second buffer layer 226 are preliminary. Neither side of the cell pattern 220 is etched.

As a result, the mask pattern 210 is completely removed to form the cell pattern 230. The cell pattern 230 includes a tunnel oxide layer pattern 228, a floating gate 212, a dielectric layer pattern 214, and a control gate 216.

As a result, even when the mask pattern 210 made of oxide is completely removed, the tunnel oxide film pattern 228 made of oxide remains below or equal to the line width of the cell pattern 230 under the cell pattern 230. The function of the pattern 230 may be performed better.

Referring to FIG. 16, the second buffer layer 226 is etched.

The second buffer layer 226 is removed by isotropic etching. In more detail, since the second buffer layer 226 includes nitride, the second buffer layer 226 may be removed by performing wet etching using phosphoric acid as an etching solution. At this time, since the remaining first buffer layer 222, the tunnel oxide layer, and the dielectric layer are made of oxide, they are hardly etched.

Subsequently, the process of removing the remaining first buffer layer 222 may be further performed. In detail, the first buffer layer 222 may be removed using a hydrofluoric acid diluent. Alternatively, the first buffer layer 222 may be an oxide, and thus may be naturally cleaned during the subsequent cleaning of the resultant.

As a result, the cell pattern 230 including the tunnel oxide layer, the floating gate 212, the dielectric layer pattern 214, and the control gate 216 may be formed on the semiconductor substrate 200.

As described above, according to a preferred embodiment of the present invention, by forming the first buffer film and the second buffer film to surround the circuit pattern, the circuit pattern is provided and made of oxide while removing the mask pattern containing oxide Damage to the insulating film, tunnel oxide film, and dielectric film can be suppressed in advance.

In addition, by completely removing the mask pattern on the circuit pattern, a process of injecting impurities into the circuit pattern or a metal silicidation process may be performed immediately.

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (7)

Sequentially forming an insulating film and a conductive film including a first oxide on the substrate; Forming a mask pattern including a second oxide on the conductive film; Patterning the conductive layer using the mask pattern as an etch mask to form a preliminary pattern in which a mask pattern, an insulating layer pattern, and a conductive layer pattern are stacked; Forming a first buffer layer on the surface of the preliminary pattern; Forming a space-type second buffer layer having an etch selectivity with the first buffer layer on the first buffer layer formed on the sidewall of the preliminary pattern; Removing the mask pattern and the first buffer layer formed on the mask pattern; And And removing the second buffer layer to form a pattern structure in which the insulating layer pattern and the conductive layer pattern are stacked. The method of claim 1, wherein the first buffer layer comprises an oxide and the second buffer layer comprises a nitride. The method of claim 1, further comprising removing the first buffer layer. The method of claim 1, wherein the forming of the second buffer layer comprises: Continuously forming a preliminary second buffer film on the first buffer film; And And anisotropically etching the preliminary second buffer layer. The method of claim 4, wherein the preliminary second buffer layer is formed to be thicker than the first buffer layer. Sequentially forming a tunnel oxide film including a first oxide, a first conductive film pattern for a floating gate, a dielectric film including a second oxide, and a second conductive film for a control gate on a semiconductor substrate; Forming a mask pattern including a third oxide on the second conductive layer; Forming a preliminary cell pattern by patterning the second conductive layer, the dielectric layer, and the first conductive layer pattern using the mask pattern as an etching mask; Continuously forming a first buffer film on the preliminary cell pattern surface; Forming a spacer-type second buffer layer having a select etch ratio with the first buffer layer on the first buffer layer formed on the sidewall of the preliminary cell pattern; Removing the mask pattern and the first buffer layer formed on the mask pattern; And Removing the second buffer layer; and forming a cell pattern of the nonvolatile memory. 7. The method of claim 6, wherein the first buffer layer comprises an oxide and the second buffer layer comprises a nitride.

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