JPH04230023A - Manufacture of cmos semiconductor device - Google Patents

Abstract

PURPOSE:To implant a polysilicon film with N type, and P type impurities in sufficient concentration without making a misalignment at all in the different step from the source drain formation step. CONSTITUTION:A polysilicon film 5 on an N type well region 2 is covered with a resist film 6 so as to be implanted with phosphorus ions 7 using the resist films 6 as a mask. Next, the polysilicon film 5 on the N type well region 2 is implanted with boron ions 9 using the thick oxide films 8 as masks. Finally, after removing the whole surface of the oxide films 8, 8a, the polysilicon film 5 is patterned to form gate electrodes 10, 11.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a CMOS semiconductor device, and more particularly to a method for manufacturing a semiconductor device characterized by the step of forming a polysilicon gate electrode.

0002

[Prior Art] In a CMOS semiconductor device, impurities are introduced into a polysilicon gate electrode to lower the resistance.
In order to prevent punch-through of the N-channel MOS transistor (hereinafter referred to as an NMOS transistor), N-type impurities are introduced into the polysilicon gate electrode of the N-channel region that forms the N-channel MOS transistor (hereinafter referred to as the NMOS transistor), thereby forming a P-channel MOS transistor. P-type impurities are introduced into the polysilicon gate electrode in the P channel region.

One method of introducing impurity ions of the same conductivity type as the channel type into the polysilicon gate electrode is to simultaneously implant impurity ions into the polysilicon gate electrode when ions are implanted to form the source and drain.

However, if impurity ions are implanted into the polysilicon gate electrode at the same time as forming the source and drain, the impurity concentration (implantation amount) of the polysilicon gate electrode is determined by the amount of impurity implanted into the source and drain, which is determined by the transistor characteristics. be done. The amount of impurity implanted into the source/drain is approximately 1×10 15 to 5×10 15 /cm 2 . With such an implantation amount, the polysilicon gate electrode becomes highly resistive. Therefore, in order to lower the resistance of the polysilicon gate electrode, an additional step is required to lower the resistance, such as siliciding the polysilicon gate electrode to lower the resistance, resulting in an increase in the number of steps.

In order to lower the resistance by introducing sufficient impurities into the polysilicon gate electrode, an ion implantation process separate from the source/drain formation process is required, and the N-channel There is also a method of introducing impurities into the polysilicon film in separate steps for the region and the P channel region.

[0006]

[Problems to be Solved by the Invention] In the method of separately implanting N-type impurities and P-type impurities into a polysilicon film before patterning, a resist pattern must be formed to separate the implanted ion species. Therefore, two photolithography steps are required.

[0007] Furthermore, when an impurity ion implantation region is formed by two photolithography processes, a photolithography process is performed to form a resist pattern for implanting N-type impurities, and a resist pattern for implanting P-type impurities is formed. If a misalignment occurs between the photolithography and the polysilicon gate electrode, there will be a region where impurity ions are not implanted near the boundary between the N-type region and the P-type region, resulting in a high-speed signal. This poses a major obstacle to propagation.

[0008] The present invention provides a method for adding N-type impurities and P-type impurities to a polysilicon film at a sufficient concentration in a process separate from the source/drain forming process, and also solves the above-mentioned problem regarding signal propagation speed caused by misalignment. The purpose is to provide a method that does not require

[0009]

[Means for Solving the Problems] The present invention provides steps (A) to (F) for forming a polysilicon gate electrode.
). (A) Step of forming a polysilicon film on the entire surface of the semiconductor wafer which has been completed up to the step of forming gate oxide film, (B) Photolithography step of forming a resist pattern to expose the first conductive channel type element formation region, (C)
an ion implantation step of implanting a first conductivity type impurity into the exposed polysilicon film using the resist pattern as a mask;
(D) After removing the resist pattern, heat treatment is performed in an oxidizing atmosphere to form a thick oxide film in the impurity ion implanted region of the polysilicon film and a thinner oxide film in the impurity ion non-implanted region. Step (E) A second step in which a thin oxide film is formed using the thick oxide film as a mask.
Ion implantation step of implanting a second conductivity type impurity into the polysilicon film in the conductive channel type element formation region, (F) After removing the oxide film on the polysilicon film, a polysilicon gate electrode is formed by photolithography and etching. Process.

0010

[Embodiment] An embodiment will be explained with reference to FIG. (A) After an N-type well 2 is formed in a P-type silicon substrate 1 by a conventional method, a field oxide film 3 is formed by a LOCOS method or the like to perform element isolation.

Next, a gate oxide film 4 is formed, ions are implanted to control the threshold voltage, and a polysilicon film 5 is formed on the entire surface with a thickness of 3,000 to 5,000 by CVD.
Deposit to a thickness of Å.

(B) A photoresist film 6 is formed on the polysilicon film 5 and patterned by photolithography.
Polysilicon film 5 on N-type well 2 is covered with photoresist film 6.

Using this photoresist film 6 as a mask, N-type impurity ions 7 such as phosphorus are implanted. The dose at this time is on the order of 1.times.10.sup.16/cm.sup.2, and the implantation energy is set to such a level that the impurity does not reach the substrate. The area where the photoresist film 6 is not formed is N.
This is an N-channel region where a MOS transistor is formed, and by this ion implantation, N-type impurities are implanted into the polysilicon film 5 in the N-channel region.

(C) After removing the photoresist film 6,
Driving is performed by performing heat treatment at about 920° C. for 30 to 60 minutes in an oxygen atmosphere. As a result, the polysilicon film 5 on the side into which the impurities have been implanted is oxidized at an increased rate of 1000~
An oxide film 8 with a thickness of 2000 Å is formed, while a polysilicon film 5 with a thickness of 150 to 250 Å is formed on the side where impurities are not implanted.
A relatively thin oxide film 8a is formed.

In this state, P-type impurity ions 9 such as boron are implanted. The dose amount at this time is 1×1016/
The implantation energy is set to be on the order of cm2, so that the implanted impurity does not pass through the thick oxide film 8, but reaches the polysilicon film 5 through the thin oxide film 8a, and does not penetrate into the substrate. As a result, P-type impurities are implanted into the polysilicon film 5 on the N-type well 2, that is, the polysilicon film 5 in the P channel region where the PMOS transistor is formed.

(D) After performing a heat treatment at 920° C. for about 30 minutes and driving, the oxide films 8 and 8a on the polysilicon film are completely removed. Thereafter, the polysilicon film is patterned by photolithography and etching according to the usual process, and gate electrodes 10 and 11 are formed. As a result, an N-type impurity set at a desired concentration is introduced into the gate electrode 10 in the N-channel region, and a P-type impurity set at a desired concentration is introduced into the gate electrode 11 in the P-channel region.

[0017] After that, according to the usual method, sources and drains are formed, an interlayer insulating film is formed, contact holes are formed, metal wiring is formed, a passivation film is formed, and multilayer wiring is further formed. CMOS
Complete the semiconductor device.

[0018] As an example, the present invention will be described with reference to a P-type substrate-N.
Although an example is shown in which the present invention is applied to a type well CMOS semiconductor device, the present invention can also be applied to N-type substrate-P-type well, P-type substrate-twin tub, and N-type substrate-twin tub CMOS semiconductor devices. .

[0019]

Effects of the Invention In the present invention, since P-type impurities and N-type impurities are implanted into the polysilicon film before patterning the polysilicon gate electrode, the impurity concentration profile and implantation amount can be changed between the source/drain and the polysilicon gate electrode. (concentration)
can be controlled independently, eliminating the need for a step of forming polycide to lower the resistance of the polysilicon gate electrode, and making it easier to manufacture high-performance CMOS.

Furthermore, when implanting P-type impurities and N-type impurities into a polysilicon film, the polysilicon film in one impurity implanted region is oxidized at an accelerated rate to form a thick oxide film, and the thick oxide film is then transferred to the other region. Since it is used as a mask during impurity implantation, impurity implantation can be performed in self-alignment, improving alignment accuracy and creating CMOS with fine gate length.
It is possible to improve performance by increasing the signal propagation speed.

Furthermore, since photolithography for implanting impurities into the polysilicon film only needs to be performed once, the number of steps can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view showing an example.

[Explanation of symbols]

1 P-type silicon substrate 2 N type well 4 Gate oxide film 5 Polysilicon film 6 Photoresist 7 Phosphorus ion 8 Thick oxide film 8a Thin oxide film 9 Boron ion

Claims (1)

[Claims] Claim 1: A CMO comprising a method for forming a polysilicon gate electrode, including the following steps (A) to (F):
S semiconductor device manufacturing method. (A) Step of forming a polysilicon film on the entire surface of the semiconductor wafer that has been completed up to the gate oxide film forming step, (B) First
a photolithography process of forming a resist pattern that exposes a conductive channel type element forming region; (C) an ion implantation process of implanting a first conductivity type impurity into the exposed polysilicon film using the resist pattern as a mask; (D) the resist. After removing the pattern, an oxidation process is performed in which heat treatment is performed in an oxidizing atmosphere to form a thick oxide film in the impurity ion implanted region of the polysilicon film and a thinner oxide film in the impurity ion non-implanted region, (E) A second layer on which a thin oxide film is formed using the thick oxide film as a mask.
Ion implantation step of implanting second conductivity type impurities into the polysilicon film in the conductive channel type element formation region, (F) After removing the oxide film on the polysilicon film, forming a polysilicon gate electrode by photolithography and etching. Process.