JPS6032354A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To accelerate the speed of a C-MOS by forming a polycrystalline silicon layer of gate electrode in reverse conductive type to the conductive type of the opposed channel region, thereby performing an enhancement type MOS transistor. CONSTITUTION:A P type buried channel region 8, in which boron ions are implanted to the surface of an N type silicon substrate 6, is provided, while an N type buried channel region 9, in which arsenic ions are implanted to the surface of a P-well 7 is provided. Gate electrodes are respectively formed on both channel regions 8, 9 through a gate insulating film 3. A double layer formed of phosphorus-doped N type polycrystalline silicon layer 2 and a tungsten layer 10 are formed on the gate electrodes on the region 8. On the other hand, a gate electrode formed of a boron-doped P type polycrystalline silicon film 1 and a tungsten layer 10 is formed on the region 9. The source, and drain regions 4, 5 of both MOS transistors are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to the structure of a complementary insulated gate field effect semiconductor device (hereinafter abbreviated as OMO3).

Conventional configuration and its problems 0MO3 has a circuit configuration in which a pair of N-channel type and P-channel type insulated gate field effect transistors are connected in a complementary manner. As shown in the main cross-sectional view, it consists of two insulated gate field effect transistors. A polycrystalline silicon layer is used for the gate electrode, and in this case, impurities of the same conductivity type as the source and drain regions are introduced into the polycrystalline silicon layer during the process of forming the source and drain regions using a self-alignment method. . That is, in FIG. 1, P-channel type MO3)
The transistor has a gate electrode of a P-type polycrystalline silicon layer 1, while the N-channel type MOS transistor has a gate electrode of a Nu polycrystalline silicon layer 2. Note that each transistor section has a gate insulating film 3 interposed therebetween.
The structure is such that a source/drain region 4 made of a P-type diffusion layer and a source/drain region 6 made of an N-type diffusion layer are provided in each region of an N-type silicon substrate 6 and a P-type well 7.

However, according to such a combination of gate electrode materials, the work function difference φMS between the gate electrode and the substrate silicon is
This results in a large positive value in the case of a P-channel MO3) transistor, while it results in a large negative value in the case of an N-channel MO8) transistor.

This is a disadvantage for the enhancement type MO3 desired for each transistor in 0MO8. In particular, MOS transistors with a buried channel structure are used to increase the speed of MoS transistors.
To realize the enhancement type, φMS needs to be negative for P-channel MOS transistors and positive for N-channel MOS transistors, and the above combination of gate electrode materials is satisfactory for 0MO8. isn't it.

OBJECTS OF THE INVENTION The main purpose of the present invention is to provide a combination of a gate electrode and a substrate semiconductor suitable for 0MO8, or a gate electrode structure thereof, and thereby realize high-speed operation of 0MO3.

Structure of the Invention To summarize, the present invention includes a pair of insulated gate field effect transistors of a P-channel type and an N-channel type on a single semiconductor substrate, and both of the field effect transistors have the following features:
Each of the semiconductor integrated circuits has a buried channel region of a corresponding conductivity type, and each gate electrode is formed of a polycrystalline silicon layer of an opposite conductivity type to the buried channel region. The work function difference φMS with the channel region of the transistor can be made negative on the side of the P-channel MO8) transistor and positive on the side of the N-channel MO3) transistor to ensure that both field-effect transistors are of the enhancement type. In addition, a buried channel region is applied to 0MO3 to
8 high speed operation can be achieved.

DESCRIPTION OF EMBODIMENTS FIG. 2 is a cross-sectional view of a main part of an apparatus according to an embodiment of the present invention.
Approximately 5×11015 was added to the surface by ion implantation.
P-type buried channel region 8 into which boron of burning degree A is introduced
On the other hand, on the surface of the P-type well 7 with an impurity concentration of about 1×1016/cJ, about 2
×1016/cn? It has an N-type buried channel region 9 into which arsenic is introduced at a concentration of . Also, the thickness is about 50 nm
A gate electrode is provided on both the child regions 8 and 9 through a gate insulating film 3 made of a silicon dioxide film. N-type polycrystalline 29 heavily doped with phosphorus
A double layer consisting of the 37 layer 2 and the tungsten layer 10 is formed, and on the other hand, on the N type buried channel region 9, a gate electrode consisting of the P type polycrystalline silicon layer doped with boron at a high concentration and the tungsten layer 10 is formed. is forming. The sources and regions 4 and 6 of both MOS transistors are respectively formed by implanting boron and arsenic using the cell alignment method using each gate electrode as a mask. Note that the tungsten layer 10 on the polycrystalline silicon layers 1 and 2 forming the gate electrodes
can be selectively grown only on the polycrystalline silicon layer by, for example, a CVD method under reduced pressure using a mixed gas of tungsten hexafluoride (WF6) and hydrogen (H2).

The tungsten layer 1o may be obtained not only by such selective growth method but also by general CVD. Furthermore, this tungsten (ILO) is compatible with metals with similar performance, such as molybdenum and tantalum.

It is possible to select from a group of high melting point metals such as titanium and platinum, as well as metal silicon compounds thereof.

According to the structure of the embodiment of the present invention, the work function difference φMS between the D-type polycrystalline silicon No. 2 and the P-type buried channel region 8 is
has a negative value, and on the other hand, the work function difference φMS between the P-type subcrystalline silicon layer 1 and the N-type buried channel region 9 has a positive value. Therefore, in these cases, both MOS transistors are of the enhancement type, and stable 0MO3 characteristics can be obtained. In addition, in a buried channel structure MOS transistor, unlike a normal surface channel structure, there is no scattering of carriers at the silicon-silicon dioxide film interface, so its 5 inductance increases significantly. 1VIO3) Transistors have lower transconductance (,!9m) in the saturation region than surface channel type ones of the same dimensions.
The value will be about 20-40% higher. This means 0MO3
Suitable for high-speed operation.

Furthermore, by providing a metal layer or a metal silicon compound layer covering the polycrystalline silicon layer as a gate electrode, the polycrystalline silicon layer has an opposite conductivity type during the process of forming the source and drain regions using the self-alignment method. It is possible to prevent impurities from being toped and reliably suppress fluctuations in the threshold voltage of the MOS transistor. In addition, although a gate electrode with a two-layer structure of a polycrystalline silicon layer and a metal layer or a metal silicon compound layer has a sufficiently low sheet resistance value by itself, the introduction of reverse conductivity type impurities is suppressed. However, no increase in the sheet resistance layer was observed,
Stable gate characteristics are maintained.

Effects of the Invention According to the present invention, in both P-channel type and N-channel type MOS transistors, the polycrystalline silicon layer of the gate electrode has a conductivity type opposite to that of its opposing channel region. By this, a reliable enhancement type MOS transistor is realized, and by configuring a CMOS, a stable 0MO8 characteristic can be obtained.

In particular, since the gate electrode structure according to the present invention can reliably achieve enhancement type MO3 characteristics even in a MOS transistor with a buried channel structure, it is possible to easily obtain an 0MO8 configuration using a MOS transistor with the same channel structure, thereby increasing the speed of 0MO3. It is useful for

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of a conventional device, and FIG. 2 is a sectional view of a main part of a device according to an embodiment of the present invention. 1...P-type child crystal silicon layer, 2...N
type polycrystalline silicon layer, 3... gate insulating film, 4...
... Source, drain P-type m region, 5 ... Source, train N-type region, 6 ... N-type silicon substrate, 7 ... P-type f) x) 8... P-type buried channel region, 9... N-type buried channel region, 1o... tungsten layer.

Claims (3)

[Claims] (1) A pair of insulated gate field effect transistors of a P-channel type and an N-channel type are provided on a jll-semiconductor substrate, and both of the field-effect transistors each have a
A semiconductor integrated circuit having a channel region of a corresponding conductivity type, and each gate electrode formed of a polycrystalline silicon layer of a conductivity type opposite to that of the channel region. (2) The semiconductor integrated circuit according to claim 1, wherein each gate electrode is a polycrystalline silicon layer covered with a metal layer or a metal silicon compound layer. (3) The semiconductor integrated circuit according to claim 1, wherein the channel region has a buried channel structure.