JPH02137270A - Dual gate mos field effect transistor - Google Patents
Dual gate mos field effect transistorInfo
- Publication number
- JPH02137270A JPH02137270A JP63291316A JP29131688A JPH02137270A JP H02137270 A JPH02137270 A JP H02137270A JP 63291316 A JP63291316 A JP 63291316A JP 29131688 A JP29131688 A JP 29131688A JP H02137270 A JPH02137270 A JP H02137270A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- effect transistor
- field effect
- mos field
- channel region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title description 5
- 230000009977 dual effect Effects 0.000 title description 3
- 239000012535 impurity Substances 0.000 claims abstract description 3
- 230000037431 insertion Effects 0.000 abstract 1
- 238000003780 insertion Methods 0.000 abstract 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はデュアルゲートＭＯＳ電界効果トランジスタに
関し、特に低電圧動作に適したゲート構造を有するデュ
アルゲー）−ＭＯ３電界効果トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dual-gate MOS field effect transistor, and more particularly to a dual-gate MOS field effect transistor having a gate structure suitable for low voltage operation.
従来、デュアルゲートＭＯＳ電解効果トランジスタ（以
下デュアルゲートＭＯ３ＦＥＴと記す）は、第１ゲート
及び第２ゲート共にゲート酸化膜厚、チャネル濃度は同
一であった。Conventionally, in a dual-gate MOS field effect transistor (hereinafter referred to as dual-gate MO3FET), both the first gate and the second gate have the same gate oxide film thickness and the same channel concentration.
上述した従来のデュアルゲートＭＯＳＦＥＴでは、第１
ゲート及び第２ゲートが両方ともデプレッションモード
あるいは両方ともエンハンスメントモードであった。In the conventional dual gate MOSFET described above, the first
The gate and the second gate were both in depletion mode or both in enhancement mode.
両方ともデプレッションモードであると、第２ゲートに
ＡＧＣ電圧を印加してカットオフするときにソースに対
し負の電圧を印加する必要があり、実際にはセルフバイ
アス方式、すなわちカットオフに必要な負の電圧分を得
るため、ソースに抵抗を入れる必要があった。このため
、ソースに入れた抵抗による電圧降下分だけ余分なドレ
イン印加電圧を必要とし、低電圧動作化が妨げられてい
た。If both are in depletion mode, it is necessary to apply a negative voltage to the source when applying the AGC voltage to the second gate to cut off. In order to obtain this voltage, it was necessary to insert a resistor into the source. Therefore, an extra voltage applied to the drain is required to compensate for the voltage drop caused by the resistor inserted in the source, which hinders low-voltage operation.
また、両方ともエンハンスメントモードであると、低電
圧動作は可能であるが、第１ゲートが常にカットオフ状
態であり、導通させるために正にバイアスする必要があ
った。また、動作点がカットオフに近いなめ、シャープ
カットオフになり、線形性が損われ、歪の増加をもたら
すという問題があった。Furthermore, when both are in enhancement mode, low voltage operation is possible, but the first gate is always in a cutoff state and needs to be biased positively in order to conduct. Further, there is a problem in that the operating point is near the cutoff or sharp cutoff, resulting in loss of linearity and increased distortion.
本発明のデュアルゲートＭＯ３電界効果トランジスタは
、リモートカットオフのデプレッションモードの第１ゲ
ートと、前記第１ゲートのゲート絶縁膜よりも厚い膜厚
の第２ゲート絶縁膜と前記第１ゲートのチャネル領域よ
りも高い不純物濃度の第２ゲートチャネル領域とを有し
エンハンスメントモードの第２ゲートとを含んで構成さ
れる。The dual-gate MO3 field effect transistor of the present invention includes a remote cut-off depletion mode first gate, a second gate insulating film thicker than a gate insulating film of the first gate, and a channel region of the first gate. a second gate channel region having an impurity concentration higher than that of the second gate channel region, and a second gate in an enhancement mode.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.
１は比抵抗１０Ω・ｃｍのＰ型シリコン基板、２．４及
び６はＮ型高濃度（Ｎ＋）拡散層であり、それぞれソー
スアイランド、ドレイン領域となっている。３及び５は
チャンネル領域で、それぞれ第１ゲート、第２ゲートの
チャンネル領域である。 この実施例では、第１ゲート
側をホウ素をドーズ量２Ｘ１０１１ｃｍ””、加速エネ
ルギー２５ｋｅＶでイオン注入し、第２ゲート側をホウ
素をドーズ量４×１０１１ｃｍ−２、加速エネルギー
２５ ｋ ｅ Ｖでイオン注入して形成する。また、１
２．１４はそれぞれ第１ゲート酸化膜、第２ゲート酸化
膜であり、第１ゲート酸化膜１２の厚さは、７０ｎｍ、
第２ゲート酸化膜の厚さは４９ｎｍである。第２図（ａ
）、（ｂ）は本発明の一実施例のＶ。−ＩＤ特性図であ
り、（ａ）図は第１ゲート側、（ｂ）図は第２ゲート側
の特性を示す。 第２図に示されるように、第１ゲート
側のＦＥＴ特性はリモートカットオフ特性をもち、デプ
レッションモードとなり、第２ゲート側のＦＥＴ特性は
エンハンスメント型となる。さらに、第２ゲート側のゲ
ート酸化膜厚を薄くしであるので第２ゲート側の相互コ
ンダクタンスが高くなり、ＡＧＣ特性も良好となる。1 is a P-type silicon substrate with a specific resistance of 10 Ω·cm, and 2.4 and 6 are N-type high concentration (N+) diffusion layers, which serve as a source island and a drain region, respectively. 3 and 5 are channel regions, which are the channel regions of the first gate and the second gate, respectively. In this example, boron is ion-implanted on the first gate side at a dose of 2 x 1011 cm and an acceleration energy of 25 keV, and on the second gate side, boron is ion-implanted at a dose of 4 x 1011 cm and an acceleration energy of 25 keV.
It is formed by ion implantation at 25 keV. Also, 1
2.14 are a first gate oxide film and a second gate oxide film, respectively, and the thickness of the first gate oxide film 12 is 70 nm,
The thickness of the second gate oxide film is 49 nm. Figure 2 (a
) and (b) are V of one embodiment of the present invention. -ID characteristic diagrams, in which the (a) figure shows the characteristics on the first gate side, and the (b) figure shows the characteristics on the second gate side. As shown in FIG. 2, the FET characteristics on the first gate side have remote cutoff characteristics and are in depletion mode, and the FET characteristics on the second gate side are enhancement type. Furthermore, since the thickness of the gate oxide film on the second gate side is made thinner, the mutual conductance on the second gate side is increased, and the AGC characteristics are also improved.
以上説明したように、本発明は、第１ゲート側をリモー
トカットオフデプレッションモード、第２ゲート側をエ
ンハンスメントモードにすることにより、第２ゲートの
セルフバイアス用ソース抵抗が不要となり、低電圧動作
が可能となり、また第１ゲートがノーマリ−オンとなり
リモートカットオフ特性をもつことがら歪特性の良いデ
ュアルゲートＭＯ３ＦＥＴが得られるという効果がある
。As explained above, in the present invention, by setting the first gate side to the remote cutoff depression mode and the second gate side to the enhancement mode, the self-biasing source resistor of the second gate is unnecessary and low voltage operation is possible. Furthermore, since the first gate is normally on and has remote cutoff characteristics, it is possible to obtain a dual gate MO3FET with good distortion characteristics.
−スミ極、１２・・・第１ゲート酸化膜、１３・・・第
１ゲート電極、１４・・・第２ゲート酸化膜、１５・・
・第２ゲート電極、１６・・・ドレイン電極。- Sumir pole, 12... first gate oxide film, 13... first gate electrode, 14... second gate oxide film, 15...
- Second gate electrode, 16... drain electrode.
第１図は本発明の一実施例を示す断面図、第２図（ａ）
、（ｂ）は本発明の一実施例のＶＢ２−ＩＤを示す特性
図である。Figure 1 is a sectional view showing one embodiment of the present invention, Figure 2 (a)
, (b) are characteristic diagrams showing VB2-ID of an embodiment of the present invention.
Claims (1)
トと、前記第１ゲートのゲート絶縁膜よりも厚い膜厚の
第２ゲート絶縁膜と前記第１ゲートのチャネル領域より
も高い不純物濃度の第２ゲートチャネル領域とを有しエ
ンハンスメントモードの第２ゲートとを有することを特
徴とするデュアルゲートＭＯＳ電界効果トランジスタ。a first gate in depletion mode of remote cutoff, a second gate insulating film thicker than the gate insulating film of the first gate, and a second gate channel region having a higher impurity concentration than the channel region of the first gate. and a second gate in an enhancement mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63291316A JPH0770723B2 (en) | 1988-11-17 | 1988-11-17 | Dual gate MOS field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63291316A JPH0770723B2 (en) | 1988-11-17 | 1988-11-17 | Dual gate MOS field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02137270A true JPH02137270A (en) | 1990-05-25 |
| JPH0770723B2 JPH0770723B2 (en) | 1995-07-31 |
Family
ID=17767325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63291316A Expired - Lifetime JPH0770723B2 (en) | 1988-11-17 | 1988-11-17 | Dual gate MOS field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0770723B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004253541A (en) * | 2003-02-19 | 2004-09-09 | Ricoh Co Ltd | Semiconductor device |
| JP2020043264A (en) * | 2018-09-12 | 2020-03-19 | 株式会社東芝 | Semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5127074A (en) * | 1974-08-20 | 1976-03-06 | Matsushita Electronics Corp | Zetsuengeetogatadenkaikokahandotaisochino seizohoho |
| JPS567479A (en) * | 1979-06-29 | 1981-01-26 | Toshiba Corp | Field-effect type semiconductor device |
-
1988
- 1988-11-17 JP JP63291316A patent/JPH0770723B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5127074A (en) * | 1974-08-20 | 1976-03-06 | Matsushita Electronics Corp | Zetsuengeetogatadenkaikokahandotaisochino seizohoho |
| JPS567479A (en) * | 1979-06-29 | 1981-01-26 | Toshiba Corp | Field-effect type semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004253541A (en) * | 2003-02-19 | 2004-09-09 | Ricoh Co Ltd | Semiconductor device |
| JP2020043264A (en) * | 2018-09-12 | 2020-03-19 | 株式会社東芝 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0770723B2 (en) | 1995-07-31 |
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