JPH05211331A - Misfet device and manufacturing method thereof - Google Patents

Abstract

PURPOSE:To shallowly distribute the impurity for threshold value adjustment by a method wherein gallium in specific concentration is contained in the part near substrate surface in a channel formation region. CONSTITUTION:Within the title MISFET formed on one main surface of a single crystal silicon substrate 101, gallium in the peak concentration of not exceeding 1X10<18>cm<-3> is contained in the part near substrate surface to be distributed notably shallower than boron. For example, an element separating silicon oxide 102 is formed on a single crystal silicon substrate 101 in the peak concentration of about 1X10<15>cm<-3>. Next, the silicon oxide 102 is implanted with baron ions in the dose of about 1X10<12>cm<-2> at 60KeV to be further implanted with gallium ions larger in mass numbers than boron in the dose of about 5X10<12>cm<-2> at 80KeV. Through these procedures, the impurities are distributed as follows, i.e., the shallow peak 103 by galluim will be about 0.05mum from the substrate surface while the deep peak 104 by boron will be about 0.2mum from the same.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a MIS type FET device and a manufacturing method thereof, and more particularly to a MIS type FE.
It relates to the channel region of the T device.

[0002]

2. Description of the Related Art Conventionally, for example, a surface channel type n channel M
IS type FET device, as shown in FIG. 7, boron concentration 1 ×
A silicon oxide 102 for element isolation is formed on a single crystal silicon substrate 101 of about 10 ¹⁵ cm ⁻³ by a well-known prior art selective oxidation method or the like, and boron is dosed at 60 eV and a dose of 1 × 10 ^{12 is obtained.}
When ion implantation is performed at about cm ^{−2 and} boron is ion-implanted at about 5 × 10 ¹² cm ⁻² at 15 KeV, the impurity distribution is as shown in FIG. 8 with a shallow peak 103 being about 0.05 μm from the substrate surface and a deep peak. 104 comes to a place of about 0.2 μm. The deep peak 104 is mainly formed to prevent punch-through between the source and the drain, and the shallow peak 103 is mainly formed to adjust the threshold voltage. After that, as shown in FIG. 9, a gate insulating film 105, a gate electrode 106, and an n-type source and drain impurity diffusion layer 107 are formed to obtain a MIS-type FET.

Next, in the case of the buried channel type P channel MIS type FET, the phosphorus concentration is 1 as shown in FIG.
Silicon oxide 102 for element isolation is formed on a single crystal silicon substrate 101 of about 1015 cm-3, and phosphorous is added to 200 K, for example.
Ion implantation is performed at eV at a dose of about 1 × 10 ¹² cm ⁻² , and then boron is ion implanted at 10 KeV at a dose of about 1 × 10 ¹² cm ⁻² . At this time, the impurity distribution is such that a P-type region 108 of boron is formed near the surface as shown in FIG. 11, and a pn junction 109 is formed between the substrate and the substrate by 0.06 μm from the substrate.
It can be placed at about m. In the buried channel type MISFET device, the gate electrode is made of polycrystalline silicon of the same type as the substrate, and the P-type region 108 is depleted due to the difference in work function to bring it into a cutoff state. In the buried channel type MIS FET, a channel starts to be formed from the pn junction 109 when the cutoff state is changed to the conductive state.
To miniaturize the IS type FET device, this pn junction 10
It is important to make 9 shallow, that is, make the P-type region 108 shallow.

[0004]

However, this conventional boron structure has the drawback that the transistor cannot be miniaturized in the same structure as the threshold adjustment. The reason is that since boron has a small mass number, it is necessary to reduce the implantation energy in order to form a shallow implantation layer.
The limit is about 0 to 15 KeV.

[0005]

Means for Solving the Problems MIS FET of the present invention
The device is a MIS formed on one main surface of a single crystal silicon substrate.
The FET is characterized by including gallium or indium having a peak concentration of 1 × 10 ¹⁸ cm ⁻³ or less near the surface of the substrate in the channel formation region. The manufacturing method is characterized in that the gallium or indium is selectively implanted into the channel formation region by an ion implantation method. Here, if the peak concentration of gallium or indium is higher than 1 × 10 ¹⁸ cm ⁻³ , as a practical matter, the cutoff of the FET becomes difficult, and it becomes difficult to manufacture the enhancement FET.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The MIS type FET of the present invention will be described below with reference to the drawings.
The device will be described in detail including the manufacturing method thereof.

As a first embodiment, as shown in FIG. 1, for example, a silicon oxide for element isolation is formed on a single crystal silicon substrate 101 having a boron concentration of about 1 × 10 ¹⁵ cm ^-3 by a well-known selective oxidation method or the like. 102 is formed. Next, boron is ion-implanted at a dose of 1 × 10 ¹² cm ^{-2 at} 60 KeV, and then gallium having a mass number larger than boron is 5 × 10 at 80 KeV.
^When ion implantation is performed at about ¹² cm ⁻² , the impurity distribution is such that the shallow peak 103 due to gallium is approximately 0.05 μm from the substrate surface and the deep peak 104 due to boron is approximately 0.2 μm as shown in FIG. The distribution is similar to that shown in FIG. 11 described in the related art. Of course, even if boron is ion-implanted at 15 KeV instead of gallium, a similar distribution can be obtained, but even if the distribution is made shallower,
When using boron, the limit is about 10 KeV,
Gallium has a much shallower distribution than boron.

After that, the gate insulating film 105, the gate electrode 106, the source / drain impurity diffusion 107, etc. are formed as shown in FIG.
Get an ET device.

Although gallium is ion-implanted in the above description, the same applies to indium having a mass number larger than boron, only by adjusting the implantation energy.
Moreover, not only a single transistor but also CMOS or B
It goes without saying that it is also applicable to iCMOS and the like.

Further, during ion implantation, it is possible to apply the invention within a range not departing from the gist of the present invention, such as providing a protective oxide film on the surface of the substrate.

Next, as a second embodiment of the present invention, a case of a buried channel type P channel MIS type FET will be described.

As shown in FIG. 4, the phosphorus concentration is about 1 × 10.
^A silicon oxide 102 for element isolation is formed on an n-type single crystal silicon substrate 101 of about ¹⁵ cm ⁻³ by a selective oxidation method. For example, phosphorus is ion-implanted at 200 KeV and a dose of 1 × 10 ¹² cm ^−2. Gallium at 10 KeV at 1 × 10 ¹² cm ^-2
About ion implantation.

The impurity distribution at this time is as shown in FIG.
The PN junction 109 between the P-type region 108 made of gallium and the substrate is located 0.02 μm from the substrate surface. When boron is ion-implanted at 10 KeV, PN is obtained from Fig. 11.
Since the junction depth is 0.06 μm, the depth can be about 1/3. The use of gallium is a great advantage because it is necessary to reduce the depth of the PN junction in order to reduce the size of the buried channel transistor.

Thereafter, as shown in FIG. 6, similarly to the first embodiment, a gate insulating film 105, a gate electrode 106, and an impurity diffusion layer 107 for source and drain are formed, and the M of the present invention is formed.
Obtain an IS type FET.

[0015]

As described above, the present invention has the effect of making the distribution of the impurities for adjusting the threshold shallow and miniaturizing the MIS type FET.

[Brief description of drawings]

FIG. 1 is a sectional view showing a single crystal silicon substrate according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an impurity distribution in the first embodiment of the present invention.

FIG. 3 is a sectional view showing an outline of a MIS type FET device according to a first embodiment of the present invention.

FIG. 4 is a sectional view showing a single crystal silicon substrate of a second embodiment of the present invention.

FIG. 5 is a diagram showing an impurity distribution in the second embodiment of the present invention.

FIG. 6 is a sectional view showing the outline of a MIS type FET device according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a conventional single crystal silicon substrate.

FIG. 8 is a diagram showing an impurity distribution in a conventional technique.

FIG. 9 is a sectional view schematically showing a conventional MIS type FET device.

FIG. 10 is a diagram showing another conventional single crystal silicon substrate.

FIG. 11 is a diagram showing an impurity distribution in another conventional technique.

[Explanation of symbols]

 Reference Signs List 101 single crystal silicon substrate 102 silicon oxide 103 shallow peak 104 deep peak 105 gate insulating film 106 gate electrode 107 source / drain impurity diffusion layer 108 P-type region 109 pn junction

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 7377-4M H01L 29/78 301 Y

Claims (2)

[Claims] 1. A MIS-type FET formed on one main surface of a single crystal silicon substrate, wherein gallium or indium having a peak concentration of 1 × 10 ¹⁸ cm ⁻³ or less is provided near the surface of the substrate in a channel formation region. MIS characterized by including
Type FET device. 2. The MIS type FE according to claim 1, wherein the gallium or indium is selectively implanted into the channel formation region by an ion implantation method.
T device manufacturing method.