JPS6466962A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6466962A
JPS6466962A JP22464487A JP22464487A JPS6466962A JP S6466962 A JPS6466962 A JP S6466962A JP 22464487 A JP22464487 A JP 22464487A JP 22464487 A JP22464487 A JP 22464487A JP S6466962 A JPS6466962 A JP S6466962A
Authority
JP
Japan
Prior art keywords
region
type
channel mos
transistor
well region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22464487A
Other languages
Japanese (ja)
Inventor
Masaru Oki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP22464487A priority Critical patent/JPS6466962A/en
Publication of JPS6466962A publication Critical patent/JPS6466962A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)
  • Thyristors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the impurity concentration of a well region and make it possible to miniaturize a CMOS transistor while maintaining the characteristics or a bipolar transistor, by implanting ions of impurities for preventing a punch-through of an N channel MOS transistor also into a well region for a base of the bipolar transistor. CONSTITUTION:An N<+>type buried region 2 is formed on a P-type semiconductor substrate 1 and a P-type epitaxial layer 3 is grown on the whole surface. Then, N-type impurities are introduced to form N-type well regions 4A and 4B and an element isolation film 5 is formed. A mask 6 is formed on a region for a P-channel MOS transistor and ions or boron are implanted in the epitaxial layer of a region for an N channel MOS transistor and N-type well region 4B in which 7 bipolar transistor is to be formed. An N<->type region 7 is formed in the region 4B. The impurity concentration is decreased because thc N<-> well region 7 is formed.
JP22464487A 1987-09-07 1987-09-07 Manufacture of semiconductor device Pending JPS6466962A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22464487A JPS6466962A (en) 1987-09-07 1987-09-07 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22464487A JPS6466962A (en) 1987-09-07 1987-09-07 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6466962A true JPS6466962A (en) 1989-03-13

Family

ID=16816947

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22464487A Pending JPS6466962A (en) 1987-09-07 1987-09-07 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6466962A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04239760A (en) * 1991-01-22 1992-08-27 Sharp Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04239760A (en) * 1991-01-22 1992-08-27 Sharp Corp Manufacture of semiconductor device

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