JPS564269A - Bipolar cmos semiconductor device and manufacture thereof - Google Patents

Bipolar cmos semiconductor device and manufacture thereof

Info

Publication number
JPS564269A
JPS564269A JP7920679A JP7920679A JPS564269A JP S564269 A JPS564269 A JP S564269A JP 7920679 A JP7920679 A JP 7920679A JP 7920679 A JP7920679 A JP 7920679A JP S564269 A JPS564269 A JP S564269A
Authority
JP
Japan
Prior art keywords
type
layer
substrate
recesses
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7920679A
Other languages
Japanese (ja)
Inventor
Toshihiro Matsuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7920679A priority Critical patent/JPS564269A/en
Publication of JPS564269A publication Critical patent/JPS564269A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To shorten the diffusing time of a bipolar CMOS semiconductor device by forming two buried epitaxial layers in a semiconductor substrate when forming a bipolar transistor and a CMOS FET on one semiconductor substrate and forming a transistor and one FET in the layers. CONSTITUTION:An anisotropic selective etching is conducted on a p-type Si substrate 4 to form two recesses 5a, 5b having acutely oblique surfaces on the side surfaces, and to epitaxially grow an n-type layer 6 on the entire surface including the recesses 5a, 5b. Then, the layer 6 is chemically or mechanically removed to expose the surface of the substrate 4 and to simultaneously retain the epitaxial layers 6a, 6b in the recesses. Thereafter, the p<+>-type source and drain regions 7, 8 of a p-channel MOS FET are diffused in the layer 6a, and the p<+>-type base region 9 and the n<+>-type collector pickup region 12 of a bipolar transistor are diffused in the layer 6b, and an n<+>-type emitter region 13 is formed in the region 9. Subsequently, the n<+>-type source and drain regions 10, 11 of an n-channel MOS FET are formed on the exposed portion of the substrate 4.
JP7920679A 1979-06-25 1979-06-25 Bipolar cmos semiconductor device and manufacture thereof Pending JPS564269A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7920679A JPS564269A (en) 1979-06-25 1979-06-25 Bipolar cmos semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7920679A JPS564269A (en) 1979-06-25 1979-06-25 Bipolar cmos semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS564269A true JPS564269A (en) 1981-01-17

Family

ID=13683465

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7920679A Pending JPS564269A (en) 1979-06-25 1979-06-25 Bipolar cmos semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS564269A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5885362U (en) * 1981-12-07 1983-06-09 株式会社日立製作所 semiconductor integrated device
JPS58164258A (en) * 1982-03-25 1983-09-29 Toshiba Corp Manufacture of semiconductor device
JPH02134863A (en) * 1988-11-15 1990-05-23 Nec Corp Integrated circuit
JPH05192371A (en) * 1991-09-30 1993-08-03 Hill Rom Co Inc Mattress for birth bed

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5244188A (en) * 1975-10-06 1977-04-06 Hitachi Ltd Semiconductor integrated circuit and process for production of the sam e
JPS5314584A (en) * 1976-07-26 1978-02-09 Hitachi Ltd Forming method for mosic and bipolar ic on one semiconductor substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5244188A (en) * 1975-10-06 1977-04-06 Hitachi Ltd Semiconductor integrated circuit and process for production of the sam e
JPS5314584A (en) * 1976-07-26 1978-02-09 Hitachi Ltd Forming method for mosic and bipolar ic on one semiconductor substrate

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5885362U (en) * 1981-12-07 1983-06-09 株式会社日立製作所 semiconductor integrated device
JPS58164258A (en) * 1982-03-25 1983-09-29 Toshiba Corp Manufacture of semiconductor device
JPH0345549B2 (en) * 1982-03-25 1991-07-11 Tokyo Shibaura Electric Co
JPH02134863A (en) * 1988-11-15 1990-05-23 Nec Corp Integrated circuit
JPH05192371A (en) * 1991-09-30 1993-08-03 Hill Rom Co Inc Mattress for birth bed

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