JPS54150091A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS54150091A
JPS54150091A JP5922778A JP5922778A JPS54150091A JP S54150091 A JPS54150091 A JP S54150091A JP 5922778 A JP5922778 A JP 5922778A JP 5922778 A JP5922778 A JP 5922778A JP S54150091 A JPS54150091 A JP S54150091A
Authority
JP
Japan
Prior art keywords
region
type
regions
diffusion
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5922778A
Other languages
Japanese (ja)
Other versions
JPS6135713B2 (en
Inventor
Toyoki Takemoto
Haruyasu Yamada
Michihiro Inoue
Hideaki Sadamatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP5922778A priority Critical patent/JPS54150091A/en
Publication of JPS54150091A publication Critical patent/JPS54150091A/en
Publication of JPS6135713B2 publication Critical patent/JPS6135713B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Bipolar Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE: To reduce the noise of J-FET as well as to secure a high density by providing the high impurity density region enclosed by the insulator film within the channel region held between the source and gate region.
CONSTITUTION: N+-type buried regions 31a∼31c are formed by diffusion on P-type Si substrate 1, and N-type layer 32 is epitaxial-grown on the entire surface. Then P+-type region 33 is formed by diffusion, and layer 32 is isolated into the island shape. At the same time, P-type well regions 34a and 34c which are to be the gate and resistance region are provided within island region 32 in opposition to regions 31a and 31c each. And P-channel P+-type gate contact region 36 is provided within region 34a, and P+-type base region 35 of the NPN element is formed by diffusion within region 32 opposing to region 31b respectively. After this, N+-type emitter region 37, N+-type source and drain regions 38 and 39, and N+-type contact parts 40 and 41 are provided within region 35, regions 34a and 34c respectively. And P+- type surface region 46 enclosed by SiO2 film 45 is formed within channel 42a produced between regions 38 and 39.
COPYRIGHT: (C)1979,JPO&Japio
JP5922778A 1978-05-17 1978-05-17 Semiconductor device Granted JPS54150091A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5922778A JPS54150091A (en) 1978-05-17 1978-05-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5922778A JPS54150091A (en) 1978-05-17 1978-05-17 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS54150091A true JPS54150091A (en) 1979-11-24
JPS6135713B2 JPS6135713B2 (en) 1986-08-14

Family

ID=13107270

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5922778A Granted JPS54150091A (en) 1978-05-17 1978-05-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS54150091A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5393998A (en) * 1992-07-17 1995-02-28 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device containing junction field effect transistor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5061984A (en) * 1973-10-01 1975-05-27
JPS5124874A (en) * 1974-08-23 1976-02-28 Nippon Telegraph & Telephone SETSUGOGATADENKAIKOKATORANJISUTA

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5061984A (en) * 1973-10-01 1975-05-27
JPS5124874A (en) * 1974-08-23 1976-02-28 Nippon Telegraph & Telephone SETSUGOGATADENKAIKOKATORANJISUTA

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5393998A (en) * 1992-07-17 1995-02-28 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device containing junction field effect transistor

Also Published As

Publication number Publication date
JPS6135713B2 (en) 1986-08-14

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