JPS6135713B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device equipped with a junction field effect transistor, which enables a high-density design of a low-noise junction field effect transistor, and also enables a semiconductor device integrated with a bipolar semiconductor element. It concerns integrated circuits (ICs).

Junction field effect transistor (junction type)
FETs) have characteristics that bipolar elements do not have, such as square-law characteristics, and have come to be used in various fields including audio, and recently integrated circuits (ICs) that incorporate FETs and bipolar elements have been developed. Attempts are being made to integrate these as needed.

One of the objectives is to increase circuit flexibility by introducing FETs, such as reducing cross-modulation due to increased input impedance and reducing the number of components due to low-noise O-bias operation. By integrating the FET into an IC, it is possible to obtain the benefits of reducing the occupied area and cost, as well as reducing noise induced in interconnection parts, etc., compared to using a single FET. I can do it.

Integrated configuration of conventional FET and bipolar element
Only ICs using PCH type FETs existed on the market, and were mainly developed for operational amplifiers. The reason for this is that the nch type is difficult to manufacture and, as will be explained later, has poor noise characteristics.Furthermore, in operational amplifiers that are allowed to use a power supply of This is because it can be used.

By the way, FETs with a normal upper gate structure in which a gate diffusion region is created in the epitaxial growth layer
The channel thickness is determined by the difference between the thickness of the epitaxial layer and the diffusion depth of the gate diffusion region,
Their strict control is required. On the other hand, determining the base width of bipolar transistors in integrated circuits is done by delicately distributing heat treatment time.
Thereby, a desired h _fe (current amplification factor) is obtained. Therefore, delicate control of channel thickness and base width cannot coexist within the heat treatment conditions, and it is extremely difficult to integrate the above-mentioned ordinary FET and bipolar element into an IC.

Therefore, a back gate structure is adopted as an FET integrated into an IC with a bipolar element. 2 shows a conventional pchFET integrated within an integrated circuit with the bipolar device shown in FIG. 1; In other words, in ICs, FETs with a surface channel or back gate structure are used, which enable the formation of a channel region without performing heat treatment that would change the base width of the bipolar transistor, and which provide stable DC characteristics. Ru.

FIG. 1 shows the general structure of this backgate structure, where 1 is a p-type substrate, 2 is a backgate region made of an n-type epitaxial layer of 1 to 3 Ω-cm formed on the p-type substrate 1, Reference numerals 3 and 4 denote source/drain regions made of p-diffusion layers, which are formed simultaneously with the base region (not shown) of the bipolar transistor formed in the n-type epitaxial layer 2.
5 is an n ⁺ diffusion gate contact region. Reference numeral 6 denotes a lightly doped p-type channel region which is formed from the upper surface of the epitaxial layer 2 by ion implantation with good controllability. 7 is a thermal oxide film, and 8 _S , 8 _D , and 8 _G are metal electrodes for the source 3 , drain 4 , and gate 5 , respectively. The operation of this FET is achieved by controlling the conductance of the channel region 6 using the gate region 2. That is, by applying a bias voltage to the gate electrode _8G , the bias voltage is applied from the back surface of the channel region 6, and conductance control is performed. In such a junction FET, the channel region 6 is formed on the top surface, so the depth and concentration of the channel do not strongly depend on the thickness and concentration of the epitaxial layer 2, but are almost exclusively determined by the amount of impurities doped from the top surface. It has the advantage of being determined by the method, and if formed using an ion implantation method or the like, it is possible to form a low resistance channel with very high precision.

However, this device also has significant drawbacks. That is, since the carrier running in the channel region 6 is controlled by the gate bias voltage applied from below the channel region 6, the carrier runs near the surface of the channel region 6 and causes noise.
This is because there are many sources of noise near the interface between the oxide film 7 and the channel region 6, such as charge exchange with the surface level and defects on the surface such as processing strain. In order to eliminate this drawback, methods have been devised to prevent the carrier from flowing onto the surface of the channel region 6.
In other words, the FET shown in Figure 2 as a first example is
By providing 8 voltage application electrodes on the thermal oxide film 7 on the surface of the channel region 6, an electrically inverted region 9 appears on the surface of the channel region 6. / This prevents the carrier from flowing into areas that cause noise. However, in order to form the inversion region 9 in the channel region 6 in this FET, a voltage far exceeding 10 V is generally required, although it depends on the thickness of the thermal oxide film 7, and this is not suitable for ordinary ICs.

As a second example, a method may be considered in which a high resistance layer such as an intrinsic semiconductor (i-layer) is provided on the surface of the channel region 6 so that the surface carrier of the channel region 6 does not flow. In this method, since the impurity concentration of the i-layer itself is low, carriers are likely to move from the channel region 6 to the i-layer, and recombination in the i-layer is performed by these moving carriers, so that noise components on the surface are no longer generated. exist, and no significant reduction can be expected.

In view of such problems, the present inventors considered forming an n layer of a conductivity type opposite to that of the p-type channel region 6 over the entire surface of the channel region 6. However, in this structure, the surface n-layer must have a low concentration in order to prevent a drop in breakdown voltage between the source and drain. This low concentration n-layer is affected by surface recombination noise similar to the above-mentioned i-layer, and the depletion layer at the PN junction at the interface with the channel region 6 spreads between the surface n-layer and the channel region 6. As a result, it is difficult to control the depth of the channel, and the variation in the saturated drain current I _DSS becomes extremely large, which is undesirable. On the other hand, if a high concentration n ⁺ layer is formed on the surface of the surface channel region 6, the influence of surface recombination noise is eliminated, and the depletion layer only extends in the direction of the channel region 6, which has the advantage of making it easier to control the channel depth. However, the withstand voltage between the source 3 and drain 4 becomes low, making it impractical.

The inventors of the present invention further studied these problems and proposed a junction FET with excellent DC characteristics and noise characteristics in Japanese Patent Application No. 102426/1983. Figure 3 shows the structure of the main parts of the junction FET proposed here. That is, in the FET shown in FIG. 4, a high concentration surface impurity doped region of the opposite conductivity type to this region is formed in the surface channel region between the source and drain, separated from the drain.

In FIG. 3, 12 is a p-type back gate region, and within this region 12 is an n-type channel region 13.
are formed, and 14 and 15 are n-type heavily doped source and drain regions. Reference numeral 16 denotes a p-type high-concentration surface impurity doped region, which has the function of blocking the flow of carriers on the surface and preventing noise, and is normally connected to the gate region 12 and also functions as a gate region.
17 is a surface oxide film.

As seen in FIG. 4, it can be seen that the structure shown in FIG. 3 significantly improves the noise characteristics. In FIG. 4, the curve represents a junction FET without a high concentration p-type region 16, and the curve represents a junction FET with a high concentration p-type region 16 selectively installed.
shows the input equivalent noise voltage of As can be seen from the characteristics of FIG. 3, the structure shown in FIG. 3 has almost no problems in terms of noise characteristics, but there are some problems with the structure of this element. In other words, as shown in FIG. 3, a high concentration region 16 of the conductivity type opposite to that of the channel
As mentioned above, in order to obtain a sufficient breakdown voltage between the source 14 and the drain 15, considering the mask alignment accuracy or the distance of penetration by diffusion, the region 16 and the source shown in FIG. At the current state of the art, the minimum distance a or b between the drains is about 4 μm. Similarly, the area 16 needs to be about 4 μm. Therefore, the distance between source and drain is 12
μm, which has two drawbacks.

The first drawback is that high density cannot be achieved. This is not much of a problem in a single device with a small gm, but when a junction FET device with a large gm, such as a comb-shaped junction FET, is manufactured, the long gate length becomes a big problem. The second drawback is that the carrier that has passed under the region 10 may flow again on the surface due to the long distance from the source, and noise current may be generated due to reactions with active layers such as surface states and defects. .

The present invention aims to reduce the above-mentioned drawbacks of the junction FET proposed in Japanese Patent Application No. 102426/1985, enable higher density, and improve noise performance. That is, the present invention is a junction FET disclosed in Japanese Patent Application No. 52-102426, which is characterized in that an insulator region is formed between the high-wavelength surface region that blocks the flow of carriers on the surface, the source, and the drain. . Note that the insulator region in the present invention may be formed between both the source and the drain, or may be formed between one of them.

FIG. 5 shows an n-channel system based on the present invention.
A method of manufacturing an IC according to an embodiment of the present invention in which an FET and a bipolar element are integrally formed will be shown, and the present invention will be explained accordingly.

Figure 5 a is p-type, 111 plane index, 1 to 10 Ω-cm
n ⁺ buried diffusion layers 31a, 31b, formed of As or Sb on the surface of the silicon wafer substrate 1.
31c is shown.

Thereafter, epitaxial growth using SiCl ₄ is performed on the substrate 1 to form an n-type epitaxial layer 32 with a specific resistance of 0.5 to 3 Ω-cm, and diffusion is performed from a source made of BBr ₃ or Bcl ₃ . A p ⁺ type isolation diffusion layer 33 is formed to separate layer 32 into island regions. When forming this layer 33, a high concentration impurity is first diffused into the formation portion of the layer 33, and then the impurity is further deeply diffused by heat treatment. This deeper diffusion will result in the same process.
Island-shaped p-well regions 34a and 34c are formed to serve as a back gate region of the FET and a region for forming a resistor. That is, the p-wells 34a and 34c are formed by selective doping by conventional thermal diffusion or ion implantation followed by the above-mentioned heat treatment, and have a specific resistance of 0.5 to several Ω-cm and a width of about 5 μm.

Next, a boron source such as BBr3, _Bcl3 , _B2O3 is selectively diffused onto the p-well 34a and the epitaxial layer 32 to form a p ⁺ type base region 35 of _the npn transistor and a low-resistance layer of the nchFET. Forming the p ⁺ type gate contact portion 36 at the same timec.

After that, an n ⁺ type emitter region 3 is formed in the base region 35 from a phosphorus p source such as POcl ₃ or P ₂ O ₅ .
7. N ⁺ type source in the p-well 34a of the FET,
N ⁺ type contact portions 40 and 41 of the resistance region are provided in the drain regions 38 and 39 and the p-well 34c with a thickness of 1.3 to 2.0.
Selectively formed to a depth of μm. During this spread,
A method is used in which high-concentration phosphorus (P) is diffused shallowly in advance and then heat-treated at a predetermined temperature. After this shallow diffusion is completed, the FET channel forming part and resistance region forming part are doped with phosphorus at a low concentration by diffusion method or ion implantation method with an energy of about 100 to 150 KeV, and phosphorus is diffused at the same time as the above heat treatment. A low resistivity n-type channel region 42a with a depth of approximately 0.4 to 1.0 μm, and an n-type resistance region 42c with the same concentration and depth as the source and drain regions 38 and 39 and contact portions 40 and 41, respectively. d formed between.

Next, a step of forming an oxide film, which will become an insulator region, which is a feature of the present invention, begins. channel 42 and source,
Leaving a part on the drains 38 and 39, it is covered with an oxide film 43 and an oxidation-resistant Si ₃ N ₄ film 44, and thermal oxidation is performed at a relatively low temperature such as a high pressure oxidation method or a steam oxidation method. selectively forming the film 45 e.

Thereafter, the Si ₃ N ₄ film 44 is removed, an oxide film is formed using a CVD film, etc., and a p-type high concentration surface impurity region 46 which becomes a surface blocking region is formed through an open hole diffusion process f.

After that, through the normal process, contact and wiring 4
Perform steps 7 to 55. The metal gate 48 on the channel is a junction type which further reduces surface noise.
g installed to stabilize the FET.

Of the above steps, regions 45 and 46, which are the characteristics of the present invention, will be explained in more detail with reference to FIG.
Note that it goes without saying that the region 45 is not limited to the oxide film, and other insulating films may be used.

In FIG. 6, the opening area of, for example, silicon nitride (Si ₃ N ₄ ) 44 for forming 45 is set to 4 μm as a standard, as described above, and the center is set as the channel 42a and the source region 3.
8, the distance c can be set to about 2 μm. Also, the distance e on the drain side is approximately 2 μm.
becomes. At this time, the distances c and e are in a complementary relationship, and when a mask shift occurs, if c increases, e decreases, and the added value of c and e is always constant. d left by c and e indicates the length of the high concentration impurity region 46, but diffusion to this location is difficult due to the presence of the oxide film 45.
It is uniquely determined by the relationship between c and channel length, and is not dependent on the opening length to this region 46. Even if 4 μm is taken as the reference dimension, d can be set to about 2 μm, and can be set in a so-called self-alignment manner.

From the above, c, d, and e are each 2 μm even if the standard mask dimension is 4 μm, and c,
The addition of d and e is 6 μm, which is 12 in the case of Figure 3.
It is about half compared to μm. Also, change the standard dimension to 2
If it is made into μm, each can be halved. Furthermore, as is clear from FIG. 6, the oxide film 45 is formed deeper than the inversion region, that is, the region 46, which is necessary in order to have a sufficient breakdown voltage with the source and drain regions 38 and 39. . Furthermore, when the region 46 is used as a gate, since the concentration of the region 46 is high, the depletion layer formed by the region 46 spreads almost only to the channel region 42a, and almost fills the difference in depth between the oxide film 45 and the region 46. Become.

As described above, the present invention is a low-noise junction type
A high-density junction type that realizes FET and greatly reduces its disadvantage of low density.
It greatly contributed to the realization of FETs, is extremely convenient for integration, and is also suitable for high frequency applications.

[Brief explanation of the drawing]

Figures 1 and 2 are cross-sectional views of the FET with a back gate structure, and Figure 3 is a cross-sectional view of the FET with a back gate structure.
A cross-sectional diagram of the main structure of the low-noise FET proposed in the issue,
Figure 4 is a noise characteristic diagram of an n-ch FET prototyped by the present inventor, Figures 5 a to g are manufacturing process diagrams of an IC incorporating an n-ch FHT according to an embodiment of the present invention, and Figure 6 is FIG. 2 is a cross-sectional view of a main part structure of a high-density FET according to the present invention. 1...p-type silicon substrate, 32...n-type epitaxial layer, 34a, 34c...p-well, 35
... Base region, 38, 39 ... N-type source, drain region, 42a ... N-type channel region, 4
5...Oxide film, 46...P-type high concentration surface impurity region.

Claims (1)

[Claims] 1. Source and drain of the transistor of the other conductivity type selectively formed in a semiconductor layer serving as a gate region of one conductivity type of a junction field effect transistor formed on a semiconductor substrate. a low-resistance surface channel region of the transistor of the other conductivity type formed in the semiconductor layer from the surface thereof to a depth shallower than the source and drain regions so as to connect the region and at least the source/drain region; a high-concentration surface impurity doped region of one conductivity type selectively formed separately from the drain region; and a surface impurity doped region selectively deeper than the doped region between the surface impurity doped region and the source or drain region. 1. A semiconductor device comprising: an insulating region formed in contact with a source or drain region and an introduction region; and a gate electrode formed on a surface of the channel region with an insulating film interposed therebetween. 2. The semiconductor device according to claim 1, wherein a bipolar semiconductor element is selectively integrally formed on a semiconductor substrate. 3. Claim 1, characterized in that the high concentration surface impurity region is connected to the gate region.
The semiconductor device described in . 4. The semiconductor device according to claim 1, wherein the semiconductor layer is made of a P-well.