JPS6222464B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a low-noise junction field effect transistor (junction FET) structure and a semiconductor integrated circuit (IC) structure integrally formed with a bipolar semiconductor element.

Junction type FETs have characteristics that bipolar elements do not have, such as square-law characteristics, and have come to be used in various fields including acoustics, and recently integrated circuits (ICs) that incorporate this FET and bipolar elements have been developed. are required, and attempts are being made to integrate them.

One of the objectives is to increase circuit flexibility by introducing FETs, such as reducing cross-modulation due to increased input impedance and reducing the number of components due to low-noise O-bias operation. By integrating the FET into an IC, it is possible to obtain the benefits of reducing the occupied area and cost, as well as reducing noise induced in interconnection parts, etc., compared to using a single FET. I can do it.

Integrated configuration of conventional FET and bipolar element
Only ICs using PCH type FETs existed on the market, and were mainly developed for operational amplifiers. The reason for this is that the nch type is difficult to manufacture and, as will be explained later, has poor noise characteristics.Furthermore, in operational amplifiers that are allowed to use + and - power supplies, the FET source must be pulled down to -. This is because it is possible to use a pch FET.

By the way, FETs with a normal upper gate structure in which a gate diffusion region is created in the epitaxial growth layer
The channel thickness is determined by the difference between the thickness of the epitaxial layer and the diffusion depth of the gate diffusion region,
Their strict control is required. On the other hand, determining the base width of bipolar transistors in integrated circuits is done by delicately distributing heat treatment time.
As a result, the desired hfe (current amplification factor) is obtained. Therefore, delicate control of channel thickness and base width cannot coexist within the heat treatment conditions, and it is extremely difficult to integrate the above-mentioned ordinary FET and bipolar element into an IC.

Therefore, as an FET integrated into an IC with a bipolar element, a back gate structure as shown in FIG. 1 is adopted. FIG. 1 shows a conventional PCH FET integrated within an integrated circuit with a bipolar device. In other words, in ICs, FETs with a surface channel or back gate structure are used, which enable the formation of a channel region without performing heat treatment that would change the base width of the bipolar transistor, and which provide stable DC characteristics. Ru.

FIG. 1 shows the general structure of this backgate structure, where 1 is a p-type substrate, 2 is a backgate region made of an n-type epitaxial layer of 1 to 3 Ω-cm formed on the p-type substrate 1, Reference numerals 3 and 4 denote source and drain regions made of p ⁺ diffusion layers, which are formed simultaneously with the base region (not shown) of the bipolar transistor formed in the n-type epitaxial layer 2. 5 is an n ⁺ diffusion gate contact region.
Reference numeral 6 denotes a lightly doped p-type channel region which is formed from the upper surface of the epitaxial layer 2 by ion implantation with good controllability. 7 is a thermal oxide film, and 8 _S , 8 _D , and 8 _G are metal electrodes for the source 3 , drain 4 , and gate 5 , respectively. The operation of this FET is achieved by controlling the conductance of the channel region 6 using the gate region 2. In other words, by applying a bias voltage to the gate electrode 8 _G , the channel region 6
A bias voltage is applied from the back side of the capacitor to control conductance. In such a junction FET, the channel region 6 is formed on the top surface, so the depth and concentration of the channel do not strongly depend on the thickness and concentration of the epitaxial layer 2, but are almost exclusively determined by the amount of impurities doped from the top surface. It has the advantage of being determined by the method, and if formed using an ion implantation method or the like, it is possible to form a low resistance channel with very high precision.

However, this device also has significant drawbacks. That is, since the carrier running in the channel region 6 is controlled by the gate bias voltage applied from below the channel region 6, the carrier runs near the surface of the channel region 6 and causes noise.
This is because there are many sources of noise near the interface between the oxide film 7 and the channel region 6, such as charge exchange with the surface level and defects on the surface such as processing strain. In order to eliminate this drawback, methods have been devised to prevent the carrier from flowing onto the surface of the channel region 6.

In other words, as a first example, the FET shown in Figure 2
By providing 8 voltage application electrodes on the thermal oxide film 7 on the surface of the channel region 6, an electrically inverted region 9 appears on the surface of the channel region 6, and an electrically inverted region 9 is created at the interface between the channel region 6 and the thermal oxide film 7. This prevents the carrier from flowing into the part that causes 1/f noise. However, in order to form the inversion region 9 in the channel region 6 in this FET, a large voltage of much more than 10 V is generally required, although it depends on the thickness of the thermal oxide film 7, which is usually unsuitable for ICs.

Further, as a second example, a method can be considered in which a high resistance layer such as an intrinsic semiconductor layer (i-layer) is provided on the surface of the channel region 6 so that the surface carrier of the channel region 6 does not flow. In this method, since the impurity concentration of the i-layer itself is low, carriers are likely to move from the channel region 6 to the i-layer, and recombination in the i-layer is performed by these moving carriers, so that noise components on the surface are no longer generated. exist, and no significant reduction can be expected.

A back gate surface channel type FET will be studied based on an integrated circuit prototyped by the inventors.
The present inventors prototyped an IC based on the structure shown in FIG. 1, which integrated a nch FET formed in a p-well, a bipolar transistor, and a resistor. FIG. 3 shows this IC, with n-type buried regions 10a, 10
b, 10c are formed on the p-type semiconductor substrate 1.
A type epitaxial layer 2 is formed, and further a p-well 11a serving as a back gate and a p-well 11b for forming a resistor are formed, and a gate contact region 12 is formed in the p-well 11a at the same time as a base region 13 of a bipolar transistor. . The source and drain regions 14 and 15 and the resistor contact regions 16 and 17 are the emitter region 18 of the transistor.
At the same time, a surface channel region 19 is formed between 14 and 15, and a resistance region 20 is formed between 16 and 17. Reference numerals 21, 22, 23, 24, and 25 are source, drain, gate, emitter, and base electrodes, respectively, and 26 and 27 are resistance electrodes. 28
29 is an oxide film, 29 is a p ⁺ type isolation region, and 30 is a MOS gate electrode on channel region 19. .

In the IC shown in FIG. 3, the p-well 11 is manufactured in balance with other heat treatment conditions for bipolar transistor manufacturing, but after the p-well is formed, the nch FET and resistor regions are It can be created in common with the formation of each region of a bipolar element.

In this IC, the FET has V _p (pinch-off voltage), I _DSS (drain saturation current) when the resistivity is several KΩ/unit and the channel thickness is about 0.1 to 0.4 μm, depending on the resistivity of the channel. , q _n (mutual conductance), h _fe , V _CBO , V _CEO of bipolar transistors, etc., satisfactory characteristic values were obtained. However, as a result of examining the noise performance of the FET shown in Figure 3, the inventors found that the noise was large over the entire frequency range.
In particular, there are chips with large 1/f noise that have an input equivalent noise voltage exceeding 1 μV/√Hz near 10 Hz.
Turns out it's worse than pch FET. this is,
This is thought to be due to the fact that the carrier travels on the surface of the channel, which causes surface noise due to the transfer of charges mainly at traps existing on the silicon oxide film surface and crystal defects on the surface. Furthermore, even if an MS gate is provided, the noise performance is poor, and in particular, the nch type has poor characteristics in the low frequency region compared to the pch type. There is no established theory on this, but it seems to be related to the type of carrier within the channel. surface like this
It was recalled that CH-type FETs are undesirable in terms of noise.

As stated above, the inventors of the present invention have determined that the depth of the channel and the depth of the gate should be increased in order to reduce the variation in DC characteristics based on the study of the manufacturing conditions of a single-element junction FET. Things that should not be done and when the carrier is run on the surface area, noise especially 1/1
It was discovered that the f-noise increases and that even if a MOS gate is attached, a large amount of voltage is required. Also, when integrated with a bipolar element, it can be used as a FET.
In order to obtain stable DC characteristics, a back-gate type device is required that does not require high heat treatment conditions, but this device has poor noise characteristics, mainly high 1/f noise, which is a practical problem. Furthermore, it has been found that it is difficult to form a good resistor and to obtain an integrated IC suitable for various electronic devices such as audio equipment.

Therefore, it is conceivable to form an inversion layer on the entire surface of the surface channel region 19 to block the carrier flow on the surface of conductivity type opposite to that of the channel, but if the inversion layer is a highly doped region, the drain-gate The withstand voltage between the source and the gate is low, and there is a high possibility that it will be destroyed under normal usage conditions.
In addition, when the inversion layer has a low concentration, the depletion layer when a voltage is applied to the gate spreads not in the channel direction but also inside the inversion layer, and when the inversion layer is used as the upper gate, the control efficiency by gate voltage is Therefore, the mutual conductance g _n is low, and the depletion layer extends to both the inversion layer and the channel, resulting in large variations in the drain current I _D .
Since this upper gate has a low concentration, it inevitably has a high resistance, which has the drawback of significantly increasing thermal noise due to an increase in gate input resistance.

Therefore, in view of these points, the present inventors proposed a junction type FET which has excellent DC characteristics and noise characteristics and is suitable for integration in Japanese Patent Application No. 102426/1982. this
The FET has a surface channel region (for example, 19 in FIG. 3) between the source and drain regions in which a high concentration surface impurity doped region of the opposite conductivity type to this region is formed separated from the drain. This structure can prevent surface carriers that cause noise, and since the high concentration surface impurity region of the opposite conductivity type to the channel is separated from the drain, it can be highly concentrated and its resistance is extremely low. Since it can be made small, thermal noise components due to input resistance can be almost ignored. Curve I in Fig. 4 shows the noise characteristics of the FET proposed in this patent application No. 52-102426.
A value of 1 to 2 nV/√Hz has been obtained with noise around several KHz compared to FET.

However, this structure also has some drawbacks. This is an increase in the noise voltage around 10Hz.
This is mainly due to the fact that the entire surface between the high-concentration surface region, which is also used as a gate region, and the source and drain regions is not covered with the high-concentration region in order to improve the breakdown voltage, as described above.

Therefore, the present invention is characterized in that a low concentration inversion region is added between the drain and source regions and the high concentration inversion region in order to further improve the noise characteristics in this low frequency region.

A method of manufacturing an IC according to an embodiment of the present invention in which a nch FET and a bipolar element are integrally formed will be described with reference to FIG.

Figure 5 a is p-type, (111) plane index, 1 to 10 Ω-cm
This figure shows a situation in which n ⁺ buried diffusion layers 31a, 31b, and 31c made of As or Sb are formed on the surface of a wafer substrate.

Thereafter, epitaxial growth using SiCl ₄ is performed on the substrate 1 to form an n-type epitaxial layer 32 with a specific resistance of 0.5 to 3 Ω-cm, and diffusion is performed from a source made of BBr ₃ or Bcl ₃ . A p ⁺ type isolation diffusion layer 33 is formed to separate layer 32 into island regions. When forming this layer 33, a high concentration impurity is first diffused into the formation portion of the layer 33, and then the impurity is further deeply diffused by heat treatment. This deeper diffusion will result in the same process.
Island-shaped p-well regions 34a and 34c are formed to serve as a back gate region of the FET and a region for forming a resistor. That is, the p-wells 34a and 34c are formed by selective doping using a conventional thermal diffusion method or ion implantation method, followed by the above-mentioned heat treatment, and have a specific resistance of 0.5 to several Ω-cm and a width of about 5 μm (b).

Next, a boron source such as BBr ₃ , Bcl ₃ , B ₂ O ₃ is diffused selectively onto the p-well 34a and the epitaxial layer 32, and the p ⁺
A shaped base region 35 and a resistive p ⁺ type gate contact portion 36 of the nch FET are simultaneously formed (c).

Thereafter, an n + type emitter region 37 is formed in the base region 35 from a phosphorus (p) source such as POcl ₃ or P ₂ O ₅ , and ^{n + type} source and drain regions 38, 39 are formed in the FET p well 34a. The n ⁺ type contact portions 40 and 41 of the resistance region are formed in the p well 34c by 1.3 mm.
Selectively form at a depth of ~2.0 μm. For this diffusion, a method is used in which highly concentrated phosphorus (p) is first diffused shallowly and then heat-treated at a predetermined temperature. After this shallow diffusion ends,
Phosphorus (p) is doped at a low concentration into the FET channel forming part and resistance region forming part by diffusion method or ion implantation method with an energy of about 100 to 150 KeV, and at the same time as the above heat treatment, phosphorus is diffused to a thickness of about 0.4 to 1.0 μm. A low resistivity n-type channel region 42a with a depth of
8 and 39 and between the contact portions 40 and 41 (d).

After this, a p-type low concentration region 43, which is a feature of the present invention, is formed on the surface of the channel region 42a. In this formation, boron is implanted by ion implantation using the same mask used for forming the channel region 42a, and p-type low concentration regions 43 are selectively formed on the surface of the channel region 42a. At this time, a p-type low concentration region 44 is similarly formed in the resistance region 42c, but since this region 44 is shallow, it does not significantly change the resistance characteristics. The region 43 is for blocking current on the surface of the channel, and an oxide film is formed on the surface when the channel 42a is formed, and by ion implantation, it is formed through this oxide film to a shallow depth of, for example, 0.05μ or less, with good controllability, and the ratio is It has a resistance of several 100Ω to several KΩ/port. Note that this region 43 can also be formed using a doped oxide method or the like.

Next, the inversion layer for blocking surface current, that is, the high concentration impurity doped region 4 proposed in Japanese Patent Application No. 52-102426.
form 5. This region 45 is a p-type opposite to the channel region, and is made of a very thin layer with a thickness of 500 Å to 3000 Å.
The surface concentration formed by doped oxide method, doped polysilicon method, etc. is 10 ¹⁹ ~
It has a high concentration of 10 ²¹ /cm ³ , is formed separately from the source and drain regions 38 and 39, and partially extends to the gate region 34 (not shown) and is connected to the p-well 34a. (e). Therefore, p-type regions 43a and 43b are formed separately between the source and drain on both sides of this region 45.

After that, an insulating film 46 made of SiO ₂ , Al ₂ O ₃ or the like used in normal integrated circuit technology is formed, and holes are opened in predetermined areas to form source, drain, and gate electrodes 47 ,
48, 49, emitter, base electrode 50, 51,
The IC shown in FIG. 5f is formed by forming resistance electrodes 52 and 53.
is completed. Note that 54 and 55 are thin insulating films 56 on the channel region 42a and the resistance region 42c.
This is a gate electrode installed via a and 56c. In particular, Al ₂ O ₃ has a negative charge and is advantageous because the voltage applied to the gate is small.

Now, first of all, in the IC created in this way,
The resistor formed from the resistance region 42c has a pinch-off voltage V _p of approximately 10 to 30V, and does not saturate at the 5V voltage used in this IC, and has a specific resistance of 200.
A high value of ~1KΩ/mouth can be obtained, and the withstand voltage is also high.
It has a high voltage of 20V to 30V and excellent linearity.
It is fully usable. Furthermore, the electrode 55 in the resistor prevents the oxide insulating film 56c from forming a charge map due to the reaction with the diffusion region, resulting in instability such as withstand voltage creep, and from changing the resistance value due to charge up of the insulating film 54c due to the surrounding atmosphere. , which made it possible to improve stability.

The bipolar npn transistor in Figure 5 f is h _fe
=90±20, V _CBO ≒60V, V _CKO ≒25V normal performance could be obtained.

The FET in this IC structure achieves V _p =
It was possible to obtain an extremely small value of about 0.9±0.2V and a small variation. The reason why we were able to reduce the pinch-off voltage is because of the relatively shallow surface channel region of one conductivity type, approximately 0.5 to 1.0μ.
This is because an extremely shallow surface region of the other conductivity type of about 500 Å to 3000 Å (0.05 μ to 0.3 μ) is formed, and the channel region is controlled to a very large extent by this surface region.

That is, as shown in FIG. 6, for example, the thickness of the channel region 42a is 0.6μ, and the thickness of the region 45 is 0.1μ.
If μ is assumed and the spread of the depletion layer into the channel region due to the gate voltage is 0.2μ, and this is shown by a broken line, the depletion layer will expand by 0.2μ from the bottom surface of 45 and the bottom surface of 42a, which is substantially the thickness of the channel region. The channel thickness is 0.1μ, which is extremely small compared to the channel thickness of 0.4μ in the case of only the back gate without the region 45. Therefore, if the region 45 is provided within the shallow channel region 42a, the controllability of the channel region 42a can be greatly improved and the pinch-off voltage can be reduced. In this way, area 4
It has been found that in the case of the channel region 42a having a shallow channel region 42a as in the case of a back gate structure, it is possible to obtain a larger channel control effect than expected.

Furthermore, in the present invention, the p-type low concentration regions 43a, 4
3b is formed on the surface of the channel region 42a and can block surface channel current between the high concentration region 45 and the source and drain, making it possible to extremely reduce 1/f noise in the low frequency region.
FIG. 4 shows the noise performance of the FET shown in FIG.

The regions 43a and 43b have a low concentration,
The breakdown voltage of the junction type FET can be maintained.

In addition, when using the gate of a junction FET with an O bias circuit, there are cases where only a voltage of around 1V is applied between the source and the gate. It is also possible that the heavily doped surface gate regions 45 are in direct contact. In this case, only the lightly doped region 43b between the drain and the heavily doped gate region 43b exists on the channel surface (not shown).

In the above embodiments of the present invention, only N-channel junction FETs have been mainly considered, but almost the same can be said for P-channels as well.

As described above, according to the present invention, a back-gate type junction FET that is easy to integrate with other elements can be used.
In this method, high-concentration and low-concentration inversion regions are installed on the surface of the channel, and a gate electrode is further installed on the surface channel with an insulating film interposed therebetween.
Further reduction of surface noise and improvement of stability,
It was possible to significantly lower 1/f and thermal noise.

[Brief explanation of the drawing]

Figures 1 and 2 are cross-sectional views of the FET with a back gate structure, and Figure 3 is a nch-
Figure 4 is a partial cross-sectional view of an IC incorporating an FET, and the FET prototyped by the present inventors and the present invention are shown in Fig. 4.
FET noise characteristic curve diagrams, FIGS.
Figure 6 is a diagram showing the manufacturing process of the IC, and is a structural diagram of the main parts of the FET shown in Figure 5. 32...n-type epitaxial layer, 34a...p
Well (back gate region), 34c...p well, 35, 37...base, emitter region, 38
... Source region, 39 ... Drain region, 42a
...N-type channel region, 43, 43a, 43c
. . . p-type low concentration surface region, 45 . . . surface p-type high concentration impurity doped region.

Claims (1)

[Claims] 1. Source and drain of the other conductivity type of the junction field effect transistor formed on the semiconductor substrate, which are selectively formed in a semiconductor layer serving as a gate region of one conductivity type of the transistor. a low resistance surface channel region of the other conductivity type formed shallower than the source and drain regions from the surface of the semiconductor layer so as to connect at least the source and drain regions; a high-concentration surface impurity-introduced region of one conductivity type that is selectively formed separately from the source and drain regions and is provided to highly impurity-concentrate the gate of the junction field effect transistor; and this surface impurity-introduced region. and a low concentration region of one conductivity type formed on the surface of the channel region between the channel region and the drain region in contact with the introduction region and the drain region, and a gate electrode formed on the surface of the channel region with an insulating film interposed therebetween. A semiconductor device characterized by comprising: 2. The semiconductor device according to claim 1, characterized in that a bipolar semiconductor element is formed within a semiconductor layer. 3. Claim 1, characterized in that the high concentration surface impurity region is connected to the gate region.
The semiconductor device described in . 4. The semiconductor device according to claim 1, wherein the semiconductor layer is made of a P-well.