JPS5830742B2 - Junction field effect semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a junction field effect semiconductor device, and more particularly to a transistor (hereinafter referred to as a junction FET).

Junction type FETs have characteristics that bipolar elements do not have, such as square-law characteristics, and attempts have been made to use them in various fields including the acoustic field, and recently there has been a need for integrated circuit ICs that incorporate these FETs and bipolar elements. Attempts are being made to integrate these.

One of the purposes is to introduce FETs to reduce cross modulation due to increased input impedance, reduce noise, and improve
By making it possible to increase the degree of circuit freedom by reducing the number of parts through O-bias operation, by integrating the FET into an IC, it takes up less space than when using a single FET. It is possible to obtain the benefits of reduction in area and cost, and reduction in noise induced in interconnection parts and the like.

Conventional ICs that integrate FETs and bipolar elements are p
Only those using a channel type F'ET exist on the market, and were mainly developed for use in operational amplifiers.

The reason for this is that the nch type is difficult to manufacture and has good noise characteristics as described later.
For operational amplifiers that are allowed to use a power supply of FE
By pulling the source of T to - pch F E
This is because T can be used.

By the way, in a conventional FET with a top gate structure in which a gate diffusion region is formed in an epitaxial growth layer, the channel thickness is determined by the difference between the thickness of the epitaxial layer and the diffusion depth of the gate diffusion region, and strict control of these is required. Ru.

On the other hand, the base width of a bipolar transistor is determined by delicately allocating heat treatment time, thereby obtaining a desired hfe.

Therefore, delicate control of channel thickness and base width cannot coexist within the heat treatment conditions, and it is extremely difficult to integrate the above-mentioned ordinary FET and bipolar element into an IC.

Therefore, the back gate structure shown in FIG. 1 is adopted as the FET integrated into an IC with the bipolar element.

FIG. 1 shows a conventional pch FET integrated within an integrated circuit with bipolar elements.

That is, the surface channel and bank gate structure shown in FIG. 1 is adopted in order to make it possible to form a channel region without performing heat treatment to the extent that the base width of the bipolar transistor changes.

In the figure, 1 is a p-type substrate, 2 is a bank gate region made of an n-type 1-32 cm epitaxial layer formed on the p-type substrate 1, and 3 and 4 are a source made of a p-type diffusion layer. , is formed simultaneously with the base region (not shown) of the bipolar transistor formed in the n-type epitaxial layer 2 in the drain region.

5 is an n+ diffusion gate contact region.

6 is a lightly doped p-type channel region in the epitaxial layer 2.
It is formed from the top surface by ion implantation with good controllability.

7 is a thermal oxide film, 8s, 8D. 8G is each source 3
, drain 4, and gate 5 metal electrodes.

The operation of this FE'l' is performed by controlling the conductance of the channel region 6 using the gate region 2.

That is, by applying a bias voltage to the gate electrode 8°, the bias voltage is applied from the back surface of the channel region 6, and conductance control is performed.

In such a junction FET, the channel region 6 is formed on the top surface, so the depth and concentration of the channel do not strongly depend on the thickness and concentration of the epitaxial layer 2, and are almost uniquely determined by the amount of impurities doped from the top surface. It has the advantage of being determined by ion implantation, and if it is formed using an ion implantation method or the like, it is possible to form a channel with very high precision.

However, this device also has significant drawbacks.

In other words, since carriers traveling in the channel region 6 are controlled by the gate bias voltage applied from below the channel region 6, the carriers travel near the surface of the channel region 6 and cause noise.

This is because there are many sources of noise near the interface between the oxide film 7 and the channel region 6, such as charge exchange with the surface level and defects on the surface such as processing distortion.

In order to eliminate this drawback, methods have been devised to prevent carriers from flowing onto the surface of the channel region 6.

That is, in the FET shown in FIG. 2 as a first example, by providing a voltage application electrode 8ch on the thermal oxide film 7 on the surface of the channel region 6, an electrically inverted region 9 appears on the surface of the channel region 6, and the channel region This prevents carriers from flowing into the interface between the thermal oxide film 7 and the thermal oxide film 7, which causes 1/f noise.

However, in order to form the inversion region 9 in the channel region 6 of the FET, a large voltage, generally far exceeding about 10V, is required, depending on the thickness of the thermal oxide film 7, and this is not suitable for ordinary ICs. .

Further, as a second example, a high resistance layer such as an intrinsic semiconductor layer (i-layer) is provided on the surface of the channel region 60, and the channel region 60 is
A method in which zero surface carriers are not allowed to flow is also conceivable.

In this method, since the impurity concentration of the i-layer itself is low, carriers tend to move from the channel region 6 to the i-layer, and recombination in the i-layer is performed by these moving carriers, so that noise components at the surface are no longer generated. exist, and no significant reduction can be expected.

In view of this problem, the inventors of the present invention have considered forming an n layer of a conductivity type opposite to that of the p-type channel region 6 over the entire surface of the channel region 6.

However, the surface n-layer needs to have a low concentration in order to prevent a drop in breakdown voltage between the source and drain.

This low concentration n-layer is affected by surface recombination noise similar to the above-mentioned i-layer, and the depletion layer at the PN junction at the interface with the channel region 6 spreads to both the surface n-layer and the channel region 60. As a result, it is difficult to control the depth of the channel, and the variation in the saturated belaying current ID5S becomes extremely large, which is not preferable.

On the other hand, if a high concentration n layer is formed on the surface of the surface channel region 6, the influence of surface recombination noise is eliminated, and the depletion layer only extends in the direction of the channel region 6, which has the advantage of making it easier to control the channel depth. Source 3 of the thing
, the breakdown voltage between the drains 4 becomes low, making it impractical.

As a result of further studying the problems of FETs, the present invention proposes to form a drain region, which is a high-concentration surface impurity doped region of the opposite conductivity type, in the surface channel region between the source and drain, separately from this region. It has been discovered that a junction type FgT for IC with excellent DC characteristics and noise characteristics can be obtained by the following method.

Furthermore, the present invention provides an nch integrated with a bipolar device.
This proposes a structure suitable for FET.

In other words, bipolar transistors in ICs are usually of the NPN type, and only ten-power supplies are used; for example, FETs in ICs used in audio equipment such as tape recorders, which require a single power supply, are also of ten-power supplies. is required.

In this case, an nch type FET is required to be integrated with the npn transistor.

That is, nch is desirable as an FET in an IC that can be used with a single power supply and low voltage.

However, the back gate type nch having the structure shown in FIG.
When considering building an FET into an IC, it is necessary to create a p-well that will serve as a gate region in an n-type epitaxial layer.

The present inventors prototyped a bipolar IC incorporating an nch FET formed in a p-well based on the structure shown in FIG.

FIG. 3 shows this IC, with an n-type buried region 10 a t
An n-type epitaxial layer 2 is formed on the p-type semiconductor substrate 1 in which a bank gate is formed, and a
A well 11 is formed in which a gate contact region 1 is formed.
2 is formed simultaneously with the base region 13 of the bipolar transistor.

Source and drain regions 14 and 15 are formed simultaneously with the emitter region 16 of the transistor, and a surface channel region 17 is formed between 14 and is.

1B, 19, 20, 21.22 are source, drain, gate, emitter, and base electrodes, respectively.

23 is an oxide film, 24 is a p-type isolation region, and 25 is a MOS gate electrode on channel region 17.

In the IC shown in FIG. 3, the p-well 11 is manufactured in balance with other heat treatment conditions for manufacturing the bipolar transistor, but after the p-well is formed, the nch
Each region of F E 'I' is formed in common with the formation of each region of the bipolar element.

The FET of FIG. 3 created in this way has Vp (pinch-off voltage), ID5S (drain saturation current), gm
Satisfactory characteristic values were obtained for DC parameters such as (mutual conductance), hfe5VCBO and VCEO of bipolar transistors.

However, as a result of examining the noise performance of the FET shown in Fig. 3, the inventors found that the noise was large over the entire frequency range, and in particular, the 1/f noise was 10 Hz for dogs.
There are some chips in the vicinity that have an input equivalent noise voltage of 1 μV-Hz, and it has been found that this is worse than the pch FET.

The vertical axis in FIG. 4 indicates the input equivalent noise voltage <In> in nanovolts.

The poor noise performance of the nch type is naturally related to manufacturing conditions, although there is no established theory, but it also seems to be due to the fact that the majority carriers in the channel are electrons. It will be done.

■ in Figure 4 indicates the third region formed without providing a p-well.
pch F in Figure 2, which is similar to the figure, i.e., integrated into IC.
Although the overall noise characteristics are by no means satisfactory, the nc
The H type has higher noise than the PCH type.

As described above, it has been found that although the surface channel type FET is provided with a MOS gate, it is still undesirable in terms of noise.

As a result of the above studies, when integrating with bipolar elements, D
Banked type FETs, which provide stable characteristics in terms of C, have poor noise characteristics, especially nch FETs, which have poor noise characteristics.
In particular, it has been found that the 1/f noise is large, causing many problems when used in audio equipment, etc.

That is, as described above, the inventors of the present invention have determined that the depth of the channel and the depth of the gate should be deep in order to reduce the variation in DC characteristics based on the study of the manufacturing conditions of a single-element junction FET. It was discovered that noise, especially 1/f noise, increases when carriers are run on the surface, and that a large amount of voltage is required even if a MOS gate is attached.

Furthermore, when integrated with a bipolar element, in order to obtain stable DC characteristics as an FET, a back gate type is required that does not require high heat treatment conditions, but this element has poor noise characteristics. Mainly, the 1/f noise was very large, and there were many practical problems.

As explained below, the present invention is based on a bipolar element and an FE.
With the structure described above in integrating the T, desirable DC characteristics and noise characteristics are achieved.

Now, the present invention is based on a bank gate type in which a channel is provided on the substrate surface and a voltage is applied from the bottom of the channel in order to make the value and distribution of the DC characteristics of the junction FET uniform and to integrate it with a bipolar transistor. In addition, in order to reduce the high input-referred noise as mentioned above, an extremely thin surface impurity doped region of the same conductivity type as the gate is formed on the surface of the channel region, and is separated from the drain region.

First, a method for manufacturing an IC according to an embodiment of the present invention in which a nch FET and a bipolar element are integrally formed will be described with reference to FIG.

FIG. 5a shows a situation in which n10 diffusion layers 31 a and 31 b made of As or sb are formed on the surface of a wafer substrate 30 of p type, (111) plane index, 1 to 10 β-m. There is.

Thereafter, epitaxial growth using SiCl was performed on the substrate 30 to form an n layer with a specific resistance of 0.5 to 3 g-α.
After forming the epitaxial layer 32, diffusion is performed from a source made of BBr3 or BCl3 to form an isolation diffusion layer 33.

When forming the diffusion layer 33, a high concentration impurity is first diffused into the formation portion of the layer 33, and then the impurity is further diffused by heat treatment to form the layer 33.

After this deeper diffusion, a p-type island region (p-well) 34, which will become a bank gate region, is formed in the epitaxial layer 32 in the same step.

This is mainly formed by selective doping by ion implantation followed by the above heat treatment, and the resistivity of the island region 34 is 0.5 to 312-CrfL.

Next, on the epitaxial layer 32 and the well 34
Boron is simultaneously diffused onto the epitaxial layer 32.
A p+ base region 35 is formed on the top, and a gate contact portion 36 having low resistance contact with the well is formed on the well 34. Next, the emitter region 37 and the source and drain regions 38 and 39 of the junction FET are formed with phosphorus (P). simultaneously formed by selective diffusion of

At this time, highly concentrated phosphorus P is preliminarily diffused shallowly into the emitter, drain, and source formation regions, and then heat-treated at a predetermined temperature to diffuse the impurity to a depth of 1 to 2.5 μm. 38, drain region 39
form.

After the shallow diffusion of phosphorus P is completed, phosphorus P is doped at a low concentration into the channel forming part of the FET using a diffusion method or an ion implantation method at an energy of 100 to 150 keys, and phosphorus is diffused at the same time as the above heat treatment. About 0.
d to form an n-type channel region 40 with a depth of 5 to 1.0 □m.

In this way, the region 30 is formed in common with the emitter, source, and drain.

Next, a high concentration impurity doped region 41 for blocking surface current, which is a feature of the present invention, is formed.

This region 41 is of the p-type opposite to the channel region, and is made of a very thin layer with a thickness of 500 to 3000A, and p-type boron impurity is added by means of a diffusion method, a doped oxide method, a doped polycondensation method, etc. Formed by

It has a high surface concentration of 1019 to 10''/cA, is formed separately from the source and drain regions 3B and 39, and partially extends to the gate region 34 (not shown).
It is connected to the well 34.

Furthermore, in the F''ET of this embodiment, a gate metal film 43 is formed on the channel region 40 to a thickness of about 0.8 μm by a normal vacuum evaporation or sputtering method via a 5 in 2 thin insulating oxide film 42 made of Al2O3 or the like.

Al2O3 has a negative charge and is advantageous because the voltage applied to the gate can be lowered.

44 is a thick insulating oxide film, 45, 46, 47, 48, 49
f are the source, drain, gate, emitter, and base electrodes, respectively.

Now, the region 41 functions to prevent the carriers in the channel region 40 from flowing to the surface, and can reduce the noise caused by the carriers flowing on the channel surface.

That is, the number of carriers flowing on the very surface of the channel region 40 is very small compared to the number of carriers flowing under the region 41, and the influence on the surface of the region 400 where the region 41 is not formed is small, making it possible to achieve low noise. can.

Further, since the region 41 is separated from the drain region 39, the breakdown voltage between the source 38 and the drain 739 does not decrease.

Furthermore, if the region 41 is doped shallowly to the extent that it does not affect the thickness of the channel region 40, the channel characteristics are uniquely determined by the doping amount during ion implantation when forming the channel region 40, Since the thickness of the region 40, impurity concentration, and pattern size can be precisely controlled, it is possible to extremely reduce variations in channel characteristics, and the distribution of ID5S in the wafer can be kept within 10% without causing any deterioration of DC characteristics. I was able to fit it into.

Furthermore, in the FET shown in FIG.
Minority carriers are collected in the area other than the area where is formed, a p-thick inversion layer is formed in this area, and the influence of surface noise is almost completely eliminated.

Furthermore, the FET of this example and the one shown in Figs. 2 and 3 (simply MO
The following major differences were found between the structure and the one provided with eight gate structures.

That is, in FIG. 3, the p-thickness inversion layer is not formed unless a large negative voltage is applied to the electrode 25, and when only a single power source is used, the effect of the electrode 25 is not exhibited at all.

However, in the present invention, minority carriers (holes) are replenished from the p-type region 41, so that the metal film 4
By simply setting 3 to Ov or the lowest potential of the power supply, the channel region 40 between the region 41 and the source and drain 38, 390
A p-thickness inversion layer (not shown) could be easily formed on the partial surface.

As described above, in the present invention, the gate metal film 43 can electrically form an inversion region where holes are gathered on the channel region 40 by simply applying the lowest potential bias voltage of an appropriate single power supply. This separates the region where carriers travel from the interface between the insulating film 42 and the channel region 40, thereby reducing surface noise that normally occurs between the silicon interface and the insulating film.

The characteristics of the junction FET achieved through the process described above are VP-0.9v±0.2 V with very little variation, and the bipolar transistor formed at the same time has hfo-90±20, VCBO medium 60V
, 25V in VCEO was obtained.

Next, nch F E T of Fig. 5 f and Fig. 5 f
nchFET without MOS gate 43 and region 4
Consider a comparison of the noise performance of FETs without 1.

In Figure 6, the channel length is 10μ, the width of region 41 is 5μ, the thickness is 0.6μ, and the distance between drain 39 and region 41 is 2.5μ.
, which shows the noise characteristics of the nchFET according to the present invention when the voltage applied to the gate metal film 43 is Ov.

The circle mark indicates the case without the metal film 43, and the cross mark indicates the case where the metal film 43 is installed, and it can be seen that the noise performance in the low frequency region is improved by 1.43.

As is clear from the comparison between Fig. 6 and Fig. 4, the area 41
Due to the presence of , the noise performance has become extremely good.

As mentioned above, FIG. 4 shows a prototype FET manufactured by the present inventors (FIG. 3) without the region 41 in FIG. 5 f, and the manufacturing conditions other than the region 41 are the same as in FIG. be.

As is clear from FIG. 6, the noise of this embodiment is low over the entire band, and especially in the low range, the noise is reduced to several tens of minutes.

The reason why the prototype shown in FIG. 3 has very poor characteristics is that there is no region 41, and the voltage applied to the electrode 25 to form the channel inversion layer is approximately Ov, which is sufficient to form the inversion layer. I think it's because I couldn't do it.

However, in this embodiment, in addition to the existence of the region 41, minority carriers can be replenished from there, resulting in a low voltage, that is, O
An inversion layer could be formed even when the temperature was lower than V, and good results were obtained.

Now, in this embodiment, the above experiment was performed with the thickness of the region 41 being 0.
1μ, but the thickness of the region 41 was set to 0.0μ under exactly the same conditions.
When experiments were conducted using 0.05μ and 0.2μ, results almost the same as those shown by the x mark in FIG. 6 were obtained.

Considering that the minimum thickness that can be doped is about 0.05 μm, this shows that the influence of surface noise can be reduced as long as the region 41 is formed in the channel region 40.

Note that if the thickness of the region 41 is set to about 0.05μ to 0.1μ, the region 41 will not have any influence on the DC characteristics of the channel region 40, so the DC characteristics of the channel region 40 can be determined only by the channel forming conditions. .

Generally, it is considered acceptable if the device variation distribution is 10 to 30%, and the depth of the channel region 40 is 1.0%.
If it is within μm, the DC% variation of junction FET is 15
%, which satisfies the permissible range.

Furthermore, another feature of the FET according to the present invention is that the pinch-off voltage Vp of the FET can be reduced.
In the case shown in the figure, it was possible to set the voltage to about 0.9±0.2V, and also to reduce the variation thereof.

The reason for this is that 500A to 3000A (0
This is because an extremely shallow surface region of the other conductivity type of about 0.05 μm - 0.3 μm is formed, and the channel region is controlled to a very large extent by this surface region.

This will be explained with reference to FIG. 7, which shows a part of FIG. 5f.

Assuming that the thickness of the channel region 40 is 0.6μ, the thickness of the region 41 is 0.1μ, and the spread of the depletion layer into the channel region due to the gate voltage is 0.2μ, this is shown by a broken line.
The depletion layer extends from the bottom surface of 41 and the bottom surface of 40 by 0.2μ, and the thickness of the channel region is substantially 0.1μ.
Therefore, the channel thickness is extremely smaller than the channel thickness of 0.4μ in the case of only the back gate without the region 41.

Therefore, if the region 41 is provided within the shallow channel region 40, the controllability of the channel region 400 can be greatly improved and the pinch-off voltage can be reduced.

In this way, it has been found that the region 41 has a greater channel control effect than expected in the case of a shallow channel region 40 such as a back gate structure.

In FIG. 8, a gate electrode 50 is formed so that a gate metal electrode is not provided in a portion corresponding to an island region 41 doped in a channel region 40. In FIG.

Even with such a configuration, effects similar to those of the embodiment shown in FIG. 5 can be obtained.

Furthermore, the FET of the embodiment shown in FIG. 9 uses the island region 41 as the source 3.
This configuration is connected to 8.

In this embodiment, the channel length between the source 38 and the drain 39 is l-7.5μ, the length of the region 41 is m=5μ, and the distance between the region 41 and the drain 39 is n=2.5μ, and the other embodiments are shown in FIG. When the frequency characteristics of the noise were investigated under the same conditions as in Figure 6, almost the same results as in Fig. 6 were obtained.

In other words, in the embodiment shown in FIG.
Since the size can be reduced by the distance between 1 and 1, this structure is advantageous for high integration.

Almost the same characteristics could be obtained in the pch FET according to the present invention, in which the conductivity type of the FET shown in FIG. 5 was reversed.

That is, FIG. 10 shows an IC according to another embodiment of the present invention in which a pchFET and a bipolar transistor are integrated, and a p-well is directly formed in the epitaxial layer without forming a p-well.
A type channel region is formed, and regions of opposite conductivity type are marked with a dash (').

As described above, in the present invention, a channel region of one conductivity type is formed on the surface of a back gate region of one conductivity type, and a surface impurity-introduced region of one conductivity type separated from a drain region is formed in this channel region. The structure is formed so that everything is covered with an insulating film, so it can greatly improve the effect of surface noise without reducing the DC% characteristics. Furthermore, when combined with an insulated gate, the noise performance is further improved. became possible.

Furthermore, the present invention proposes a structure suitable as a high-density FET in an IC using a single low-voltage power supply, and has greatly contributed to the realization of high-performance integrated circuits.

[Brief explanation of drawings]

Figures 1 and 2 are structural cross-sectional views of FE'I' with a back gate structure, Figure 3 is a partial cross-sectional view of an IC incorporating a nchFET prototyped by the present inventors, and Figure 4 is a structural cross-sectional view of an FE'I' with a back gate structure. A noise characteristic curve diagram of a prototype FET, FIG. 5 a"f is a manufacturing process diagram of an IC incorporating an nchFET according to an embodiment of the present invention, FIG.
Fig. 7 is a structural diagram of the main part of the FE'I', Figs. 8 and 9 are structural sectional views of FETs according to other embodiments of the present invention, and Fig. 10 is a structural diagram of the FET according to other embodiments of the present invention. FIG. 32...Epitaxial layer, 34...
p-well (back gate region), 38, 38'...
... Source region, 39, 39'... Drain region, 40, 40'... N-type surface channel region, 4L41'... Surface high concentration impurity introduction region, 43 ......Gate metal film.

Claims (1)

[Claims] 1. A source/drain region of one conductivity type selectively formed in a semiconductor layer serving as a gate region of the other conductivity type;
at least a surface channel region of the other conductivity type formed from the surface of the semiconductor layer shallower than the source/drain regions so as to connect the source/drain regions; A junction characterized by comprising: a high-concentration surface impurity-introduced region of one conductivity type selectively formed separately from the drain region; and a gate electrode formed on the surface of the surface channel region with an insulating film interposed therebetween. type field effect semiconductor device. 2. The junction field effect semiconductor device according to claim 1, wherein the surface impurity introduced region is connected to the gate region.