JPS54157090A - Semiconductor device and its production - Google Patents

Abstract

PURPOSE:To improve an electric characteristic and eliminate a harmful parasitic effect by providing an insulator layer just under the gate region of the gate PN junction make a part of the junction ineffective when a vertical J-FET or a static induction transistor is formed. CONSTITUTION:Maskes 24 and 26 of SiO2 films are used to form N<+>-type regions 28A, 30A and 32A, which should become the soruce or bit region of a static induction transistor, on P<->-type Si substrate 22 by diffusion. Next, an N-type Si layer is grown throughout the surface while leaving masks 24 and 26 as they are, and the donor in regions 28A, 30A and 32A is distributed again to make regions 28, 30 and 32, and simultaneously, N<->-type single crystal region 34, 36 and 38 and poly crystal regions 40 and 42 are generated on regions 28, 30 and 32 and on masks respectively. After that, an acceptor is doped throughout the surface to make regions 40 and 42 low-resistance, and simultaneously, P<+>-type regions 44, 46 and 48 which should become gate regions are formed while they are positioned on regions 28, 30 and 32 respectively. Thus, masks 24 and 26 are provided to make the needless part of the gate PN junction ineffective.