JPS5574181A - Preparing junction type field effect transistor - Google Patents

Preparing junction type field effect transistor

Info

Publication number
JPS5574181A
JPS5574181A JP14835478A JP14835478A JPS5574181A JP S5574181 A JPS5574181 A JP S5574181A JP 14835478 A JP14835478 A JP 14835478A JP 14835478 A JP14835478 A JP 14835478A JP S5574181 A JPS5574181 A JP S5574181A
Authority
JP
Japan
Prior art keywords
layer
area
type
diffused
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14835478A
Other languages
Japanese (ja)
Other versions
JPS6117154B2 (en
Inventor
Kosuke Yasuno
Tatsunori Nakajima
Kazutoshi Nagano
Kosei Kajiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP14835478A priority Critical patent/JPS5574181A/en
Publication of JPS5574181A publication Critical patent/JPS5574181A/en
Publication of JPS6117154B2 publication Critical patent/JPS6117154B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE: To prevent gm from decreasing through a reduced isolation diffusion by allowing the main part to be formed from two epitaxial layers containing channel area.
CONSTITUTION: p-Type epitaxial layer 9 is formed on the surface of p+-type semiconductor substrate 8. On the layer 9, n-type epitaxial layer 10 is formed to be used for channel. Then, p-type impurity is diffused from the surface of the layer 10 to form isolation diffusion layer 11 having a nesessary depth to cross the layer 10. Next, p+-type epitaxial layer 12 is formed on the layer 10. This allows the layer 12 and the area 11 to be electrically connected. Next, oxide films 17 are formed to insulate and isolate the area 13 corresponding to the surface of isolation diffusion area from the layer 12 which will later form the source area 14, the gate area 15, and the drain area 16. Then, n-type impurity is diffused into the source area 18 and the drain area 19. At this time, the n-type impurity is diffused in a concentration higher than the concentration of holes within the layer 12, allowing convertions to n+-type. The method requires only the thickness of the channel to isolate the area 4. As a result, heat treatment is reduced and thus gm is prevented from decrease.
COPYRIGHT: (C)1980,JPO&Japio
JP14835478A 1978-11-29 1978-11-29 Preparing junction type field effect transistor Granted JPS5574181A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14835478A JPS5574181A (en) 1978-11-29 1978-11-29 Preparing junction type field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14835478A JPS5574181A (en) 1978-11-29 1978-11-29 Preparing junction type field effect transistor

Publications (2)

Publication Number Publication Date
JPS5574181A true JPS5574181A (en) 1980-06-04
JPS6117154B2 JPS6117154B2 (en) 1986-05-06

Family

ID=15450875

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14835478A Granted JPS5574181A (en) 1978-11-29 1978-11-29 Preparing junction type field effect transistor

Country Status (1)

Country Link
JP (1) JPS5574181A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09213712A (en) * 1996-01-30 1997-08-15 Nec Corp Junction-type field effect transistor and method of the same
US6362079B1 (en) * 1997-06-06 2002-03-26 Kabushiki Kaisha Tokai Rika Denki Seisakusho Semiconductor device and method of anodization for the semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63131848A (en) * 1986-11-20 1988-06-03 Takara Co Ltd Cylinder inside processing method for toy engine

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09213712A (en) * 1996-01-30 1997-08-15 Nec Corp Junction-type field effect transistor and method of the same
US6362079B1 (en) * 1997-06-06 2002-03-26 Kabushiki Kaisha Tokai Rika Denki Seisakusho Semiconductor device and method of anodization for the semiconductor device

Also Published As

Publication number Publication date
JPS6117154B2 (en) 1986-05-06

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