JPS58153370A - Mos transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain the MOS element having small source-drain junction capacity, and moreover having the small short channel effect and the quasi-floating substrate effect using a substrate of normal concentration by a method wherein a low impurity concentration region is provided on the surface coming in contact with a gate insulating film of the semiconductor substrate shallowly at the part to face with a gate electrode, and moreover deeply at the source-drain region forming parts. CONSTITUTION:A thick field oxide film 3 is formed at the circumference of the p type Si substrate 1, the thin gate oxide film 2 is adhered on the surface of the substrate 1 surrounded with the film thereof, P ions are implanted therein to make the shallow P type region 4 to compensate for B in the surface of the substrate 1 and having low concentration equivalently to be generated. Then the gate electrode 5 consisting of polycrystalline Si is formed on the surface at the central part of the film 2, P ions are implanted again to convert only the regions 4 on both the sides of the electrode 5 into the deep and low concentration P type regions 6, and As ions of high concentration are implanted therein to form N type source and drain regions 8 on both the sides of the electrode 5.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a MOS (MOS) transistor having a small source/drain junction capacitance and a weak short channel effect, and a method for manufacturing the same.

The so-called scaling law is well-known as an index for miniaturization of MOS transistors. The scaling law requires an increase in substrate concentration as the size decreases, but if this is implemented, the junction capacitance per unit area of diffusion layers such as sources and drains will increase, and the substrate effect will not affect transistor characteristics. No improvement. These are high performance L
This is an unfavorable phenomenon in realizing SI'i, and efforts have been made to obtain lower junction capacitance and substrate effect.

The most common example is to create a MOS transistor on a lightly doped substrate and control the threshold voltage (7 transistors) by doping the channel. This method can relatively easily create a MOS resistor with low junction capacitance and low substrate effects, and in particular, for short channels, deep channel doping for punch-through prevention and shallow channel doping for vT control are required. Good results have been obtained by combining them. However, with this method,
There is a limit to the shortening of C1 channels, for example, when the effective channel length approaches 11IIn, a considerable amount of channel doping must be implanted to prevent punch-through, and the junction capacitance and substrate effect inevitably increase. .

Furthermore, when such a lightly doped substrate is used, the channel doped layer has a high resistance and is connected to the substrate bias power supply or ground, making it almost equivalent to an electrically floating state. Therefore, a weak avalanche occurs at the drain end, and when carriers of the opposite type to the conduction carriers are injected into the substrate, bipolar operation occurs and the drain breakdown voltage decreases, or due to the charge bombing phenomenon, carriers of the same type as the conduction carriers is injected into the substrate, an apparent upward substrate bias is added, and it becomes the same as 9, causing various problems such as the height of the 7th column (called the suspended substrate effect).

Therefore, the purpose of the present invention is to suppress the source/drain junction capacitance to a sufficiently low value for practical use while using a substrate with a normal concentration (t'), and to create a MOS (MOS) with little short channel effect and suspended substrate effect.
The object of the present invention is to provide a transistor and a manufacturing method that can easily and reliably realize such a MOS transistor.

The MOS) transistor according to the present invention has an impurity l1111 directly under the source/drain diffusion layer and directly under the gate insulating film.
There is a layer with a very low wIL, and the surface of this layer in contact with the substrate semiconductor in each region, that is, the boundary surface, is not flat but has a step, and only the boundary surface in the region directly under the gate insulating film has an edge surface. It is characterized by the fact that it exists nearby, and by using a substrate with a relatively high concentration, the above purpose can be achieved late. Further, in the manufacturing method of the present invention, first, a gate insulating film is formed on a first conductivity type semiconductor substrate, and then a second conductivity type 9 impurity is implanted by ion implantation to form a gate electrode. In each region, impurities of the second conductivity type are implanted somewhat deeply at an ion implantation amount selected to compensate for the substrate impurities, and then impurities of the @2 conductivity type are ion-implanted shallowly and at a high concentration to form the source. , forming a drain is a 4I feature, and exhibits an outstanding effect in easily and reliably manufacturing a MOS/MOS transistor having the structure of the present invention.

The structure and manufacturing method of a typical embodiment of the present invention will be explained below with reference to the drawings. In the embodiment, an N-channel MOS transistor will be described for convenience of explanation, but a P-channel MOS transistor is essentially the same, and both are naturally included in the present invention.

1st! g(m)t! , non-IA item 11 [5x1ots/-
A field oxide film 3 is formed on a p-type substrate 1 by normal LOCO 8 oxidation, and then a gate oxide film 2 of about 400X is grown, and phosphorous is ion-implanted at an energy of 150 KeV to remove the borosiness on the surface of the substrate 1. / is compensated to form a low concentration region 4 isometrically. The amount of phosphorus injected at this time needs to be carefully selected because it will be K if the final 7 guns are controlled, but in this example it was set to I x 10"/cIRs. 1lK
Figure 1 (b) shows that polysilicon of approximately s o o o x is grown and a polysilicon gate 5 is formed using resist as a mask.
After forming phosphorus y2.5 at an energy of 400KeV
This is a state in which a region 6 with an isometrically low impurity concentration is formed by implanting at about X 10 "7'am". At this time, since it is combined with the already formed low concentration region 4, the entire low source region is integrated into one as shown in the figure.

Figure 1(C) shows that after removing the resist in Figure 1(b), arsenic was added 1x at an energy of 100 KeV.
This is the state in which implantation and source and drain diffusion layers 8 have been formed by approximately 101·15+3. FIG. 1(d) shows a state in which a CVD film 9 is further grown, contact holes are opened, and metal wiring 10 is applied. This figure 1(d)
is a typical example of the structure of the present invention.

Although the MOS transistor with the structure of the present invention uses a relatively highly doped substrate, as shown in FIG. Spread over almost all areas. This situation was analyzed using a two-dimensional analysis program using the parameters of the above embodiment, and nine examples are shown in FIG. Second
In the figure, 11 is a silicon substrate, 12 is a source, 13 is a drain, 14 is a gate electrode, 15Fi gate oxide film, 16#
'' is the equipotential, 17ij is the depletion layer edge. Here, the gate voltage is 2V and the drain voltage is 1V.

As is clear from Figure 2, there is approximately un*m@f in the depletion layer on the source side, and in fact, the junction is as low as 5 x 10"/a*"g, which is the same level as when the source is made on a vertical substrate. capacity. In addition, a depletion layer of 13 μm wide under the gate weakens the p1 substrate bias effect. Nevertheless, these low sources [8 the boundary between the region and the substrate are
Due to the step, only the part directly under the gate is located near the surface as shown in Figure 1 (dl), so as shown in Figure 2, a relatively high concentration of impurities of 5X 10''/a1m is present under the gate. However, the rounding and short channel effects that suppress the elongation of the drain depletion layer are weakened.Moreover, the use of such a highly doped substrate also effectively suppresses the floating substrate effect, which is an outstanding effect. It is.

According to the manufacturing method of the present invention, extremely low impurity concentration regions can be provided directly under the source and drain diffusion layers and directly under the gate insulating film with the same number of ion implantations as in the conventional method! I can do it.

Furthermore, this low III! Of the interface between the doweling bin and the substrate,
The above structure can be obtained by performing self-unin to position only the portion immediately below the gate insulating film near the surface.

In the above description, for convenience of explanation, only one typical and simple embodiment has been described, but the present invention is not limited to such an embodiment. For example, the first
Figure (ml) In the low concentration layer 4, not only phosphorus but also boron or the like may be doubly implanted to control the final VTt with more precision.

Father, Figure 1 (When forming the low concentration region 6 with BL, there is no need to leave the resist 7 if the polysilicon gate 5 is 7000A or more.Such a modification is naturally included in the present invention.

[Brief explanation of drawings]

FIG. 1 (13 to d) are main cross sections showing a typical example of the method for manufacturing MO8 transistors of the present invention in the order of steps;
This figure is a diagram showing the potential distribution of the MOS transistor of the ninth embodiment shown in FIG. 1. 1... Silicon substrate 2... Gate oxide film 5.
...Field oxide film 4...Shallow low impurity concentration region 5...Gate polysilicon 6...Deep low impurity concentration region 7...Resist 8...Source and drain! ...CVD oxide film 10...Metal wiring patent applicant NEC Corporation Figure 1 (b)

Claims (2)

[Claims] (1) A semiconductor with a very low impurity concentration is made to exist directly under the source and drain diffusion layers formed on the semiconductor substrate and directly under the gate insulating film, and each region of this extremely low concentration semiconductor layer and the substrate A MOS transistor is characterized in that it has a WJK step in contact with a semiconductor, and that the surface immediately below the gate insulating film is located near the surface. (2) A gate insulator jIK is formed on the first conductive lid semiconductor substrate, and then a 24th conduction type impurity is implanted near the surface by ion implantation to form a gate electrode, and a gate insulator jIK is formed slightly deeper by ion implantation. By implanting two conductivity type impurities, each
1. A method of manufacturing a MOS transistor, which comprises compensating the impurity concentration of a substrate and ion-implanting a 24th type impurity into the corresponding wall shallowly and at a high concentration to form a source and a drain.゛