JPH01268171A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent irreversible breakdown in a high breakdown strength field effect transistor structure and to properly hold the value of a transistor conductance by providing a second conductivity type second low concentration impurity diffused region for forming a junction to a high concentration impurity region. CONSTITUTION:A second conductivity type first low concentration impurity diffused region 8 is formed between at least any one of high concentration source, drain regions 4, 7 and a gate region in a first conductivity type substrate 1 in a state that the gate region 7 and the regions 4, 7 at both sides of the gate region are provided, and a second conductivity type second low concentration impurity diffused region 9 for forming a junction to a first conductivity type high concentration impurity region 3 is provided adjacent to the source, drain regions provided with the region 8. The impurity concentrations of the regions for forming the junctions are optimized to move an electric field concentration generated when a bias voltage is applied to the drain region from the left or right end of the first low concentration impurity diffused region to the junction between the high concentration impurity region and the second low concentration impurity diffused region.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and more specifically, to a high voltage field effect transistor structure that prevents irreversible breakdown when a bias voltage is applied to the drain. This relates to an improved structure to prevent this.

[Conventional technology]

As a conventional high-voltage field effect transistor structure of this type, for example, FIG. Shown below.

That is, in the field effect transistor configuration according to the conventional example shown in FIG.
2 and 2a are thick field oxide films for isolation between elements formed on the main surface of this P-type silicon substrate 1.

Further, numeral 3 denotes a P-type isolation region for a channel stopper provided in a part directly under the field oxide film 2, and 4 an N+ type isolation region formed on the main surface of the P-type silicon substrate 1.
5 is a thin gate oxide film formed on the same main surface, 6 is a gate electrode formed thereon and extending on the thick oxide film 2a to form a gate region, and 7 is a gate electrode formed on the thick oxide film 2a. An N+ type drain region 8 is formed opposite to the N++ source region 4 with the gate region in between, and 8 is a region between the gate region and the N+ type drain region 7, which is covered with the thick oxide film 2a. The formed first N- type impurity diffusion region 9 surrounds and adjoins a portion of the N+ type drain region excluding the first N- type impurity diffusion region 8, and is connected to the vi type isolation region 3. A second N-type impurity diffusion region is formed with a predetermined distance therebetween.

In the case of this conventional configuration, in order to turn on the transistor, a predetermined positive bias voltage (usually about 5 V) is applied to the gate electrode 6 while the P-type silicon substrate I and the N++ source region 4 are held at Ov. ), electrons pass from this N+ type source region A, through the channel region formed directly under the gate oxide film 5, and through the first N- type impurity diffusion region 8, and then enter the N+ type drain region A. Region 7 is reached and current flows in this way.

On the other hand, if the P-type silicon substrate 1, the N++ source region 4, and the gate electrode 6 are held at Ov, and a positive bias voltage is applied to the N+-type drain region 7 in this state, the first An electric field is concentrated at the left end or right end of the N-type impurity diffusion region 8, and here, the so-called
This will result in avalanche breakdown.

[Problem to be solved by the invention]

In the conventional device having the above configuration, as described above, when a positive bias voltage is applied to the N+ type tray region 7, the left end or right end portion of the first N− type impurity diffusion region 8 This will cause electric field concentration to occur, but in this case,
On the other hand, if the impurity concentration is increased to avoid electric field concentration in the first N- type impurity diffusion region 8, there is a risk that the device itself will be irreversibly destroyed.
When the impurity concentration of the N- type impurity diffusion region 8 is lowered,
There was a problem in that this resulted in high resistance and the gm (h-lance conductance) of the device itself deteriorated.

This invention was made to solve these conventional problems, and its purpose is to prevent irreversible breakdown in a high-voltage field effect transistor structure, and at the same time, to reduce the value of gm. I made it possible to maintain it properly. An object of the present invention is to provide a semiconductor device of this type.

[Means to solve the problem]

In order to achieve the above object, a semiconductor device according to the present invention provides a semiconductor device that is adjacent to at least one of a substrate of a predetermined conductivity type or a high concentration source/drain region of an opposite conductivity type provided on a well. A low concentration impurity diffusion region of an opposite conductivity type is provided to form a junction between the high concentration impurity region of the same conductivity type and serving as a channel stopper.

That is, the present invention provides a thin gate oxide film on a main surface of a substrate or well of the first S conductivity type separated by an element isolation oxide film and a high concentration impurity region of the first conductivity type immediately below the element isolation oxide film. , a gate region consisting of a gate electrode thereon, and a highly doped source region of a second conductivity type and a drain region sandwiching this gate region. A first low concentration impurity diffusion region of the second conductivity type covered with a thick oxide film is provided between at least one of the gate regions and the gate region, and a source provided with the first low concentration impurity diffusion region This semiconductor device is characterized in that a second low concentration impurity diffusion region of a second conductivity type is provided adjacent to the drain region and the drain region to form a junction with the high concentration impurity region.

[For production]

Therefore, in the device of the present invention, the substrate of the first conductivity type,
Alternatively, with a gate region and high concentration source/drain regions of the second conductivity type provided on both sides of the gate region, at least one of these high concentration regions and the gate region are provided. A first low-concentration impurity diffusion region of the second conductivity type is provided between the regions, and a junction is formed between the first low-concentration impurity region of the first conductivity type and adjacent to each source/drain region in which the same region is provided. a second conductivity type forming a second
By optimizing the impurity concentration of each region that forms these junctions, the electric field concentration that occurs when a bias voltage is applied to the drain region can be reduced. The left end of the first low concentration impurity diffusion region.

Alternatively, it can be transferred from the right end portion to the junction between the high concentration impurity region and the second low concentration impurity diffusion region. By setting it somewhat lower, the withstand voltage of the device,
In addition, it is possible to maintain an appropriate gm value and prevent its irreversible destruction.

〔Example〕

Hereinafter, different embodiments of the semiconductor device according to the present invention will be described in detail with reference to FIGS. 1 and 2.

FIG. 1 is a cross-sectional configuration diagram schematically showing the outline of a field effect transistor to which an embodiment of the device of the present invention is applied. In the configuration of the embodiment shown in FIG. Indicates the same or equivalent parts.

That is, also in the embodiment shown in FIG. 1, the symbol l is a P-type silicon substrate (or well), and
, 2a are thick field oxide films formed on the main surface of the P-type silicon substrate 1 for isolation between elements.

Further, reference numeral 3 indicates a p-type isolation region (high concentration impurity diffusion region) for a channel stopper provided in a portion directly under the field oxide film 2, and 4 a p-type isolation region (high concentration impurity diffusion region) formed on the main surface of the above-mentioned p-type silicon substrate l. 5 is a thin gate oxide film formed on the main surface, 6 is a gate electrode formed thereon and extends on the thick oxide film 2a to form a gate region, and 7 is an N1 type source region. The N
This is an N9 type drain region formed opposite to the + type resource region.

Furthermore, 8 is a first region formed between the gate region and the N" type drain region 7 and covered with the thick oxide film 2a.
The N- type impurity diffusion region 9 surrounds and adjoins a portion of the N+ type drain region excluding the first N- type impurity diffusion region 8, and is adjacent to the P+ type isolation region 3.
This is a second N- type impurity diffusion region formed in contact with.

Therefore, in this embodiment configuration, in order to turn on the transistor, a predetermined positive bias voltage (usually about 5 V) is applied to the gate electrode 6 while the P type silicon substrate 1 and the N+ type resource region 4 are held at Ov. When is applied, electrons pass from this N+ type resource region 4, through the channel region formed directly under the gate oxide film 5, to the first N- type impurity, as in the case of the conventional configuration described above. After passing through the diffusion region 8, it reaches the N+ type drain region 7, and thus current flows.

On the other hand, if the P type silicon substrate 1 and the N+ type resource region 4 gate electrode 6 are held at Ov and a positive bias voltage is applied to the N+ type drain region 7 in this state, in this S. By optimizing the impurity concentrations of the P+ type isolation region 3 and the second N- type impurity diffusion region 9, in the case of the conventional configuration described above, the first N- type impurity diffusion region 8 can be The electric field concentration occurring at the left end or right end portion can be moved to the junction between the second N- type impurity diffusion region 9 and the P+ isolation region 3; The breakdown voltage at the junction between the second N- type impurity diffusion region 9 and the P+ isolation region 3 is somewhat lower than the breakdown voltage at the left end or right end of the - type impurity diffusion region 8. By setting in this way, irreversible destruction of the device can be prevented without significantly lowering the withstand voltage of the device itself, and even the value of gm.

In the configuration of the embodiment shown in FIG. 1, the thick oxide film 2a and the first . Although the second N-type impurity diffusion regions 8 and 9 are formed,
As shown in the configuration of the embodiment in FIG.
They may be formed in exactly the same way, even if they are on the side.
In this case, there is no problem in using either of the inner regions 4.7 as the source or the drain.

In addition, in each of the above embodiments, P-type silicon substrate I
However, P formed on an N-type silicon substrate
In addition, although each embodiment describes the case where it is applied to a k-channel field effect transistor, it can also be applied to a p-channel field effect transistor by setting the conduction type in the opposite way. similar effect,
Of course, it is effective.

(Effects of the Invention) As detailed above, according to the present invention, a gate region is formed on a substrate or a well of the first conductivity type.

In a field effect transistor having a second conductivity type high concentration source/drain region sandwiching the gate region, a second conductivity type is provided between at least one of these source/train regions and the gate region. A first low-concentration impurity diffusion region of a shape is provided, and the same region is adjacent to the provided source/drain region to form a junction with a high-concentration impurity region of a first conductivity type serving as a channel stopper. A configuration in which a second low concentration impurity diffusion region of the second conductivity type is provided, in other words, a high concentration impurity region of the first conductivity type and a second low concentration impurity diffusion region of the second conductivity type are bonded. By optimizing the impurity concentration of each of these regions, the electric field concentration that occurs when a bias voltage is applied to the drain region can be reduced by the first low concentration impurity diffusion. It can be easily transferred from the left end or right end of the region to the junction between the high concentration impurity region and the second low concentration impurity diffusion region.
If the breakdown voltage at the junction is set somewhat lower than the breakdown voltage at the first low concentration impurity diffusion region, the breakdown voltage and gm value of this type of field effect transistor will hardly decrease. In addition, it can effectively prevent irreversible destruction of the device, helping to improve its reliability, and has superior features such as being structurally simple and easy to implement when compared to conventional examples. .

[Brief explanation of the drawing]

1 and 2 are cross-sectional configuration diagrams schematically showing the outline of field effect transistors to which different embodiments of the device of the present invention are applied, and FIG. 3 is a diagram showing a field effect transistor according to a conventional example. FIG. 2 is a cross-sectional configuration diagram schematically showing an outline of an effect transistor. l...P-type silicon substrate (P-type well), 2.2a
...Thick field oxide film, 3...P+ type isolation region (high concentration impurity diffusion region), 4...
- N+ type resource regions 5 and 6...thin gate oxide film and gate electric field Fj (gate region), 7...
N++ drain region, 8... first N- type impurity diffusion region, 9... second N- type impurity diffusion region. Agent Masu Oiwa Showa Year/Month [1 1. Indication of the case Japanese Patent Application No. 63-97578 2. Title of the invention Semiconductor device 3. Tenant making the amendment Detailed description of the invention in the specification list subject to amendment 6. Contents of correction (1) F! On page 3, line 15 of the A specification, add ``A predetermined positive bias voltage (usually about 5 V) is applied to the N+ drain region I'' after ``while holding the voltage at ''. 2) Correct "value of r gm" on page 15, line 5 to "value of gm and breakdown voltage." (3) In the same book, page 9, line 8, ``1 after j while holding it in
A predetermined positive bias voltage (usually
5V) and add ". that's all

Claims (1)

[Claims] In the substrate or well of the first conductivity type, on the principal surface separated by the element isolation oxide film and the high concentration impurity region of the first conductivity type immediately below the element isolation oxide film, a thin gate oxide film and a gate electrode on the main surface are separated. A field effect transistor structure including a gate region consisting of a gate region, a second conductivity type high concentration source region, and a drain region sandwiching the gate region, at least one of the source region and the drain region;
A first low concentration impurity diffusion region of a second conductivity type covered with a thick oxide film is provided between the gate region and the first low concentration impurity diffusion region is provided adjacent to the source region and the drain region. A semiconductor device further comprising: a second low concentration impurity diffusion region of a second conductivity type forming a junction with the high concentration impurity region.