JPS6083365A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6083365A JPS6083365A JP58191480A JP19148083A JPS6083365A JP S6083365 A JPS6083365 A JP S6083365A JP 58191480 A JP58191480 A JP 58191480A JP 19148083 A JP19148083 A JP 19148083A JP S6083365 A JPS6083365 A JP S6083365A
- Authority
- JP
- Japan
- Prior art keywords
- type
- resistance
- region
- polycrystalline silicon
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000009792 diffusion process Methods 0.000 claims abstract description 12
- 230000005669 field effect Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052782 aluminium Inorganic materials 0.000 abstract description 8
- 238000005468 ion implantation Methods 0.000 abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 6
- 239000011229 interlayer Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 description 5
- 230000003068 static effect Effects 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は半導体装置に関し、特にスタティックＲＡＭ’
ｒ有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a semiconductor device, and in particular to a static RAM'.
The present invention relates to a semiconductor device having r.
従＊ ズｉ千ノ、、、 ／＞ Ｒ，Ａ Ｍ−ｈル翔ζｆ
）伯庸子ＦＭテプレッション型ＭＯＳトランジスタや高
抵抗多結晶シリコン素子が用いられていた。Follow * zu i thousand,,, //> R, A M-h le sho ζf
) Hakuyoko FM depression type MOS transistors and high-resistance polycrystalline silicon elements were used.
デプレッション型ＭＯ８ト９ンジスタをＲＡＭセルの負
荷に使用する場合（以下このＭＯＳ）ラン、リスタを負
荷ＭＯ８と記す）、消費電流を抑制するためには、非常
に長いゲート長が必要となり、高集積度化には非常に不
利でおる。When a depletion type MO8 transistor is used as the load of a RAM cell (hereinafter referred to as MOS), the run and lister are referred to as load MO8), a very long gate length is required in order to suppress current consumption, and a highly integrated It is very disadvantageous for deterioration.
最近工は、負荷ＭＯ，９の代わりに高抵抗多結晶シリコ
ン素子が負荷として用いられるようになってきた。Recently, a high resistance polycrystalline silicon element has been used as a load instead of the load MO,9.
第１図は従来の高抵抗多結晶シリコン素子をセル部の負
荷として用いたスタティックＲ，ＡＭの新興−でやる。Figure 1 shows an emerging static R/AM system using a conventional high-resistance polycrystalline silicon element as a load in the cell section.
ｐ型半導体基板１上にフィールド酸化膜２及び絶縁酸化
膜３を形成し、絶縁酸化膜３上にゲート馬極４を形成し
、自己整合的にソース及びドレインとなるわ＋拡散領域
５をヒ素イオン打込み法により形成し、これによ沙形成
されだｎ＋拡散領域５上の絶縁酸化膜に高抵抗素子接合
用開孔部６’５形成し、高抵抗素子用の不純物低ドーズ
多結晶シリコン層を形成し、抵抗接合開孔部６及び１０
の領域を覆うようにヒ素イオン打込みにより低抵抗多結
晶シリコン領域８を形成し、層間絶縁膜９を形成したの
ち、アルミニウム接合開孔部１０を形成し、アルミニウ
ム電極１１を形成することにより得られる。A field oxide film 2 and an insulating oxide film 3 are formed on a p-type semiconductor substrate 1, and a gate pole 4 is formed on the insulating oxide film 3 to become a source and a drain in a self-aligned manner. A low-dose impurity polycrystalline silicon layer for high-resistance elements is formed by ion implantation, and a high-resistance element junction opening 6'5 is formed in the insulating oxide film on the n+ diffusion region 5 formed by this method. and resistive junction apertures 6 and 10
A low resistance polycrystalline silicon region 8 is formed by arsenic ion implantation so as to cover the region, an interlayer insulating film 9 is formed, an aluminum junction opening 10 is formed, and an aluminum electrode 11 is formed. .
なお、低抵抗多結＋ｉ＆シリコン領域８を形成する理由
は、抵抗接合開孔部６０周辺には拡がり抵抗が介在し、
この抵抗値は接合開孔部６の形状に大きく依存するため
に、再現性の良い高抵抗素子を形成するために拡がり抵
抗を肩する抵抗接合開孔部６の周囲を低抵抗化しなけれ
はならない。The reason for forming the low-resistance multi-connection +i & silicon region 8 is that a spreading resistance exists around the resistance junction opening 60.
Since this resistance value largely depends on the shape of the junction opening 6, in order to form a high-resistance element with good reproducibility, it is necessary to reduce the resistance around the resistance junction opening 6, which shoulders the spreading resistance. .
さらに、抵抗接合開孔部１０においては、アルミニウム
電極１１を形成する前に行なうリン拡散でリンネ細物が
抵抗接合開孔部１０から拡散し、高濃度不純物領域が拡
がるために、尚抵抗素子の有効抵抗長が、熱処理などに
大きく依存し、安定に高抵抗素子を作ることができなく
なるため、このリンネ細物拡散勿光分見込んだ低抵抗領
域を形成しておかなけれはならない。しかも、従来例で
示される構造では、前述の理由のために低抵抗多結晶シ
リコン領域８を形成しなければならなく、セル面積が非
常に大きくなるだけでなく低抵抗多結晶シリコン領域８
を選択的に形成するためのホトレジスト工程及び、低抵
抗多結晶シリコン領域８形成のイオン打込み工程が増す
ために、非効率的でおるというような多くの欠点を有し
ていた。Furthermore, in the resistance junction opening 10, phosphorus particles are diffused from the resistance junction opening 10 by phosphorus diffusion performed before forming the aluminum electrode 11, and the high concentration impurity region expands. Since the effective resistance length largely depends on heat treatment and the like, making it impossible to stably produce a high-resistance element, a low-resistance region must be formed that takes into account the amount of light diffused by the Linnean thin material. Moreover, in the structure shown in the conventional example, it is necessary to form the low resistance polycrystalline silicon region 8 for the above-mentioned reason, and not only does the cell area become very large, but also the low resistance polycrystalline silicon region 8 has to be formed.
It has many drawbacks such as inefficiency due to the increased photoresist process for selectively forming the polycrystalline silicon region 8 and the ion implantation process for forming the low resistance polycrystalline silicon region 8.
本発明の目的は、以上の欠点を除去し、構造が簡単で制
御性がよく、小型化に好都合な負荷抵抗素子を有する半
導体装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks, and to provide a semiconductor device having a load resistance element that has a simple structure, good controllability, and is convenient for downsizing.
本発明の半導体装置は、第１導電型の半導体基板上に形
成されたＭＯ８型電界効果トランジスタのソース又はド
レイン領域となる拡散層の少なくとも一部と直接接続さ
れ、かつ前記半導体基板の少なくとも一部と直接接続さ
れて形成された第２導電型の多結晶シリコン層から成る
抵抗素子を含んで構成される。The semiconductor device of the present invention is directly connected to at least a portion of a diffusion layer serving as a source or drain region of an MO8 field effect transistor formed on a semiconductor substrate of a first conductivity type, and at least a portion of the semiconductor substrate. The resistive element includes a resistive element made of a second conductivity type polycrystalline silicon layer formed in direct connection with the resistive element.
以下、本発明の実施例について、図面を参照して説明す
る。Embodiments of the present invention will be described below with reference to the drawings.
第２図１ａ）〜ｉｆ）は本発明の一実施例の製造方法を
説明する丸めの工程順に示した断面図である。FIGS. 2a) to 1f) are cross-sectional views shown in the order of rounding steps to explain a manufacturing method according to an embodiment of the present invention.
本発明の一実施例の半導体装置は以下の工程により製造
することが出来る。A semiconductor device according to an embodiment of the present invention can be manufactured by the following steps.
先ず、第２図（ａ）に示すように、ｐ型半導体基板ン１
上にフィールド酸化膜２２を形成する。First, as shown in FIG. 2(a), a p-type semiconductor substrate 1 is
A field oxide film 22 is formed thereon.
次に、第２図１ｂ）に示すように、絶縁酸化膜２３を形
成した後、絶縁酸化膜２３上のｆ９「定領域にゲート電
極２４を形成する。Next, as shown in FIG. 2B, after forming an insulating oxide film 23, a gate electrode 24 is formed in the f9 constant region on the insulating oxide film 23.
次に、第２図（Ｃ）に示すように、ＭＯ８型トランジス
タのドレイン領域に隣接してｐ低額城門残すためイオン
打込み阻止ホトレジスト３２を形成した後、ヒ素イオン
注入を半導体基体全面に咎なうことによりｎ十拡散領域
２５．２５’を形成しドレインおよびソース領域とする
。Next, as shown in FIG. 2C, after forming an ion implantation blocking photoresist 32 to leave a low-p gate adjacent to the drain region of the MO8 transistor, arsenic ions are implanted over the entire surface of the semiconductor substrate. As a result, n+ diffusion regions 25 and 25' are formed to serve as drain and source regions.
次に、第２図（ｄ）Ｋｉ示すように１Ｍ０ｆＳ型トラン
ジスタのドレイン領域であるｎ十拡散領域２６及びこれ
に１１１１＠１−だ０刑側域の某旙害面μの一揚酸什膜
２３の少なくとも一部を除去するだめに、ホトレジスト
膜３３を形成したのち、選択除去を行なうことにより、
抵抗接合開孔部２６を形成する。Next, as shown in FIG. 2(d) Ki, there is a diffusion region 26 which is the drain region of the 1M0fS type transistor, and a certain damaged surface μ of the 1111@1-0 region on this. In order to remove at least a portion of 23, after forming a photoresist film 33, selective removal is performed.
A resistance junction opening 26 is formed.
次に、第２図ｔｅ）に示すように、抵抗接合開孔部２６
において、ＭＯ８型トランジスタのドレイン領域である
ｎ＋拡散領域２５とこれに隣接するｐ低額域との両方に
、少なくとも一部で直接接触するように多結晶レリコン
層２７を形成したのち、ｎ型不純物イオン打込みを行な
い多結晶シリコン層２７をｎ型にする。Next, as shown in FIG.
After forming a polycrystalline relicon layer 27 so as to be in direct contact at least partially with both the n+ diffusion region 25, which is the drain region of the MO8 type transistor, and the adjacent p low-density region, n-type impurity ions are formed. An implant is performed to make the polycrystalline silicon layer 27 n-type.
次に、第２図（ｒａｍ示すように、層間絶縁膜２９を半
導体基体全面に形成した後、アルミニウム接合開孔部３
０を形成し、アルミニウム電極３１を形成することによ
り本実施例は実現できる。Next, as shown in FIG. 2 (RAM), after forming an interlayer insulating film 29 on the entire surface of the semiconductor substrate,
This embodiment can be realized by forming the aluminum electrode 31 and forming the aluminum electrode 31.
以上により得られた本実施例は、ｎ型の多結晶シリコン
Ｎ２７と抵抗接合開孔部２６とが直接接触する部分にお
いて、接合型Ｆｌ（Ｔを形成し、抵抗接合開孔部２６の
部分ｐｎ接合には逆方内法なる向きのバイアス電圧がか
かるので接合部の空乏層はｐ型の基板幀域からｎ型の多
結晶シリコン層２７へと拡がり、ｎ型の多結晶シリコン
層２７は空乏漸拡がりによるピンチオフ抵抗となり抵抗
素子として作用する。In the present example obtained as described above, a junction type Fl (T is formed in the portion where the n-type polycrystalline silicon N27 and the resistance junction opening 26 are in direct contact with each other, and a portion pn of the resistance junction opening 26 is formed. Since a reverse bias voltage is applied to the junction, the depletion layer at the junction spreads from the p-type substrate region to the n-type polycrystalline silicon layer 27, and the n-type polycrystalline silicon layer 27 becomes depleted. It becomes a pinch-off resistance due to gradual expansion and acts as a resistance element.
また、ピンチオフ抵抗は、ｎ＋拡散領域２５に隣接する
ｐ型頭域と直接接触している多結晶シリコン層２７の幅
と、多結晶シリコン層のｎ型不細物＃鼓に依存するため
に、その制御性は非常に良好である。なお空乏層の拡が
りに影響を与える多結晶シリコン層２７へのｎ型不細物
濃ＩＷはイオン打込みのドーズ量により加減することが
できる。In addition, the pinch-off resistance depends on the width of the polycrystalline silicon layer 27 that is in direct contact with the p-type region adjacent to the n+ diffusion region 25 and the n-type impurities in the polycrystalline silicon layer. Its controllability is very good. Note that the concentration IW of n-type impurities in the polycrystalline silicon layer 27, which affects the spread of the depletion layer, can be adjusted by adjusting the dose of ion implantation.
また、本実施例は従来の負荷ＭＯ８や多結晶シリコン高
抵抗素子と全く別の機構によるものであり、その製造工
程は、極めて簡素であるはかりでなく、従来例のような
低抵抗領域を必要としないため、セルの面積を非常に小
さくできるなどの効果がある。In addition, this example has a completely different mechanism from the conventional load MO8 and polycrystalline silicon high resistance element, and its manufacturing process is not an extremely simple scale, but requires a low resistance region like the conventional example. This has the advantage that the area of the cell can be made extremely small.
なお、上記実施例はｎチャンネルＭＯ８型トランジスタ
の場合について示したが、ｐチャンネルＭＯ８型トラン
ジスタの場合も同様に適用できる。Note that although the above embodiments have been shown in the case of an n-channel MO8 type transistor, they can be similarly applied to the case of a p-channel MO8 type transistor.
以上説明したとおり、本発明によれば、構造が簡単で、
抵抗値の制御性がよく、小型化に好適な負荷抵抗素子を
備えた半導体装置が得られる。As explained above, according to the present invention, the structure is simple,
A semiconductor device having a load resistance element with good controllability of resistance value and suitable for miniaturization can be obtained.
第１図は従来の高抵抗多結晶シリコン素子ヶセル部の負
荷に用いたスタティックＲＡＭの断面図、第２図（ａ）
〜（ｆ）は本発明の一実施例を説明するための工程順に
示した断面図である。
１．２１・・・・・・ｐ型半導体基板、２．２２・・・
・・・フィールド酸化膜、３．２３・・・・・・絶縁酸
化膜、４゜２４・・・・・・ゲート電極、５，２５．２
５’・・・・・・計拡散領域、６．２６・・・・・・抵
抗接合開孔部、７．２７・・・・・・多結晶シリコン層
、８・・・・・・低抵抗多結晶／リコン領域、９．２９
・・・・・・層間絶縁膜、１０．３０・・・・・・アル
ミニウム接合開孔部、１１．３１・・・・・・アルミニ
ウム電極、３２・・・・・・イオン打込み阻止ホトレジ
スト膜、３３・・・・・・ホトレジスト膜。
代理人 弁理士 内 原 、 ？゛、ｆ；、＞１、 ７
１
第 Ｉ 閾
第 ２ 図
采２ 司Figure 1 is a cross-sectional view of a static RAM used for loading the conventional high-resistance polycrystalline silicon element cell section, and Figure 2 (a).
- (f) are sectional views shown in order of steps for explaining one embodiment of the present invention. 1.21...p-type semiconductor substrate, 2.22...
...Field oxide film, 3.23...Insulating oxide film, 4゜24...Gate electrode, 5,25.2
5'... Total diffusion region, 6.26... Resistance junction opening, 7.27... Polycrystalline silicon layer, 8... Low resistance Polycrystalline/recon region, 9.29
......Interlayer insulating film, 10.30...Aluminum junction opening, 11.31...Aluminum electrode, 32...Ion implantation blocking photoresist film, 33...Photoresist film. Agent Patent Attorney Uchihara ?゛, f;, >1, 7
1 Part I Threshold 2 Diagram 2 Tsukasa
Claims (1)
果トランジスタのソース址たはドレイン領域となる拡散
層の少なくとも一部と直接接続され、かつ前記半導体基
板の少なくとも一部と直接接続されて形成された第２導
電型の多結晶シリコン層から成る抵抗素子を含むことを
特徴とする半導体装置。Directly connected to at least a portion of a diffusion layer serving as a source or drain region of an NO8 field effect transistor formed on a first conductivity type semiconductor substrate, and directly connected to at least a portion of the semiconductor substrate. A semiconductor device comprising a resistance element formed of a second conductivity type polycrystalline silicon layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58191480A JPS6083365A (en) | 1983-10-13 | 1983-10-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58191480A JPS6083365A (en) | 1983-10-13 | 1983-10-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6083365A true JPS6083365A (en) | 1985-05-11 |
Family
ID=16275342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58191480A Pending JPS6083365A (en) | 1983-10-13 | 1983-10-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6083365A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8371419B2 (en) | 2008-04-22 | 2013-02-12 | 3M Innovative Properties Company | Hybrid sound absorbing sheet |
| US8469145B2 (en) | 2008-04-14 | 2013-06-25 | 3M Innovative Properties Company | Multilayer sound absorbing sheet |
| US8573358B2 (en) | 2008-05-22 | 2013-11-05 | 3M Innovative Properties Company | Multilayer sound absorbing structure comprising mesh layer |
-
1983
- 1983-10-13 JP JP58191480A patent/JPS6083365A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8469145B2 (en) | 2008-04-14 | 2013-06-25 | 3M Innovative Properties Company | Multilayer sound absorbing sheet |
| US8371419B2 (en) | 2008-04-22 | 2013-02-12 | 3M Innovative Properties Company | Hybrid sound absorbing sheet |
| US8573358B2 (en) | 2008-05-22 | 2013-11-05 | 3M Innovative Properties Company | Multilayer sound absorbing structure comprising mesh layer |
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