JPH1041501A - Dmos fet - Google Patents
Dmos fetInfo
- Publication number
- JPH1041501A JPH1041501A JP8189230A JP18923096A JPH1041501A JP H1041501 A JPH1041501 A JP H1041501A JP 8189230 A JP8189230 A JP 8189230A JP 18923096 A JP18923096 A JP 18923096A JP H1041501 A JPH1041501 A JP H1041501A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- drain
- electric field
- withstand voltage
- concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 230000005684 electric field Effects 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims description 9
- 230000003247 decreasing effect Effects 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 15
- 239000010410 layer Substances 0.000 description 94
- 239000012141 concentrate Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000004088 simulation Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、微弱信号を高速で
切り換える半導体リレーの接点として使用されるＤＭＯ
Ｓ ＦＥＴの出力端子間容量を少なくし、高耐圧化する
改良に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMO used as a contact of a semiconductor relay for switching a weak signal at a high speed.
The present invention relates to an improvement in reducing the capacitance between output terminals of an SFET and increasing the breakdown voltage.
【０００２】[0002]
【従来の技術】ＬＳＩテスタ等では測定信号その他の微
弱信号を高速で多量に切り換えるため、巨大なリレーマ
トリクスを構成する必要があり半導体リレーが使用され
る。この切り換えのためのスイッチ素子としてＤＭＯＳ
ＦＥＴが用いられる。図５は従来のＤＭＯＳ ＦＥＴ
の構造を示す断面図である。１は低濃度のｐ-半導体基
板である。（以下ｐ-、ｎ+等は一例を示す。） ２は半導体基板１の１つの面に一定の幅をもって細長く
且つその両端部を円弧形に形成した高濃度のｎ+半導体
ドレイン層である。３はボンデイングパッド部である。
４はドレイン電極である。この電極とドレイン層２との
接合部は隙間に絶縁膜を充填するなど損傷防止の構造に
する。このドレイン電極４の上に配線用のボンデイング
パッドが作られる。ドレイン層２からドレイン電極４ま
でを含めてドレインと呼ぶことがある。、５ａ、５ｂは
ドリフトチャンネル層である。ドレイン層２を中に配置
し所定の耐電圧値が得られるようドレイン層２の縁から
一定の幅（ドリフトチャンネル長Ｌｄと言う。）をもっ
てドレイン層２と相似形に形成する。また、ＤＭＯＳ
ＦＥＴの耐圧を低下させずに導通時のオン抵抗を下げる
ために、ドリフトチャンネル層を二分してドレイン層２
側（５ａ）の不純物濃度をソース層６側（５ｂ）の不純
物濃度より高くしてその境界をほぼ中央におく。2. Description of the Related Art In an LSI tester or the like, a large relay matrix must be formed in order to switch a large number of measurement signals and other weak signals at high speed, and semiconductor relays are used. DMOS as a switch element for this switching
An FET is used. FIG. 5 shows a conventional DMOS FET
FIG. 3 is a cross-sectional view showing the structure of FIG. 1 is a low-concentration p - semiconductor substrate. (Hereinafter, p − , n +, etc. are examples.) Reference numeral 2 denotes a high-concentration n + semiconductor drain layer which is elongated on one surface of the semiconductor substrate 1 with a constant width and has both ends formed in an arc shape. . 3 is a bonding pad part.
4 is a drain electrode. The junction between the electrode and the drain layer 2 has a structure for preventing damage, such as filling a gap with an insulating film. A bonding pad for wiring is formed on the drain electrode 4. The drain from the drain layer 2 to the drain electrode 4 may be called a drain. Reference numerals 5a and 5b denote drift channel layers. The drain layer 2 is disposed inside and is formed in a shape similar to the drain layer 2 with a certain width (referred to as a drift channel length Ld) from an edge of the drain layer 2 so as to obtain a predetermined withstand voltage value. Also, DMOS
In order to reduce the ON resistance during conduction without lowering the withstand voltage of the FET, the drift channel layer is divided into
The impurity concentration on the side (5a) is higher than the impurity concentration on the source layer 6 side (5b), and the boundary is set substantially at the center.
【０００３】６はドリフトチャンネル層５ｂの外側に形
成したＰベース層である。７はＰベース層６の中に形成
した高濃度のｎ+半導体層である。８はＰベース層６の
中に形成した高濃度のｐ+半導体層である。９は高濃度
のｎ+半導体層７及び高濃度のｐ+半導体層８に共通のソ
ース電極である。これらの部分を一括してソースと言う
ことがある。１０は酸化膜である。１１はＰベース層か
ら前記ドリフトチャンネル層５ｂにわたって酸化膜１０
を介して設けたゲート電極である。１２は層間絶縁膜で
ある。電流はソース電極９からゲート電極１１に対向す
るＰベース層６の表面の反転した層を通り、ドリフトチ
ャンネル層５ｂ、５ａ、ドレイン層２、ドレイン電極３
へと水平方向に流れる。この電流はゲート電極１１に与
える電圧を変えて制御する。Reference numeral 6 denotes a P base layer formed outside the drift channel layer 5b. Reference numeral 7 denotes a high-concentration n + semiconductor layer formed in the P base layer 6. 8 is a high concentration p + semiconductor layer formed in the P base layer 6. Reference numeral 9 denotes a source electrode common to the high-concentration n + semiconductor layer 7 and the high-concentration p + semiconductor layer 8. These parts may be collectively called a source. Reference numeral 10 denotes an oxide film. 11 denotes an oxide film 10 extending from the P base layer to the drift channel layer 5b.
Is a gate electrode provided through the gate electrode. Reference numeral 12 denotes an interlayer insulating film. The current flows from the source electrode 9 through the inverted layer on the surface of the P base layer 6 facing the gate electrode 11, and drift channel layers 5b and 5a, the drain layer 2, and the drain electrode 3
Flows horizontally to This current is controlled by changing the voltage applied to the gate electrode 11.
【０００４】図６は図５で示した横型ＤＭＯＳ ＦＥＴ
の平面図である。平面の構造は一般的にレーストラック
型をしており、中央部にドレイン層２、その外周部にド
リフトチャンネル層５ａ、５ｂ及びＰベース層６が配置
されている。この他にこの図には表されていないがゲー
ト電極１１等がある。従来の例では、ドレイン層２の上
に配線用のボンデイングパッド３を設けるので、ドレイ
ン層２を大きくしなければならず、そのため、ドレイン
層２の下面で接するドリフトチャンネル層５ａ、５ｂと
基板１との接合面積も大きくなり、必然的に出力端子間
容量が大きくなっていた。この出力端子間容量を低減さ
せるためには、接合面積を小さくする必要がある。接合
面積を小さくするためには、ドレイン電極４を取り付け
るボンデイングパッド部３に一定の面積を確保しつつド
レイン（ドレイン層及びドレイン電極部分）を細くする
必要がある。ドレインを細くしてゆくとドレイン端部の
曲率半径が小さくなり電界が集中してＤＭＯＳ ＦＥＴ
の耐圧がおお幅に低下する。図７は耐圧低下のシミュレ
ーション結果と実験データを示す。ドリフトチャンネル
長Ｌｄが２０μｍの場合ドレイン層２の曲率半径Ｒｄが
１０μｍになると耐圧は５０Ｖ近くも低下することが分
かる。FIG. 6 shows a lateral DMOS FET shown in FIG.
FIG. The planar structure is generally of a race track type, in which a drain layer 2 is provided at a central portion, and drift channel layers 5a and 5b and a P base layer 6 are provided at an outer peripheral portion thereof. In addition, although not shown in this figure, there is a gate electrode 11 and the like. In the conventional example, since the bonding pad 3 for wiring is provided on the drain layer 2, the drain layer 2 must be enlarged, and therefore, the drift channel layers 5a, 5b contacting the lower surface of the drain layer 2 and the substrate 1 And the junction area with the output terminal became large, and the capacitance between the output terminals was inevitably increased. In order to reduce the capacitance between output terminals, it is necessary to reduce the bonding area. In order to reduce the bonding area, it is necessary to make the drain (drain layer and drain electrode portion) thin while securing a fixed area in the bonding pad section 3 to which the drain electrode 4 is attached. As the drain becomes thinner, the radius of curvature at the end of the drain becomes smaller and the electric field concentrates, causing a DMOS FET
Withstand pressure is greatly reduced. FIG. 7 shows a simulation result of the breakdown voltage reduction and experimental data. It can be seen that when the drift channel length Ld is 20 μm and the radius of curvature Rd of the drain layer 2 becomes 10 μm, the breakdown voltage is reduced by nearly 50V.
【０００５】[0005]
【発明が解決しようとする課題】半導体リレーの出力端
子間容量を少なくするため、横型ＤＭＯＳ ＦＥＴの接
合面積を小さくしたい。接合面積を小さくするためには
ドレイン電極部以外のドレイン領域を細くする。ドレイ
ン領域を細くすると、ドレイン電極が無い側の端部の曲
率半径が小さくなりドレイン近傍に電界が集中してＤＭ
ＯＳ ＦＥＴの耐圧が大きく低下する。そこで本発明
は、横型ＤＭＯＳ ＦＥＴの出力端子間容量を少なくす
るとともに耐圧の低下を防止することを目的とする。In order to reduce the capacitance between output terminals of a semiconductor relay, it is desired to reduce the junction area of a lateral DMOS FET. To reduce the junction area, the drain region other than the drain electrode portion is made thin. When the drain region is made thinner, the radius of curvature at the end on the side where there is no drain electrode becomes smaller, and the electric field concentrates near the drain, causing DM
The withstand voltage of the OS FET is greatly reduced. Accordingly, it is an object of the present invention to reduce the capacitance between output terminals of a lateral DMOS FET and to prevent a decrease in withstand voltage.
【０００６】[0006]
【課題を解決するための手段】ＤＭＯＳ ＦＥＴの出力
端子間容量を少なくするためにドレインを細くしてゆ
く。するとドレイン端部の曲率半径が小さくなるので耐
圧がおお幅に低下する。この耐圧の低下はドレイン端部
での放電破壊によることが多い。そこで電界が集中する
端部のみドリフトチャンネル層の濃度を分ける境界を、
曲率半径が大きくなる方向つまりソース寄りへ移行させ
ることに着目した。半導体基板の一つの面にｎ+半導体
層とｐ+半導体層を含むＰベース層と、このＰベース層
に隣接し所定の耐電圧が得られるよう一定の幅をもった
ドリフトチャンネル層と、このドリフトチャンネル層に
接するドレイン層とを含みこの断面に直交する方向に延
長した横型ＤＭＯＳ ＦＥＴにおいて、前記ドリフト・
チャンネル層を二分しドレイン層に近い側の不純物濃度
をＰ−ベース層に近い側の濃度より濃くし、電界が特に
集中する延長方向の端部及び折り曲げ部の外側では前記
の不純物濃度が変化する境界を、外側へ移行させること
により電界の集中を緩和して耐圧の低下を防止すること
を特徴とする。In order to reduce the capacitance between output terminals of a DMOS FET, the drain is made thinner. Then, since the radius of curvature at the end of the drain becomes small, the breakdown voltage is largely reduced. This decrease in breakdown voltage is often due to discharge breakdown at the drain end. Therefore, the boundary that separates the concentration of the drift channel layer only at the end where the electric field is concentrated,
We focused on shifting to a direction in which the radius of curvature increases, that is, closer to the source. A P base layer including an n + semiconductor layer and a p + semiconductor layer on one surface of the semiconductor substrate, a drift channel layer adjacent to the P base layer and having a certain width so as to obtain a predetermined withstand voltage; A lateral DMOS FET including a drain layer in contact with the drift channel layer and extending in a direction orthogonal to the cross section;
The channel layer is bisected, and the impurity concentration on the side closer to the drain layer is higher than that on the side closer to the P-base layer, and the impurity concentration changes at the end in the extension direction where the electric field is particularly concentrated and outside the bent portion. By shifting the boundary to the outside, the concentration of the electric field is alleviated to prevent a decrease in breakdown voltage.
【０００７】[0007]
【発明の実施の形態】図１は本発明の横型ＤＭＯＳ Ｆ
ＥＴの構造を示す断面図である。１はｐ-の低濃度の半
導体基板である。２は半導体基板１の１つの面に所定の
幅をもって細長く形成しその幅よりも大きい径の円弧形
にした第１の端部と、前記の幅を径とする円弧形にした
第２の端部を持つｎ+高濃度のドレイン層である。この
部分を一括してドレインと言う。３はボンデイングパッ
ドである。４はドレイン電極である。ドレイン層２から
電極を引き出す接合部は損傷を防止するよう間隙は酸化
膜などを充填した構造にする。この上に配線用ボンデイ
ングパットを設ける。５はドリフトチャンネル層であ
る。ドレイン層２を中に配置し所定の耐電圧値が得られ
るようドレイン層２の縁から一定の幅（ドリフトチャン
ネル長Ｌｄと言う。）をもってドレイン層２と相似形に
形成する。このドリフトチャンネル層を二分してドレイ
ン層２側を５ｆで表し２ｎ-の不純物濃度とし、ソース
層６側を５ｇで表しｎ-の不純物濃度として、この不純
物が変化する境目に符号５ｈが付けてある。この濃くし
た５ｆ側の幅を以後ＮＤ１で表す。６はこのドリフトチ
ャンネル層の外側に形成したｐベース層である。FIG. 1 shows a horizontal DMOS F of the present invention.
It is sectional drawing which shows the structure of ET. 1 p - is a low concentration of the semiconductor substrate. Reference numeral 2 denotes a first end formed into an elongated shape having a predetermined width on one surface of the semiconductor substrate 1 and having an arc shape having a diameter larger than the width, and a second end formed into an arc shape having the diameter equal to the width. N + high-concentration drain layer having an end of This part is collectively called a drain. 3 is a bonding pad. 4 is a drain electrode. The junction at which the electrode is drawn from the drain layer 2 has a structure in which the gap is filled with an oxide film or the like so as to prevent damage. On this, a bonding pad for wiring is provided. 5 is a drift channel layer. The drain layer 2 is disposed inside and is formed in a shape similar to the drain layer 2 with a certain width (referred to as a drift channel length Ld) from an edge of the drain layer 2 so as to obtain a predetermined withstand voltage value. The drift channel layer is divided into two parts, and the drain layer 2 side is represented by 5f and has an impurity concentration of 2n − , and the source layer 6 side is represented by 5g and is an n − impurity concentration. is there. The increased width on the 5f side is hereinafter referred to as ND1. Reference numeral 6 denotes a p base layer formed outside the drift channel layer.
【０００８】７はＰベース層６の中に形成したｎ+半導
体層である。８はＰベース層６の中に形成したｐ+半導
体層である。９はｎ+半導体層７及びｐ+半導体層８に共
通のソース電極である。この部分を一括してソースと呼
ぶことがある。１０は酸化膜である。１１はＰベース層
から前記ドリフトチャンネル層５ｇにわたって酸化膜１
０を介して設けたゲート電極である。普通ポリシリコン
が用いられる。１２は層間絶縁膜である。Reference numeral 7 denotes an n + semiconductor layer formed in the P base layer 6. Reference numeral 8 denotes ap + semiconductor layer formed in the P base layer 6. Reference numeral 9 denotes a source electrode common to the n + semiconductor layer 7 and the p + semiconductor layer 8. This part may be collectively called a source. Reference numeral 10 denotes an oxide film. Reference numeral 11 denotes an oxide film 1 extending from the P base layer to the drift channel layer 5g.
0 is a gate electrode provided. Usually, polysilicon is used. Reference numeral 12 denotes an interlayer insulating film.
【０００９】電流はソース電極９からゲート電極１１に
対向するＰベース層６の反転した層を通り、ドリフトチ
ャンネル層５ｇ、５ｆ、ドレイン層２、ドレイン電極３
へと水平方向に流れる。この電流はゲート電極１１に与
える電圧を変えて制御する。図２は本願発明の横型ＤＭ
ＯＳ ＦＥＴの構造を示す平面図である。符号は図１と
共通である。ドレイン層２の端部ｃには電界が部分に集
中するのでドリフトチャンネル層５ｆ、５ｇの境界５ｈ
をソース９側に移すことを示している。図３は横型ＤＭ
ＯＳ ＦＥＴの他の実施例を示す平面図である。図１と
同じ構造であるが、小型化するために各層を折り曲げて
有効面積を拡げ導通時のオン抵抗を低減している。ま
た、折り曲げた端部ｃは図２の場合と同じであるが端部
ｄでは電界は曲率半径が小さいソース９側に集中するの
でドリフトチャンネル層５ｆ、５ｇの境界５ｈをドレイ
ン２側に移動させることを示している。A current flows from the source electrode 9 through the inverted layer of the P base layer 6 facing the gate electrode 11 and drift channel layers 5g, 5f, the drain layer 2, and the drain electrode 3
Flows horizontally to This current is controlled by changing the voltage applied to the gate electrode 11. FIG. 2 shows a horizontal DM according to the present invention.
FIG. 3 is a plan view illustrating a structure of an OS FET. The reference numerals are the same as those in FIG. At the end c of the drain layer 2, the electric field concentrates on the portion, so that the boundary 5h between the drift channel layers 5f and 5g
Is transferred to the source 9 side. Figure 3 is a horizontal DM
FIG. 9 is a plan view showing another embodiment of the OS FET. Although the structure is the same as that of FIG. 1, each layer is bent to increase the effective area and reduce the on-resistance at the time of conduction for miniaturization. The bent end c is the same as that of FIG. 2, but at the end d, the electric field is concentrated on the source 9 side having a small radius of curvature, so that the boundary 5h between the drift channel layers 5f and 5g is moved to the drain 2 side. It is shown that.
【００１０】次に図１により本発明の横型ＤＭＯＳ Ｆ
ＥＴの主要な動作を説明する。ドリフトチャンネル層の
中の不純物濃度の濃い部分５ｆをソース９側に寄せるこ
と、即ち境界５ｈをソース９側に寄せることにより、ド
リフトチャンネルのｎ -層と基板ｐ-層の接合からドレイ
ン層２側に向けた空乏層の伸びがこの境界５ｈで抑えら
れ、ドレイン層２への電界の集中を緩和するように働く
ので耐圧が向上する。図３の場合のようにソース９が内
側でドレイン層２が外側にある端部ｄでは、ソース９へ
の電界の集中を避けるためドリフトチャンネル層５ｆ、
５ｇの境界５ｈをドレイン層２側へ寄せた構造にする。
このようにドリフトチャンネル層の境界５ｈを移行させ
ることにより次の図に示すように耐圧が改善される。図
４はドリフトチャンネル層５ｆ、５ｇの境界５ｈの位置
（ＮＤ１）と耐圧の関係を示すシミュレーション図であ
る。（図２の場合） ドリフトチャンネル層の長さＬｄ＝５０μｍ、端部ｃの
曲率半径が５μｍのもので、ドリフトチャンネル層の濃
度の高い部分の長さＮＤ１を大きくしてゆくと耐圧が大
きくなることを示している。境界５ｈの位置が中央にあ
る場合（イで示すＮＤ１＝２５μｍの点）では耐圧が約
４８０Ｖであるのに対して、境界５ｈの位置をソース９
に移行させてゆくに従って約５３０Ｖまで上昇させるこ
とができる。尚、イの点の８９０Ｖは直線部のみで得ら
れる耐圧を示したものである。Next, referring to FIG. 1, the horizontal DMOS F of the present invention will be described.
The main operation of the ET will be described. Of the drift channel layer
Move the part 5f with a high impurity concentration in the source 9 side.
That is, by moving the boundary 5h toward the source 9, the
Lift channel n -Layer and substrate p-Dray from joining layers
The depletion layer elongation toward the p-layer 2 is suppressed at this boundary 5h.
Work to reduce the concentration of the electric field on the drain layer 2
Therefore, the breakdown voltage is improved. Source 9 is inside as in the case of FIG.
At the end d where the drain layer 2 is on the outside on the side
In order to avoid concentration of the electric field of the drift channel layer 5f,
The structure is such that the boundary 5h of 5g is shifted toward the drain layer 2 side.
In this way, the boundary 5h of the drift channel layer is shifted and
This improves the breakdown voltage as shown in the following figure. Figure
4 is the position of the boundary 5h between the drift channel layers 5f and 5g.
FIG. 9 is a simulation diagram showing a relationship between (ND1) and withstand voltage.
You. (In the case of FIG. 2) The length Ld of the drift channel layer is 50 μm,
With a radius of curvature of 5 μm, the density of the drift channel layer
The withstand voltage increases as the length ND1 of the high degree part increases.
It indicates that it will be easier. The position of the boundary 5h is in the center
(ND1 = 25 μm point indicated by a), the breakdown voltage is about
480V, while the position of boundary 5h is
To 530V as you move to
Can be. Note that 890 V at point a was obtained only from the straight line portion.
FIG.
【００１１】[0011]
【発明の効果】横型ＤＭＯＳ ＦＥＴのドレインを細く
することにより出力端子間容量を少なくすることが可能
になった。しかし、ドレインを細くしたことによりドレ
イン端部や折れ曲がり部に電界が集中するため耐圧の低
下が生じる。耐圧を主として負担するドリフトチャンネ
ル層を不純物濃度の異なる二層に分けて、その境目を端
部や折れ曲がり部の曲率半径が大きくなる方向に移動さ
せることによりこの耐圧の低下を防止することができ
た。また、不純物濃度の変化する境界の位置を変えるこ
とにより一定の範囲で任意の耐圧をもったＤＭＯＳ Ｆ
ＥＴを作りだすことができるようになった。According to the present invention, it is possible to reduce the capacitance between output terminals by making the drain of the lateral DMOS FET thin. However, as the drain is made thinner, the electric field is concentrated on the drain end and the bent portion, so that the breakdown voltage is reduced. The drift channel layer, which mainly bears the breakdown voltage, is divided into two layers having different impurity concentrations, and the boundary is moved in the direction in which the radius of curvature of the end portion or the bent portion is increased, thereby preventing the breakdown voltage from being lowered. . Also, by changing the position of the boundary where the impurity concentration changes, a DMOS F having an arbitrary withstand voltage within a certain range can be obtained.
You can now create ET.
【図１】本願発明のＤＭＯＳ ＦＥＴの構造を示す断面
図である。FIG. 1 is a sectional view showing a structure of a DMOS FET of the present invention.
【図２】本願発明のＤＭＯＳ ＦＥＴの構造を示す平面
図である。FIG. 2 is a plan view showing a structure of a DMOS FET of the present invention.
【図３】本願発明のＤＭＯＳ ＦＥＴの他の一例の構造
を示す平面図である。FIG. 3 is a plan view showing the structure of another example of the DMOS FET of the present invention.
【図４】ドリフトチャンネル層の長さと耐圧の関係を示
す図である。FIG. 4 is a diagram showing the relationship between the length of the drift channel layer and the breakdown voltage.
【図５】従来のＤＭＯＳ ＦＥＴの構造を示す断面図で
ある。FIG. 5 is a cross-sectional view showing a structure of a conventional DMOS FET.
【図６】従来のＤＭＯＳ ＦＥＴの構造を示す平面図で
ある。FIG. 6 is a plan view showing the structure of a conventional DMOS FET.
【図７】ドレインの曲率と耐圧の関係を示す図である。FIG. 7 is a diagram showing the relationship between the curvature of the drain and the withstand voltage.
１ 半導体基板 ２ ドレイン層 ３ ボンデイングパッド ４ ドレイン（層、電極） ５ａ、５ｂ、５ｆ、５ｇ ドリフトチャンネル層 ５ｃ、５ｈ ドリフトチャンネル層中の不純物変化の境
界 ６ Ｐベース層 ７ ｎ+半導体層 ８ ｐ+半導体層 ９ ソース（層、電極） １０ 酸化膜 １１ ゲート電極 １２ 層間絶縁膜Reference Signs List 1 semiconductor substrate 2 drain layer 3 bonding pad 4 drain (layer, electrode) 5a, 5b, 5f, 5g drift channel layer 5c, 5h boundary of impurity change in drift channel layer 6 P base layer 7 n + semiconductor layer 8 p + Semiconductor layer 9 source (layer, electrode) 10 oxide film 11 gate electrode 12 interlayer insulating film
Claims (1)
半導体層を含むＰベース層と、このＰベース層に隣接し
所定の耐電圧が得られるよう一定の幅をもったドリフト
チャンネル層と、このドリフトチャンネル層に接するド
レイン層とを含みこの断面に直交する方向に延長した横
型ＤＭＯＳ ＦＥＴにおいて、 前記ドリフト・チャンネル層を二分しドレイン層に近い
側の不純物濃度をＰ−ベース層に近い側の濃度より濃く
し、電界が特に集中する延長方向の端部及び折り曲げ部
の外側では前記の不純物濃度が変化する境界を、外側へ
移行させることにより電界の集中を緩和して耐圧の低下
を防止することを特徴とするＤＭＯＳＦＥＴ。An n + semiconductor layer and ap + are formed on one surface of a semiconductor substrate.
A P base layer including a semiconductor layer, a drift channel layer adjacent to the P base layer and having a certain width so as to obtain a predetermined withstand voltage, and a drain layer in contact with the drift channel layer, and including a drift layer perpendicular to the cross section. In the lateral type DMOS FET extended in the direction in which the drift channel layer is divided into two, the impurity concentration on the side near the drain layer is made higher than the impurity concentration on the side near the P- base layer, and the end in the extension direction where the electric field is particularly concentrated is increased. A DMOSFET characterized in that the boundary where the impurity concentration changes outside the bent portion is shifted to the outside, thereby alleviating the concentration of the electric field and preventing the withstand voltage from decreasing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8189230A JPH1041501A (en) | 1996-07-18 | 1996-07-18 | Dmos fet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8189230A JPH1041501A (en) | 1996-07-18 | 1996-07-18 | Dmos fet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1041501A true JPH1041501A (en) | 1998-02-13 |
Family
ID=16237778
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8189230A Pending JPH1041501A (en) | 1996-07-18 | 1996-07-18 | Dmos fet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1041501A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002314077A (en) * | 2001-02-28 | 2002-10-25 | Linear Technol Corp | High-voltage mos transistor |
| JP2005093696A (en) * | 2003-09-17 | 2005-04-07 | Matsushita Electric Ind Co Ltd | Lateral mos transistor |
| JP2006114768A (en) * | 2004-10-15 | 2006-04-27 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
| JP2009267211A (en) * | 2008-04-28 | 2009-11-12 | Panasonic Corp | Semiconductor device and method for manufacturing teh same |
-
1996
- 1996-07-18 JP JP8189230A patent/JPH1041501A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002314077A (en) * | 2001-02-28 | 2002-10-25 | Linear Technol Corp | High-voltage mos transistor |
| JP2005093696A (en) * | 2003-09-17 | 2005-04-07 | Matsushita Electric Ind Co Ltd | Lateral mos transistor |
| JP2006114768A (en) * | 2004-10-15 | 2006-04-27 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
| US8298898B2 (en) | 2004-10-15 | 2012-10-30 | Fujitsu Semiconductor Limited | Manufacturing method of semiconductor device with increased drain breakdown voltage |
| JP2009267211A (en) * | 2008-04-28 | 2009-11-12 | Panasonic Corp | Semiconductor device and method for manufacturing teh same |
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